KR20000057937A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to suppress the increase of a chip area by disposing mats having a short length in the column direction. CONSTITUTION: A first mat(M1, M2) has a memory cell block of a first number arranged in the column direction. A second mat(M3-M6) has a memory cell block of a second number larger than the first number and arranged in the column direction. A peripheral circuits(P1, P2) are connected to the first and second mats(M1, M2, M3-M6) and controls the circuit operations of the first and second mats(M1, M2, M3-M6). The first and second mats(M1, M2, M3-M6) are arranged in parallel to each other on a semiconductor substrate.

Description

Semiconductor Memory Device {SEMICONDUCTOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device in which memory cells are efficiently arranged on a chip to obtain a desired chip size.

1 is a plan view showing a schematic configuration of a semiconductor memory device.

The memory cells are arranged in a matrix by a predetermined number, word lines are connected to each row, bit lines are connected to each column, and constitute a memory cell block B. For example, in one block B, only 128 rows x 256 columns of memory cells are arranged, and a storage capacity of about 32K bits is obtained. Block B is arrange | positioned by a predetermined number in a line, and comprises mat M. FIG. The mat M is arranged in parallel with each other by having both ends. In FIG. 1, four blocks B11-B84 are arrange | positioned at four, and eight mats M1-M8 are formed. Therefore, blocks B11 to B84 having a storage capacity of 32K bits are arranged in 4x8 (32) blocks to obtain a storage capacity of 1M bits in total.

Peripheral circuits P1 and P2 are arranged in connection with mats M1 to M8. The peripheral circuits P1 and P2 include a decoder for designating a specific memory cell in the mats M1 to M8, an amplifier for writing and reading data to and from the designated memory cell. In each of the mats M1 to M8, memory cells in the blocks B11 to B84 share bit lines in the column direction and word lines in the row direction. As a result, when a row (word line) and a column (bit line) are designated in response to the address data, a specific memory cell is specified, and a write amplifier or sense amplifier is connected in a circuit to write or read data.

In a general semiconductor memory device, since data to be stored is normally 2 ⁿ bits (n is a natural number), the number of arrays of mats and the number of arrays of memory cells in each block are set to ²ⁿ . For this reason, as shown in FIG. 1, except that four blocks B11 to B84 are arranged in eight, four mats M1 to four are arranged by arranging eight identical 32 blocks B11 to B48 as shown in FIG. M4 is to be formed.

In the case of a semiconductor memory device, since the shapes of the memory cells are all equal in principle, when the number of arrangement of memory cells in a block is determined, the size of the block is also determined. At the same time, when the number of arrangements of mats is determined, the entire device, that is, the chip size, is determined. For this reason, the chip size is determined in accordance with the arrangement state of the blocks, and the chip size is similarly limited when the number of arrays of memory cells and the number of arrays of mats is limited to ²ⁿ .

For example, as shown in FIG. 1, when the 32 blocks B11 to B84 are arranged in eight by four, when the size in the row direction becomes too large, as shown in FIG. 2, four blocks B11 to B84 are eight by four. It is arranged in dog. However, as shown in Fig. 2, when four mats M1 to M4 are formed, the size in the row direction can be halved, but since the size in the column direction is doubled, it cannot fit the desired chip size. There may be cases.

In the above-described semiconductor memory device, peripheral circuits are constructed in accordance with the number of bits of the storage information. When storing 8 bits of information, the memory cells are arranged in each block B11 to B84 by an integer multiple of eight (e.g., 8 x 32 = 256 columns), and 8 in each of the memory cell rows in the peripheral circuits P1 and P2. Memory cells are selected in units so that only a predetermined number (for example, 32) of 8-bit information can be stored.

For this reason, the configurations of the peripheral circuits P1 and P2 are predetermined according to the number of bits of the storage information, and the information of the number of bits different from the setting cannot be stored in the memory cell as it is. Therefore, in the case of changing the number of bits of information to be stored, it is necessary to change the configuration of the peripheral circuits of the memory cells, and in the semiconductor memory device formed by integration, it is practically impossible to change the number of bits of the storage information.

The present invention is a semiconductor memory device comprising a mat in which a number of memory cells according to the number of bits of stored data are arranged in a matrix to form a block, and the blocks are arranged in a column direction, wherein the first number of memory cell blocks is a column. First mats arranged in a direction, a second number of memory cell blocks larger than the first number, and a second mat arranged in a column direction, respectively, connected to the first and second mats, respectively, so that the first and second mats are connected. A peripheral circuit for controlling the circuit operation of the mat, the first and second mats being disposed parallel to each other on a semiconductor substrate, and at least a part of the peripheral circuits disposed adjacent to an end of the first mat. It is characterized by one.

According to the present invention, by arranging two kinds of mats in length, the number of mats can be freely selected while the total number of blocks is adapted to the number of bits of the storage data. Then, by arranging the mat having a short length in the column direction to arrange the peripheral circuit in the empty area, the useless area can be eliminated and the increase in the chip area can be suppressed.

The present invention is a semiconductor memory device comprising a mat having a plurality of memory cells arranged in a matrix according to the number of bits of stored data, the blocks having a plurality of mats arranged in a column direction, and a first number of memory cell blocks. A first mat arranged in the column direction, a second mat having more than a first number of memory cell blocks arranged in the column direction, and connected to the first and second mats, respectively; Peripheral circuitry for controlling the circuit operation of the second mat, the first and second mats being disposed parallel to each other on a semiconductor substrate, and at the end of the first mat At least a portion of the peripheral circuit including a control circuit for arranging a spare memory cell row corresponding to the memory cell row in each block, and adjacent to an end of the first mat and controlling the operation of the spare memory cell column. To characterized in that the groping.

According to the present invention, two types of mats having different lengths are mixed and arranged, a spare block for relief is placed at an end of the first mat having a short length in the column direction, and the first mat is arranged in an empty area. By arranging the peripheral circuit including the control circuit of the preliminary block, the useless area can be eliminated and the increase in the chip area can be suppressed.

In addition, the present invention is a semiconductor memory device including a mat in which a plurality of memory cells are arranged in a matrix to form a block, and the blocks are arranged in a column direction, wherein 2n columns (n is an integer of 2 or more) arranged in parallel with each other. A plurality of column decoders arranged adjacent to one end of the mat of the 2n column, a plurality of column decoders for selecting a memory cell column in the mat, and spaced at two-column intervals between the mats of the 2n column, the row of memory cells in the mat A row decoder for selecting n columns and a peripheral circuit disposed adjacent to one end of the mat and controlling circuit operations of the mat, the column decoder and the row decoder, and the row decoders of the n columns Switching between the first operation mode in which one of the adjacent mats is selected and operated, and the second operation mode in which both of the mats adjacent to both sides are selected and operated. Is in.

According to the present invention, a row decoder for selecting both rows of memory cells is disposed between two columns of mats, and when one mat is selected from the row decoder, a predetermined number of bits of information can be stored, and both mats When is selected, the double bit number information can be stored.

1 is a plan view showing an example of a conventional semiconductor memory device.

2 is a plan view showing another example of a conventional semiconductor memory device.

3 is a plan view showing a first embodiment of a semiconductor memory device of the present invention.

4 is a plan view showing a second embodiment of the semiconductor memory device of the present invention.

Fig. 5 is a plan view showing a third embodiment of the semiconductor memory device of the present invention.

6 is a plan view showing a fourth embodiment of the semiconductor memory device of the present invention.

Fig. 7 is a plan view showing a fifth embodiment of the semiconductor memory device of the invention.

8 is a block diagram showing the configuration of a low decoder;

<Explanation of symbols for the main parts of the drawings>

P1, P2: peripheral circuit

B: block

M: Mat

3 is a plan view showing a first embodiment of the semiconductor memory device of the present invention. In this figure, similarly to FIG. 1, the case where 32 blocks B11-B84 are arrange | positioned and comprised is shown.

The memory cells are arranged in a matrix by a predetermined number, word lines are connected to each row, bit lines are connected to each column, and constitute a memory cell block B. For example, only 128 rows x 256 columns are arranged in memory cells, and blocks B11 to B84 each having a storage capacity of about 32K bits are formed. These blocks B11 to B84 themselves have the same configuration as the semiconductor memory device shown in FIG.

In the first mats M1 and M2, four blocks B11 to B14 and B21 to B24 are arranged in one row. In the second mats M3 to M6, one block of four blocks B31 to B64 is arranged, and two blocks of the blocks B71 to B84 are arranged in one row and arranged in total of six units. One end of these mats M1 to M6 is arranged in parallel with each other. In this embodiment, the first mats M1 and M2 are arranged in the center, and the second mats M3 to M6 are arranged on both sides of the first mats M1 and M2 so as to be symmetrical. Thus, when 1st and 2nd mat M1-M6 are arrange | positioned, the empty area | region for 2 blocks x 2 will be produced in the other end side of 1st mat M1, M2.

The 1st peripheral circuit P1 is arrange | positioned along the edge part of the side provided with the 1st and 2nd mat M1-M6, and the 2nd peripheral circuit P2 is the 2nd mat M4 which arises in the other end side of 1st mat M1, M2. , Is placed in the empty area between M5. The peripheral circuits P1 and P2 have functions equivalent to those of the peripheral circuits P1 and P2 shown in Fig. 1, and include a decoder, a light amplifier, a sense amplifier, and the like, and designate specific memory cells in each of the blocks B11 to B84. And to write or read data.

In each of the mats M1 to M6, in each of the blocks B11 to B84 in the same mat, each memory cell shares the bit line in the column direction in the same column. In each of blocks B11 to B84, each memory cell in the same block shares a word line in the row direction in the same row. As a result, in the 24 blocks in each of the mats M1 to M6, as in the memory device shown in Fig. 1, rows (word lines) and columns (bit lines) are designated in response to the address data.

In addition, for each of the blocks B71 to B74 and B81 to B84 in the second mats M3 to M6, the seventh and eighth mats M7 and M8 correspond to the memory devices shown in FIG. The selection becomes valid when these addresses are specified. At this time, the column addresses corresponding to the seventh mat M7 are replaced with the second mats M3 and M4, and the column addresses corresponding to the eighth mat M8 are replaced with the second mats M5 and M6. Therefore, from the outside of the apparatus, as shown in Fig. 1, data can be written and read out according to an address designation equivalent to that when eight mats M1 to M8 are arranged in parallel.

4 is a plan view showing a second embodiment of the semiconductor memory device of the present invention. In this figure, the first mats M1, M2 and the second mats M3 to M6 are the same as those in Fig. 3, in which blocks B11 to B84 in which a predetermined number of memory cells are arranged in a matrix are four and six, respectively. It is arranged.

The first mats M1, M2 and the second mats M3 to M6 have one end and are arranged in parallel with each other. In this embodiment, the second mats M3 to M6 are arranged at the center, and the first mats M1 and M2 are arranged on both sides of the second mats M3 to M6 so as to be symmetrical. Thus, when 1st and 2nd mat M1-M6 are arrange | positioned, it will be two places of the other end side of 1st mat M1, M2, and a space area for 2 blocks will respectively generate.

The first to third peripheral circuits P1 to P3 are disposed adjacent to the mats M1 to M6. These peripheral circuits P1 to P3 correspond to the first and second peripheral circuits P1 and P2 shown in FIG. 3. The first peripheral circuit P1 is disposed along one end provided with the first and second mats M1 to M6. The second and third peripheral circuits P2 and P3 are configured by dividing a circuit equivalent to the second peripheral circuit P2 shown in FIG. 3 into two parts, respectively, on both sides of the second mats M3 to M6, respectively. It is arranged in the blank area created on the other end side.

In this second embodiment, the arrangement of word lines and bit lines in each block is almost the same as in the first embodiment. That is, in the second embodiment, compared with the first embodiment, the positions in the row direction of the first mats M1 and M2 and the second mats M3 to M6 are reversed, and each block B11 to B84 in the same mat is inverted. In FIG. 2, each memory cell shares a bit line in the column direction in the same column, and also a word line in the row direction in the same row. The addressing for each memory cell is performed in the same manner as in the first embodiment.

In the semiconductor memory device described above, it is possible to set the arrangement of the mats irrespective of the number of bits of the storage data while allocating addresses corresponding to 2 ⁿ bits of storage data. Further, since the first mats M1 to M2 and the second mats M3 to M6 are arranged to be symmetrical with respect to the second peripheral circuit P2, the difference in the wiring for each block B11 to B84 with respect to the second peripheral circuit P2 is different. It is possible to reduce variations in operating characteristics caused. However, in the conventional semiconductor memory device, since the bit line or the like is formed by using aluminum wiring with low resistance, it is not necessary to arrange the mat symmetrically with respect to the peripheral circuit when the storage capacity is small.

According to the present invention, the memory cell block can be arranged in accordance with the desired chip size without being limited to the number of bits of the stored data. Therefore, the desired chip size can be obtained in a closer form, and an increase in the cost of the package can be prevented. In addition, even when the mats having different lengths are mixed, the empty area on the chip can be minimized, so that the increase in the chip area can be suppressed.

Fig. 5 is a plan view showing a first embodiment of the semiconductor memory device of the present invention. In this figure, the case where 32 blocks B11-B84 are arrange | positioned similarly to FIG. 1 is shown.

The memory cells are arranged in a matrix by a predetermined number, word lines are connected to each row, bit lines are connected to each column, and constitute a memory cell block B. For example, only 128 rows x 256 columns are arranged in memory cells, and blocks B11 to B84 each having a storage capacity of about 32K bits are formed. The spare memory cells are arranged in the row direction by the same number as the columns of the memory cells in the block B, and are arranged in the column direction by a predetermined number to constitute the spare block R. For example, only eight rows x 256 columns are arranged in the spare memory cells, and the spare blocks R1 and R2 can be configured to save eight rows of memory cells. The above blocks B11 to B84 and the spare blocks R1 and R2 themselves have the same configuration as the semiconductor memory device shown in FIG.

In the first mats M1 and M2, four blocks B11 to B14 and B21 to B24 are arranged in one row, and the spare blocks R1 and R2 are arranged at one end thereof, respectively. In the second mats M3 to M6, blocks B31 to B64 are arranged in one row of four, and two blocks B71 to B84 are arranged in one row and arranged in total of six units. These mats M1 to M6 have ends opposite to the side where the preliminary blocks are arranged, for example, and are arranged in parallel with each other. In this embodiment, the first mats M1 and M2 are arranged in the center, and the second mats M3 to M6 are arranged on both sides of the first mats M1 and M2 so as to be symmetrical. Thus, when 1st and 2nd mat M1-M6 are arrange | positioned, the empty area | region which is narrower than a 2 block x 2 area | region by a spare block will arise in the edge part of 1st mat M1, M2. In reality, while blocks B11 to B14 and B21 to B24 are constituted by 128 rows of memory cells, the spare blocks R1 and R2 are constituted by eight rows of spare memory cells, so the occupied area of the spare blocks R1 and R2 is larger than one block. It is small enough (in theory, 1/16), and the blank area never narrows.

The 1st peripheral circuit P1 is arrange | positioned along the edge part of the side provided with the 1st and 2nd mat M1-M6, and the 2nd peripheral circuit P2 is the 2nd mat M4 which arises in the other end side of 1st mat M1, M2 , Is placed in the blank area between M5. The peripheral circuits P1 and P2 have functions equivalent to those of the peripheral circuits P1 and P2 shown in Fig. 1, and include a decoder, a light amplifier, a sense amplifier, and the like, and designate specific memory cells in each of the blocks B11 to B84. And to write or read data. Here, the second peripheral circuit P2 includes a switching circuit for replacing each spare memory cell row of the spare blocks R1 and R2 with a memory cell row including defective points in each block B11 to B84. For example, a memory cell row including a plurality of physically cut fuses and a plurality of transistors operable by cutting each fuse, and cutting the cut portions of the fuses corresponding to the defective portions, thereby including the defective portions. The spare memory cells of the spare blocks R1 and R2 are replaced by one row unit.

In each of the mats M1 to M6, in each of the blocks B11 to B84 in the same mat, each memory cell shares the bit line in the column direction in the same column. In each of the blocks B11 to B84, each memory cell in the same block shares a word line in the row direction in the same row. Accordingly, in the 24 blocks in each of the mats M1 to M6, one of the blocks B11 to B84 is designated together with the rows (word lines) and columns (bit lines) in response to the address data, similarly to the memory device shown in FIG. do. At this time, if there is a bad place at a specific address and the fuse of the control circuit is blown according to the address, when a memory cell row including the address is designated, a specific column in the spare blocks R1 and R2 is selected instead.

In addition, the blocks B71 to B74 and B81 to B84 in the second mats M3 to M6 each correspond to the seventh and eighth mats M7 and M8 in the memory device shown in FIG. When these addresses are specified, the selection of each block B71 to B74 and B81 to B84 becomes valid. At this time, the column addresses corresponding to the seventh mat M7 are replaced with the second mats M3 and M4, and the eighth column addresses are replaced with the second mats M5 and M6. The same operations as the replacement of the defective points in the 24 blocks B11 to B64 described above are also performed for the two blocks B71 to B74 and B81 to B84 in the second mats M3 to M6, respectively. Therefore, from the outside of the apparatus, as shown in Fig. 1, data can be written and read out according to the same addressing as when eight mats M1 to M8 are arranged in parallel.

6 is a plan view showing a second embodiment of the semiconductor memory device of the present invention. In this figure, the first mats M1, M2 and the second mats M3 to M6 are the same as those in Fig. 5, in which blocks B11 to B84 in which a predetermined number of memory cells are arranged in a matrix are arranged in one column of four and six, respectively. The spare blocks R1 and R2 are arranged one by one on the first mats M1 and M2.

The first mats M1, M2 and the second mats M3 to M6 have one end and are arranged in parallel with each other. In this embodiment, the second mats M3 to M6 are arranged at the center, and the first mats M1 and M2 are arranged one by one on both sides of the second mats M3 to M6 so as to be symmetrical. Thus, when 1st and 2nd mat M1-M6 are arrange | positioned, the empty area | region which becomes narrower by 2 parts of preliminary blocks R1 and R2 rather than 2 blocks of each is provided in two places of the other end side of 1st mat M1, M2.

The first to third peripheral circuits P1 to P3 are disposed adjacent to the mats M1 to M6. These peripheral circuits P1 to P3 correspond to the first and second peripheral circuits P1 and P2 shown in FIG. 5. The first peripheral circuit P1 is disposed along one end provided with the first and second mats M1 to M6. The second and third peripheral circuits P2 and P3 are configured by dividing a circuit equivalent to the second peripheral circuit P2 shown in FIG. 5 into two parts, respectively, on both sides of the second mats M3 to M6, respectively. It is arranged in the blank area created on the other end side.

In this second embodiment, the arrangement of word lines and bit lines in each block is almost the same as in the first embodiment. That is, in the second embodiment, compared with the first embodiment, the positions in the row direction of the first mats M1 and M2 and the second mats M3 to M6 are reversed, and in each block B11 to B84 in the same mat, Each memory cell shares a bit line in the column direction in the same column and also a word line in the row direction in the same row. Therefore, the same addressing and remedy processing as in the first embodiment are performed.

In the semiconductor memory device described above, it is possible to set the arrangement of the mats regardless of the number of bits of the storage data while allocating addresses corresponding to 2 ⁿ bits of storage data. Further, since the first mats M1 to M2 and the second mats M3 to M6 are arranged to be symmetrical with respect to the second peripheral circuit P2, the difference in the wiring for each block B11 to B84 with respect to the second peripheral circuit P2 is different. It is possible to reduce variations in operating characteristics caused. However, in the conventional semiconductor memory device, since the bit line or the like is formed by using aluminum wiring with low resistance, it is not necessary to arrange the mat symmetrically with respect to the peripheral circuit when the storage capacity is small.

According to the present invention, the memory cell block can be arranged in accordance with the desired chip size without being limited to the number of bits of the stored data. At this time, the preliminary block for relief can be arrange | positioned at the edge part of the 1st mat with a short length of a column direction, and it controls for the relief process to the empty area which arises in the edge part of a 1st mat adjacent to this preliminary block. Peripheral circuits including circuits may be disposed. Therefore, the desired chip size can be obtained in a closer form while minimizing the increase in the chip area by minimizing the free area on the chip.

Further, by arranging the first mat and the second mat symmetrically with respect to the peripheral circuit, variations in the operating characteristics for each mat can be minimized and the circuit operation can be stabilized.

Fig. 7 is a plan view showing a first embodiment of the semiconductor memory device of the present invention. In this figure, the case where 32 blocks B11-B84 are arrange | positioned similarly to FIG. 1 is shown.

The memory cells are arranged in a matrix by a predetermined number, word lines are connected to each row, bit lines are connected to each column, and constitute a memory cell block B. For example, memory cells are arranged in 128 rows x 256 columns and constitute blocks B11 to B84 having a storage capacity of about 32K bits. These blocks B11 to B84 themselves have the same configuration as the semiconductor memory device shown in FIG.

In the first mats M1 and M2, four blocks B11 to B14 and B21 to B24 are arranged in one row. In the second mats M3 to M6, the blocks B31 to B64 are arranged in one row of four, and the two blocks in the blocks B71 to B84 are arranged in one row and composed of six units in total. One end of these mats M1 to M6 is arranged in parallel with each other. In this embodiment, the first mats M1 and M2 are arranged in the center, and the second mats M3 to M6 are arranged on both sides of the first mats M1 and M2 so as to be symmetrical. Thus, when 1st and 2nd mat M1-M6 are arrange | positioned, the empty area | region for 2 blocks x 2 will be produced in the other end side of 1st mat M1, M2. Here, since the blocks B71 to B84 arranged in the seventh and eighth columns in Fig. 1 are arranged in the second mats M3 to M6, the length in the row direction of the placement area is shorter than in the case of Fig. 1. . Therefore, even if the row decoders R1 to R3 described below are disposed between the mats M1 to M6, the arrangement area of each part can be prevented from being too wide in the row direction. Moreover, since the peripheral circuit P2 is arrange | positioned in the empty area | region formed in the edge part of 1st mat M1, M2, expansion of the length of a column direction is suppressed to the minimum.

The first column decoders C1 and C2 are disposed adjacent to one end of the first mats M1 and M2, and the first row decoder R1 is disposed between the first mats M1 and M2. The second column decoders C3 to C6 are disposed adjacent to one end of the second mats M3 to M6, and the second row decoders R2 and R3 are respectively between the second mats M3 and M4 and between the second mats M5 and M6. Is placed.

The 1st peripheral circuit P1 is arrange | positioned along the edge part of the side provided with the 1st and 2nd mat M1-M6, and the 2nd peripheral circuit P2 is the 2nd mat M4 which arises in the other end side of 1st mat M1, M2. , Is placed in the empty area between M5. The peripheral circuits P1 and P2 include write amplifiers, sense amplifiers, and the like, and write or read data to specific memory cells in each of blocks B11 to B84 designated by column decoders C1 to C6 and low decoders R1 to R3. It is configured to perform.

In each of the mats M1 to M6, in each of the blocks B11 to B84 in the same mat, each memory cell shares the bit line in the column direction in the same column. Accordingly, each column decoder C1 to C6 selects and activates a specific memory cell column in each of the mats M1 to M6 in response to the column selection information. For example, 256 rows of memory cells arranged in each of the mats M1 to M6 are selected in units of eight columns in response to column selection information. In each of the blocks B11 to B84, each memory cell in the same block shares a word line in the row direction in the same row. Each row decoder R1 to R3 selects and activates a row of memory cells for each block B11 to B84 in the mats M1 to M6 arranged on both sides. At this time, the row decoders R1 to R3 are configured to select either side in the first operation mode and simultaneously select both sides in the second operation mode. For example, 128 rows of memory cells arranged in each of the blocks B11 to B84 are selected one by one of the blocks B11 to B84 in the first operation mode, and adjacent to each of the blocks B1 to B84 in the second operation mode. Two rows are selected. At this time, if the row decoders R1 to R3 select eight rows of memory cells in each of the mats M1 to M6, 8-bit data is written or read in the first operation mode, and 16-bit data is read in the second operation mode. Writing or reading of data is performed.

In addition, for each of the blocks B71 to B74 and B81 to B84 in the second mats M3 to M6, the seventh and eighth mats M7 and M8 correspond to the memory devices shown in FIG. The selection becomes valid when these addresses are specified. At this time, the column addresses corresponding to the seventh mat M7 are replaced with the second mats M3 and M4, and the column addresses corresponding to the eighth mat M8 are replaced with the second mats M5 and M6. Therefore, from the outside of the apparatus, as shown in Fig. 1, data can be written and read out according to an address designation equivalent to that when eight mats M1 to M8 are arranged in parallel.

8 is a block diagram showing an example of the configuration of the row decoder R1. This figure shows a case where a specific column in a specific block is selected in response to the row selection signal RD and the block selection signal BD.

The row decoder R1 is composed of a row select circuit 1, a first block select circuit 2, a second block select circuit 3, and a 占 OR gate 4. In response to the row selection signal RD, the row selection circuit 1 generates selection signals S _O and S _E for selecting one of the memory cell rows within one block. For example, the selection signals S _O and S _{E which} constitute a row selection signal RD of 7 bits corresponding to 128 memory cell rows arranged in one block, and raise one of the 128 outputs according to the contents of the row selection signal RD. Create The first and second block selection circuits 2, 3 are provided so as to correspond to odd-numbered mats M1 and even-numbered mats M2, respectively, and respond to each of the selection signals S _O and S _E in response to a common block selection signal BD. By sorting, the selection signals S _{O1 to} S _O4 and S _{E1 to} S _E4 are supplied to the blocks B11 to B24. In addition, the second block selection circuit 3 is provided with a selection signal OE for selecting either odd or even columns, and the first block selection circuit 2 has an exclusive logical sum of the selection signal OE and the mode setting signal MS. This is given from the xOR gate 4. Here, the first and second block selection circuits 2 and 3 are configured to enable the operation in response to the logical sum of the selection signal OE and the mode setting signal MS and the selection signal OE itself. Accordingly, when the mode setting signal MS is at the high level, the selection signal OE is inverted and supplied to the first block selection circuit 2, so that the first and second block selection circuits 2, Alternatively, operate 3). In addition, when the mode setting signal MS is at the low level, the selection signal OE is supplied to the first block selection circuit 2 as it is, and according to the instruction of the selection signal OE, the first and second block selection circuits 2, 3 are used. ) At the same time. Therefore, in the second operation mode, it is possible to write and read data twice as many times as the first operation mode. The mode setting signal MS is a signal fixed at a high level or a low level, and once determined, it is not necessary to change it in most cases. Therefore, in the manufacturing process, the mode setting signal MS forms a fuse that can be physically cut or a nonvolatile memory cell in advance, and either the power supply potential or the ground potential is changed by cutting the fuse or writing to the memory cell. You can get it by making choices. In addition, even when a fuse, a memory cell, or the like is not formed, it is also possible to select a power supply potential and a ground potential by changing a part of the wiring. In this case, if the wiring of the uppermost layer is changed, most manufacturing processes can be made common.

In the above embodiment, the case where the first mats M1 and M2 and the second mats M3 to M6 are arranged to have one end is provided, but the empty areas are arranged to form outside the both ends of the first mats M1 and M2. You may also In addition, although the memory cell method is not specified, in such a semiconductor memory device, a static RAM, a dynamic RAM, various ROMs, etc. are mentioned as an example.

According to the present invention, by arranging two kinds of mats in length, the number of mats can be freely selected while the total number of blocks is adapted to the number of bits of the storage data. Then, by arranging the mat having a short length in the column direction to arrange the peripheral circuit in the empty area, the useless area can be eliminated and the increase in the chip area can be suppressed.

Claims (6)

In a semiconductor memory device comprising a mat in which a number of memory cells corresponding to the number of bits of stored data are arranged in a matrix, and the blocks are arranged in a plurality of columns in a column direction. A first mat having a first number of memory cell blocks arranged in a column direction; A second mat having a second number of memory cell blocks greater than the first number arranged in a column direction; Peripheral circuits connected to the first and second mats, respectively, to control circuit operation of the first and second mats. And And arranging the first and second mats in parallel with each other on the semiconductor substrate, and at least a part of the peripheral circuits adjacent to an end of the first mat. The method of claim 1, A plurality of the first and second mats are arranged symmetrically with respect to a straight line extending in the column direction. In a semiconductor memory device comprising a matrix in which a number of memory cells corresponding to the number of bits of stored data are arranged in a matrix to form blocks, and the blocks are arranged in a plurality of columns in a column direction. A first mat having a first number of memory cell blocks arranged in a column direction; A second mat having a second number of memory cell blocks greater than the first number arranged in a column direction; Peripheral circuits connected to the first and second mats, respectively, to control circuit operation of the first and second mats. And Arranging the first and second mats on a semiconductor substrate in parallel with each other, and a row of spare memory cells corresponding to the memory cell rows in each block of the first and second mats at an end of the first mat. And at least a portion of the peripheral circuit including a control circuit for controlling the operation of the preliminary memory cell columns adjacent to an end of the first mat. The method of claim 1, A plurality of the first and second mats are arranged symmetrically with respect to a straight line extending in the column direction. A semiconductor memory device comprising a plurality of memory cells arranged in a matrix to form a block, and the blocks include a plurality of mats arranged in a column direction. Mats of 2n rows (n is an integer of 2 or more) arranged in parallel with each other, A plurality of column decoders arranged adjacent to one end of the mat of the 2n column and selecting a memory cell column in the mat; An n-column decoder unit arranged at intervals of two columns in the gap between the 2n-column mats and for selecting memory cell rows in the mat; A peripheral circuit disposed adjacent one end of the mat and controlling circuit operations of the mat, the column decoder, and the row decoder; And The n-row row decoder switches between a first operation mode in which one of the mats adjacent to both sides operates and a second operation mode in which both of the mats adjacent to both sides are selected and operated. Memory device. The method of claim 1, The row decoder of the n column, A first block selection circuit connected to one of the mats adjacent to both sides and selecting a specific block in the mat; A second block selection circuit connected to the other side of the mat adjacent to both sides and selecting a specific block in the mat; A row selection circuit for selecting a specific memory cell column in a block selected by the first and second block selection circuits; Including, In the first operation mode, either one of the first and second block selection circuits operates, and in the second operation mode, both of the first and second block selection circuits operate. Device.