KR20080063874A - Semiconductor memory device - Google Patents

Abstract

A semiconductor memory device is provided to minimize area occupied by a fuse, as maintaining equal repair efficiency. A unit memory cell region includes a normal cell array and a number of redundancy columns. A number of fuse sets(300,400,500,600) correspond to each redundancy column, and program a column address of a repair target normal cell. An addressing unit selects the redundancy column corresponding to a fuse set by comparing an applied column address with a column address of the repair target normal cell programmed in the fuse sets. At least one fuse set shares a fuse corresponding to a most significant bit of the column address of the fuse sets.

Description

Semiconductor memory device {SEMICONDUCTOR MEMORY DEVICE}

1 is a block diagram illustrating some components of a general DRAM.

FIG. 2 is a block diagram illustrating a first fuse set of FIG. 1. FIG.

3 is a block diagram illustrating a first to fourth fuse set according to an embodiment of the present invention.

4 is a view for explaining the repair efficiency of the embodiment of FIG.

* Explanation of symbols for the main parts of the drawings

300: first fuse set 400: second fuse set

500: third fuse set 600: fourth fuse set

F_EN: Enable Fuse F_ADD <2: 9>: Repair Fuse

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly to a redundancy circuit for repairing defective cells.

In general, a large number of memory cells exist in a semiconductor memory device including a DRAM (Dynamic Random Access Memory (DRAM)), and if any one of these memory cells fails, the semiconductor memory device may fail. It is treated as defective. However, as the degree of integration of semiconductor memory devices increases gradually, there is a high probability that defects may occur only in a small number of cells, but disposing of the entire device as a defective product and discarding it is an inefficient way of lowering the yield of the product. It can be called a processing method. Therefore, a method of increasing the yield by replacing a defective cell by using a redundancy cell provided in the cell region in advance is commonly used. The circuit used at this time is a redundancy circuit.

The repair algorithm capable of repairing such defective cells can be divided into row repair and column repair. Among these, the column repair repairs a column line having a defective cell, and programs the column address of the defective cell into the fuse. Thus, when a defective cell is accessed through read and write operations, the programmed information is compared with the input column address to access the redundant cell instead of the defective cell. Here, among programming methods, a method of programming an address by laser cutting a fuse is most widely used.

1 is a block diagram for explaining a part of a configuration of a general DDR2 SDRAM.

FIG. 1 shows a quarter bank 10, a quarter bank 10, a column decoder 20, and first to fourth fuse sets 30, 40, 50, 60 is shown.

The quarter bank 10 is composed of normal cell arrays A, B, C, and D and redundancy columns E, F, G, and H, and is divided into 16 memory blocks BLOCK1 separated by row addresses. , BLOCK2, ... BLOCK15, BLOCK16).

The column decoder 20 decodes the column address ADD_COL <2: 9> and outputs a column selection signal YI that can access each normal cell array A, B, C, D. The column addresses ADD_COL <2: 9> and the addresses programmed in the first to fourth fuse sets 30, 40, 50, and 60, and compare the respective redundancy columns E, F, G, A column select signal (YI) signal for accessing H) is output. As a result, the column decoder 20 may access 2 ⁸ column select signal YI signals for accessing the normal cell arrays A, B, C, and D and redundancy columns E, F, G, and H for access. Outputs four column select signal (YI) signals.

The first to fourth fusesets 30, 40, 50, and 60 are for programming four repair target addresses per memory block BLOCK1, BLOCK2, ... BLOCK15, BLOCK16. Only 30 are shown.

Referring to FIG. 2, the first fuse set 30 includes a plurality of fuse blocks F_BLOCK1, F_BLOCK2, ... F_BLOCK15, F_BLOCK16 corresponding to each of the memory blocks BLOCK1, BLOCK2, ... BLOCK15, BLOCK16. do. Each of the fuse blocks F_BLOCK1, F_BLOCK2, ... F_BLOCK15, F_BLOCK16 includes a plurality of repair fuses F_ADD <2: 9> corresponding to the bits of the repair target column address ADD_COL <2: 9>. One enable fuse F_EN corresponding to the corresponding memory block is included.

Here, the plurality of repair fuses F_ADD <2: 9> are for programming an address of a repair target cell, and the enable fuse F_EN is a flag indicating whether to repair the memory blocks independently of each other. flag) to generate a signal. Therefore, the first fuse set 30 includes eight repair fuses F_ADD <2: 9> and one enable fuse F_EN corresponding to the column address ADD_COL <2: 9>. BLOCK1, BLOCK2, ... BLOCK15, BLOCK16).

That is, the first fuse set 30 is provided with 144 fuses of 9 (the number of fuses per fuse block) x 16 (the number of fuse blocks). The configuration of the second to fourth fuse sets 40, 50, and 60 is the same as that of the first fuse set 30, and the first to fourth fuse sets 30, 40, 50, and 60 are four. 576 fuses are provided (number of fuse sets) x 144 (number of fuses per fuse set). Since one bank is composed of four quarter banks, one bank is provided with 2304 fuses of 4 (number of quarters) x 576 (number of fuses per quarter). In this case, the total number of fuses considering the number of banks is N (where 'N' is a natural number). In the case of the bank DDR2 SDRAM, a total of 2304 × N fuses should be provided.

Recently, various electronic products have been developed in response to the demand for miniaturization, low power consumption, and low price. Semiconductor memory devices are also developing toward higher capacity, higher speed, lower power, and new functions. Therefore, in order to achieve high capacity and high integration of semiconductor memory devices, efforts to increase net die have been required.

In such a situation, repair for up to four defective cells per block of quarter bank 10 is possible, but requires a large number of fuses, which limits circuit layout and wiring connections. In addition, when the number of fuses is reduced to increase the net die, the repair efficiency decreases, which may affect the yield.

The present invention has been proposed to solve the above problems of the prior art, and has an object of providing a semiconductor memory device capable of minimizing the area occupied by a fuse while maintaining the same repair efficiency.

According to an aspect of the present invention for achieving the above object, a unit memory cell region including a normal cell array and a plurality of redundancy columns; A plurality of fuse sets corresponding to each redundancy column, for programming column addresses of a repair target normal cell; And addressing means for selecting the redundancy column corresponding to the fuse set by comparing an applied column address with a column address of a repair target normal cell programmed in the plurality of fuse sets, wherein at least one of the plurality of fuse sets is provided. The fuse set is provided with a semiconductor memory device that shares a fuse corresponding to a predetermined bit of the column address of another fuse set.

According to another aspect of the present invention for achieving the above object, a unit memory cell region including a normal cell array and a plurality of redundancy rows; A plurality of fusesets corresponding to each redundancy row and configured to program a row address of a repair target normal cell; Addressing means for selecting the redundancy row corresponding to the fuse set by comparing an applied row address with a row address of a repair target normal cell programmed in the plurality of fuse sets, wherein at least one of the plurality of fuse sets is provided; The fuse set is provided with a semiconductor memory device that shares a fuse corresponding to a predetermined bit of a row address of another fuse set.

Preferably, any one memory block in the unit memory cell area is divided into two areas by a predetermined bit (for example, the most significant bit), and when one or more defects occur in one area of the total number of defects that can occur in one memory block. The number of fuses for the shared fuse can be reduced by first repairing the first and second fuse sets that share the fuse in which the most significant bit is programmed, and repairing the remaining defects using the remaining fuse sets.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

3 is a block diagram illustrating first to fourth fuse sets 300, 400, 500, and 600 according to an exemplary embodiment of the present invention. For convenience of description, in order to obtain the same repair efficiency as that of the prior art (up to 4 repairs per block), the first to fourth fusesets 300 and 400 corresponding to four redundancy columns may also be used in the embodiment of the present invention. , 500, 600). In addition, each of the first to fourth fuse sets 300, 400, 500, and 600 corresponds to the first to fifth memory blocks BLOCK1, BLKOK2, BLKOK3, BLKOK4, and BLKOK5 among the 16 memory blocks. Only five fuse blocks F_BLOCK1, F_BLOCK2, F_BLOCK3, F_BLOCK4 and F_BLOCK5 are shown.

The first fuse set 300 includes a plurality of fuse blocks F_BLOCK1, F_BLOCK2, F_BLOCK3, F_BLOCK4, and F_BLOCK5 corresponding to each of the memory blocks BLOCK1, BLKOK2, BLKOK3, BLKOK4, and BLKOK5. Each fuse block F_BLOCK1, F_BLOCK2, F_BLOCK3, F_BLOCK4, and F_BLOCK5 includes a plurality of repair fuses F_ADD <2: 9> corresponding to each bit of the repair target column address ADD_COL <2: 9>. It is composed of one enable fuse F_EN corresponding to the memory block. In addition, the third fuse set 500 and the fourth fuse set 600 have the same configuration as the first fuse set 300.

The second fuse set 400 includes a plurality of fuse blocks F_BLOCK1, F_BLOCK2, F_BLOCK3, F_BLOCK4, and F_BLOCK5 corresponding to each of the memory blocks BLOCK1, BLKOK2, BLKOK3, BLKOK4, and BLKOK5. Each of the fuse blocks F_BLOCK1, F_BLOCK2, F_BLOCK3, F_BLOCK4, and F_BLOCK5 has a plurality of repair fuses corresponding to each bit of the 'ADD_COL <2: 8>' address among the repair target column addresses ADD_COL <2: 9>. (F_ADD <2: 8>) and an enable fuse F_EN corresponding to the memory block. The second fuse set 400 shares a 'F_ADD <9>' fuse in which an 'ADD_COL <9>' address is programmed in the first fuse set 300. Here, the 'ADD_COL <9>' address is an address bit that can divide one quarter bank from left to right using a most significant bit (hereinafter, referred to as "MSB"). As can be seen in the figure, the number of fuses of the second fuse set 400 is reduced by 'N' than conventional. Hereinafter, the repair efficiency will be described.

FIG. 4 is a diagram illustrating the number of cases where a repair target normal cell may occur in order to explain the repair efficiency of the embodiment of FIG. 3. For convenience of description, only five memory blocks BLOCK1, BLOCK2, BLOCK3, BLOCK4, and BLOCK5 of 16 memory blocks (BLOCK1, BLOCK2, BLOCK3, ..., BLOCK16) of one quarter bank are shown.

3 and 4, one quarter bank is an area in which the address 'ADD_COL <9>' is logical 'low' and an area in which the address 'ADD_COL <9>' is logical 'high'. Can be divided. This means division of one quarter bank by 'ADD_COL <9>' address, and it is also possible to distinguish areas by using address bits other than the 'ADD_COL <9>' address. For example, it is also possible to use the least significant bit (hereinafter, "LSB").

On the other hand, it will be described on the assumption that up to four repair target columns per memory block occurs.

Referring to the number of cases, as shown in the first memory block BLOCK1 of FIG. 4, when four repair target columns fail in a region where the address 'ADD_COL <9>' is logical 'low' (a ), And as shown in the second memory block BLOCK2, three repair target columns are generated in the region where the address' ADD_COL <9> 'is logical' low, and the address' ADD_COL <9> 'is logical' low '. One repair target column occurs in the region (b), and as shown in the third memory block BLOCK3, two repair target columns occur in the region where the address' ADD_COL <9> 'is logical' low. When two repair target columns occur in an area where the address' ADD_COL <9> 'is logical' low '(c), and as shown in the fourth memory block BLOCK4, the' ADD_COL <9> 'address is logical' One repair target column occurs in the 'low' area and the 'ADD_COL <9>' address is logical 'low' When three repair target columns occur in the in-region (d), and as shown in the fifth memory block (BLOCK5), four repair target columns occur in the region where the address' ADD_COL <9> 'is logical' high. (E)

First, since all four defective cells exist in (a), (b), (c), (d), and (e), the first to fourth fusesets 300, 400, 500, and 600 may be formed. The enable fuses F_EN of the first through fifth fuse blocks F_BLOCK1, F_BLOCK2, F_BLOCK3, F_BLOCK4, and F_BLOCK5 are cut to indicate that a column address programmed in the fuse is repaired. Here, the cutting is a high cutting method, and it is assumed that the fuse corresponding to the bit that is the logic 'high' is cut.

In the case of (a), the column addresses of four repair target normal cells are programmed in the first fuse block F_BLOCK1 of FIG. 3. That is, the plurality of repair fuses F_ADD <2 in which the column addresses of the repair target normal cells of the first fuse set 300, the third fuse set 500, and the fourth fuse set 600 correspond to each bit, respectively. : 9>). In this case, the 'F_ADD <9>' repair fuse of the first fuse set 300 is not cut, and the second fuse set 400 shares the 'F_ADD <9>' repair fuse of the first fuse set 300. As a result, only the 'F_ADD <2: 8>' repair fuse can be programmed to compare with the desired repair target column address.

In the case (b), the column addresses of four repair target normal cells are programmed in the second fuse block F_BLOCK2 of FIG. 3. That is, either one of the third fuse set 500 or the fourth fuse set 600-in FIG. 3, the 'F_ADD <9>' repair fuse of the third fuse set 500 is cut. 9> Program the column address of the repair target normal cell whose address is logical 'high' and program the column address of the repair target normal cell whose address is 'logic' low using the remaining fuse set. . Also, the 'F_ADD <9>' repair fuse of the first fuse set 300 is not cut, and the second fuse set 400 shares the 'F_ADD <9>' repair fuse with the first fuse set 300. As a result, only the 'F_ADD <2: 8>' repair fuse can be programmed to compare with the desired repair target column address.

In the case (c), the column addresses of four repair target normal cells are programmed in the third fuse block F_BLOCK3 of FIG. 3. That is, the 'F_ADD <9>' repair fuse of the first fuse set 300 is cut, and the 'ADD_COL <9>' address is logic 'high' in the first fuse set 300 and the second fuse set 400. The column address of the repair target normal cell is programmed, and the column of the repair target normal cell whose 'ADD_COL <9>' address is logical 'low' using the remaining third fuseset 500 and the fourth fuseset 600. The address may be programmed. Alternatively, the column address of the repair target normal cell having the 'ADD_COL <9>' address is logic 'high' may be programmed in the third and fourth fusesets 500 and 600. The column address of the repair target normal cell whose 'ADD_COL <9>' address is logic 'low' may be programmed using the remaining first fuse set 300 and the second fuse set 400. In FIG. 3, the repair fuse 'F_ADD <9>' of the first fuse set 300 is cut.

In the case of (d), the column addresses of four repair target normal cells are programmed in the fourth fuse block F_BLOCK4 of FIG. 3. That is, the 'F_ADD <9>' repair fuse of the first fuse set 300 is cut, and the 'ADD_COL <9>' address is logic 'high' in the first fuse set 300 and the second fuse set 400. The column address of the repair target normal cell may be programmed, and one of the remaining third fuseset 500 and the fourth fuseset 600 may program the column address of the repair target normal cell having a logic 'high', and the other One fuse set may be used to program the column address of a repair target normal cell whose address is 'logic' low. In FIG. 3, a repair fuse 'F_ADD <9>' is cut in the third fuse set 500 to program a column address of a repair target normal cell having an 'ADD_COL <9>' address as logic 'high'.

In the case of (e), the column addresses of four repair target normal cells are programmed in the fifth fuse block F_BLOCK5 of FIG. 3. That is, the 'F_ADD <9>' repair fuse of the first fuse set 300 is cut, and the 'ADD_COL <9>' address is logic 'high' in the first fuse set 300 and the second fuse set 400. The column address of the repair target normal cell may be programmed, and the remaining two logic 'high' column addresses of the repair target normal cell are programmed by using the remaining third fuse set 500 and the fourth fuse set 600. can do.

Preferably, any one memory block of one quarter bank 100 is divided into two regions by the most significant bit, and if one or more defects of the total number of defects that can occur in one memory block occur in one region, the highest priority is first. Repair may be performed using the first and second fuse sets 300 and 400 that share a 'F_ADD <9>' repair fuse in which a bit is programmed. The remaining defects may be repaired using the remaining fuse sets 500 and 600.

As described above, the second fuse set 400 shares the 'F_ADD <9>' repair fuse corresponding to the 16 memory blocks BLOCK1, BLOCK2,..., BLOCK16 of the first fuseset 300. Therefore, the same repair efficiency can be obtained in the second fuse set 400 without the 'F_ADD <9>' repair fuse. In addition, the net die may be increased due to the area N of the fuse that may be removed from the second fuse set 400. That is, the second fuse set 400 may reduce the 'F_ADD <9>' repair fuses corresponding to the 16 memory blocks BLOCK1, BLOCK2,..., And BLOCK16. Thus, four quarter banks can reduce 64 fuses, 16 (the number of fuses reduced in one quarter) x 4 (the number of quarter banks), for example, 512 with 8 (number of banks) x 64 for 8 banks of DDR2 SDRAM. Fuses can be reduced. In the present embodiment, one quarter bank is divided into sixteen memory blocks (BLOCK1, BLOCK2, ..., BLOCK16). However, when dividing more than that, the number of fuses can be increased.

In addition, in the embodiment of the present invention has been shown to reduce the 'Net Die' while ensuring a maximum of four repairs, configuration for ensuring a maximum of three repairs-in that case three fusesets and one of the fuseset Should share a fuse corresponding to a certain bit of the column address of the other fuse set-it is possible to reduce the number of fuses substantially the same as the embodiment, which is applicable to those skilled in the art Therefore, detailed description will be omitted.

In addition, in the configuration for guaranteeing five or more repairs, in which case there are five or more fuse sets, the regions are divided according to the column address of the normal cell to be repaired, and at least one fuse set among the plurality of fuse sets is different. By sharing fuses corresponding to at least one or more bits of the column address of the fuse set, the number of fuses can be reduced while ensuring the same repair efficiency as in the prior art.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment, the case of the column repair has been described as an example, but the present invention can be applied to the case of the low repair.

The present invention described above can increase the 'Net Die' by minimizing the fuse area without deteriorating the repair efficiency, it is also possible to obtain the effect of reducing the circuit layout and wiring constraints according to the fuse arrangement.

Claims (12)

A unit memory cell area including a normal cell array and a plurality of redundancy columns; A plurality of fuse sets corresponding to each redundancy column, for programming column addresses of a repair target normal cell; And addressing means for selecting the redundancy column corresponding to the fuse set by comparing an applied column address with a column address of a repair target normal cell programmed in the plurality of fuse sets. At least one fuse set among the plurality of fuse sets shares a fuse corresponding to a predetermined bit of a column address of another fuse set. The method of claim 1, The plurality of fuse sets, First and second fuse sets having a plurality of fuses corresponding to each bit of the column address; A third fuse set sharing the fuse corresponding to the predetermined bit with the first fuse set A semiconductor memory device comprising: a. The method of claim 1, And said predetermined bit is a most significant bit. The method of claim 1, And the unit memory cell region is a quarter bank region, and the quarter bank region includes a plurality of memory blocks separated by row addresses. The method of claim 4, wherein Each fuse set includes a plurality of fuse blocks corresponding to each of the plurality of memory blocks. The method of claim 5, Each of the plurality of fuse blocks, The plurality of repair fuses corresponding to each bit of the column address; And an enable fuse corresponding to each of the plurality of memory blocks. A unit memory cell area including a normal cell array and a plurality of redundancy rows; A plurality of fusesets corresponding to each redundancy row and configured to program a row address of a repair target normal cell; And addressing means for selecting the redundancy row corresponding to the fuse set by comparing an applied row address with a row address of a repair target normal cell programmed in the plurality of fuse sets. And at least one of the plurality of fusesets shares a fuse corresponding to a predetermined bit of a row address of another fuseset. The method of claim 7, wherein The plurality of fuse sets, First and second fuse sets having a plurality of fuses corresponding to each bit of the row address; A third fuse set sharing the fuse corresponding to the predetermined bit with the first fuse set A semiconductor memory device comprising: a. The method of claim 7, wherein And said predetermined bit is a most significant bit. The method of claim 7, wherein Wherein the unit memory cell region is a quarter bank region, and the quarter bank region includes a plurality of memory blocks separated by column addresses. The method of claim 10, Each fuse set includes a plurality of fuse blocks corresponding to each of the plurality of memory blocks. The method of claim 11, Each of the plurality of fuse blocks, The plurality of repair fuses corresponding to each bit of the row address; And an enable fuse corresponding to each of the plurality of memory blocks.

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