B7 B7 經濟部智慧財產局典工消费合竹扭印笮 五、發明說明（1 ) [發明所屬之技術領域] 本發明係關於在晶片上將記憶晶胞作高效率配置，而 可製得理想大小之晶片的半導體記憶裝置。 [習知技術] 第1圖係顯示半導體記憶裝置的概略構造之平面圖。 將一定數目之記憶晶胞（ffiemorycell)作行列配置，各 列各以字線（word 1 ine)連接，而各行也各以位元線接續， 構成記憶晶胞區塊（B1 ock)B。例如，每個區塊b若配置以 1 28列x256行之記憶晶胞’則各可得約32Kb之記憶容量。 每一定數目之區塊β配置於一行，即構成一區塊排 (Mat)Μ。這些區塊排Μ可以將兩端排列整齊、以多數行互 相平行配置。在第1圖中’區塊Bl 1至Β84是以每4個配 置成一區塊排共形成8排區塊排Ml至Μ8。因而，各具有 32Kb記憶容量之區塊Bl 1至B84，共配置有4x8 (32)個區 塊，故總計可得1 Mb之記憶容量。 鄰接各區塊排Ml至M8配置有周邊電路pi'p2。這些 周邊電路P1、P2含有用以指定各區塊排mi至内特定記 憶晶胞之解碼器（Decoder)’進行對應於各被指定記憶晶胞 之數據的寫入與讀取之放大器（Amp )等，各區塊排M i至 内的各區塊BU至B84内之記憶晶胞，在行（τ〇ι_η)方向 共有一位元線’在列（row )方向共有一字線。因此，回應位 址數據時而指定列；字線）及行位元線）時即可指定特定 之茫憶晶胞漣接寫八.故大器或讀取放太器進行數據之寫 八或讀取> 善.厂 ffj. 由；|J ♦，卞：—广、1 ... ' I . t ^ _, . .. LU..，iJ.I ! .. V - ' w ^ Hi rf—·ν^-ι^··^· -------------裝--------訂---------線 C請先閱讀背面之注意事項再填寫本頁) 1088 461079 ‘ A7 _____B7 _ 五、發明說明（2 ) (請先閲讀背面之注意事項再填寫本頁) 在一般的半導體記憶裝置之中，由於所記錄之數據通 常為2n bit (η為自然數），所配置之區塊排之數目，及各 區塊内所排列之記憶晶胞個數也設定成2的整數次方。所 以’如第1圖所示，區塊B1〗至B84是以每行各4配置成 8行；或如第2圖所示，相同的32個區堍B11至B84是以 每排各8配置成4排的區塊排Ml至M4 % 在半導體記憶裝置中，由於所有的記憶晶胞之形狀原 則上都均等之故，一旦各區塊内的記憶晶胞之排列數目決 定之後’區塊的大小也就一定。同時，一旦區塊排之排列 數目決定之後’裝置全體，亦即晶片大小，也就已經決定。 因此’晶片大小就取決於區塊的排列狀態；當記憶晶胞之 排列數目及區塊排之排列數目受限於2的整數次方時，晶 片大小也就同受限制。 經濟部智慧財產局員工消費合作社印製 例如，如第1圖所示，若將32個區塊B11至B84以每 行4個配置成8行、則列（Row)方向尺寸過大，於是如第2 圖改將區塊B11至B84以每行8個配置成4行。然而，如 第2圖所示，形成4排的區塊排Ml至M4時則列（Row)方 向之尺寸固可減半，但是行（Column)方向之尺寸卻成為2 倍’依然無法達到理想的晶片大小。 而且’在上述半導體記憶裝置中，構築有對應於記博 資訊的位元數之周邊電路》當所記憶為8位元之資訊時， 於各區塊Β11至Β84内其記憶晶胞是以8之整數倍的行數 配置（例如8x32 = 2 56行），而周邊電路Pi、Ρ2由每列記憶 晶胞内選擇8個單位的記憶晶胞，而可記憶一定數目（例如 本紙張尺度適用令國國家標準（CNS)A4規格（210 x 297公爱） 2 311088 B7 B7 經濟部智慧財產局員工消費合"":::···'''·-·· 五、發明說明（3 ) 32個）的8位元資訊》 因此’周邊電路P1、P2之結構’已預先取決於纪慎資 訊之位元數，對於與所設定位元數不同的資釩，就無法直 接記錄於記憶晶胞。是故，當所欲記錄之資訊的位元數變 更時，記憶晶胞的周邊電路的結構也非跟著變更不可；而 於經積體化所構成的半導髏記憶裝置，實際上，記憶資訊 的位元數之變更是不可能的。 [發明之概要] 本發明係含有將對應於記憶數據的位元數之數目的記 憶晶胞作行列配置成區塊，再以該區塊於行方向多數排列 而成的區塊排之半導體記憶裝置；包括有第1個數目的記 憶胞區塊於行方向排列之第1區塊排，及具有大於第丨個 數目的記憶晶胞區塊於行方向排列而成第2區塊排，及各 連接上述第1之區塊排及第2之區塊排、以控制其電路動 作之周邊電路：上述第丨之區塊排及第2之區塊排於半導 體基板上相互平行配置，而且，與上述第丨之區塊排的末 端相鄰配置有上述周邊電路的至少一部份為其特徵。 依本發明，因有兩種不同長度之區塊排混合配置在 使全體區塊數適合於記憶數據之位元數的同時區塊排的 數目也能自由選擇4當行方向所配置之區塊排較短的時 候‘其空白區域可以配置周邊電路而不會浪費區娀雨能 抑制晶片面積之增大。 是故’本發明係含有將對應於記憶教據之位元數的齡 a之i己德晶胞.作行朽配置兩成區塊^ : h:: H n决區魂铲 (請先閱讀背面之注意事項再填寫本頁) '装--------訂---------線------- A7 4 6 1 0 7 9 ______B7___ 五、發明說明（4 ) 行方向多數排列而成的區塊排（mat)之半導體記憶裝置；具 備將第一數目的記憶晶胞區塊於行方向排列之第1區塊 排’及以大於第1數目的第2數目之記憶晶胞區塊於行方 向排列之第2區塊排，及各連接於上述第1區塊排及第2 區塊排、以控制其電路動作之周邊電路；將上述第1區塊 排及第2區塊排區塊排於半導體基板上相互平行配置，同 時，於上述第1區塊排的端部配置有對應於上述第1區塊 排及第2區塊排的各區塊内之記憶晶胞列而設的預備記憶 晶胞列，並且，與上述第1區塊排的端部相鄰配置有包含 控制上述預備記憶晶胞行的動作之控制電路的上述周邊電 路之至少一部份為其特徵。 依本發明，因有長度不同的兩種區塊排混合配置，可 於行方向較短的第1區塊排的端部配置用來補救不良部位 之預備區塊，於配置第1區塊排後所空出的空白區域配置 包含預備區塊之控制電路的周邊電路，以清除閒置區域並 抑制晶片面積之增大。 再者，本發明是含有將多數的記憶晶胞作行列配置而 成的區塊，將這些區塊於行方向以多數排列成區塊排的半 導體記憶裝置：具備相互並列配置的2η行（η是大於2之 整數）的區塊排，及與上述2ri行的區塊排相鄰配置而用以. 選擇上述區塊排内之記憶晶胞行的多數行解碼器（Column Decoder) *及配置於上述2n行的區塊排每隔2行之間隙 而用以選擇上述區塊排内之記憶晶胞列的η行之列解碼器 (Row Decoder)，及與上述區塊排之一端相鄰配置的控制上 --------------東·11!1訂--------- 'IJ (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） 4 311088 A7 A7 經濟部智慧財產局_工消費合：c-fi-! 五、發明說明（5 述區塊排、上述行解 . 碼15以及上述列解碼器之電路動作的 周邊電路；而以上述 ^ ^ 订的列解碼器將選擇兩側相鄰的區 塊排之任一而動作的第 動作模式與選擇兩側相鄰的區塊 排之兩者而動作的第2動作模式予以切換者。 :本發明’於2行的區塊排之間配置有選擇兩區塊排 ，晶胞列之列解碼器；由列解碼器選擇其一之區塊排 時，可以記錄所設定的位开舡 > 农〜 鄉 叼位疋數之資訊，而選擇兩者之區塊 排時，則可以記錄二倍的位元數之資訊。 [圖式之簡單說明] 第1圖顯示慣用半導體記憶裝置之一例的平面圖。 第2圖顯示慣用半導體記憶裝置之另—例的平面圖。 第3圖顯示本發明之半導體記憶裝置的第1施形態 之平面圖。 第4圖顯示本發明之半導體記憶裝置的第2實施形態 之平面圖。 第5圊顯示本發明之半導體記憶裝置的第3實施形態 之平面圖。 第6圖顯示本發明之半導體記憶裝置的第4實施形態 之平面圖。 笫7圖顯示本發明之半導體記憶裝置的第5實施形態 之平面圖。 第8圖顯示列解碼器之構造的區塊圖 元件符號之說明 區塊B7 B7 Consumption by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumption and Contortion Printing 5. Description of the Invention (1) [Technical Field to Which the Invention belongs] The present invention relates to the efficient configuration of memory cells on a wafer, which can be made ideally. Semiconductor memory device of large and small chips. [Conventional Technology] FIG. 1 is a plan view showing a schematic structure of a semiconductor memory device. A certain number of memory cells (ffiemorycells) are arranged in rows and columns, and each column is connected by a word line, and each row is connected by a bit line to form a memory cell block (B1 ock) B. For example, if each block b is configured with a memory cell of 128 rows x 256 rows, each can obtain a memory capacity of about 32 Kb. Each certain number of blocks β is arranged in a row, which constitutes a block array (Mat) M. These block rows M can be neatly arranged at both ends and arranged in parallel with most rows. In the first figure, 'blocks Bl 1 to B84 are arranged in a block row every 4 in total to form 8 rows of block rows M1 to M8. Therefore, each of the blocks Bl to B84 having a memory capacity of 32Kb is configured with 4x8 (32) blocks in total, so a total memory capacity of 1 Mb can be obtained. Adjacent block rows M1 to M8 are provided with peripheral circuits pi'p2. These peripheral circuits P1 and P2 contain decoders (Decoders) for designating each block row mi to a specific memory cell within the amplifier (Amp) for writing and reading data corresponding to each specified memory cell. Wait, the memory cells in each block BU to B84 in each block row Mi to have a single bit line in the row (τ〇ι_η) direction and a word line in the row (row) direction. Therefore, when responding to the address data, you can specify the columns; word lines) and row bit lines). You can specify a specific memory cell to write and write. Read > 善. 厂 ffj. By; | J ♦, 卞: — 广, 1 ... 'I. T ^ _,. .. LU .., iJ.I! .. V-' w ^ Hi rf— · ν ^ -ι ^ ·· ^ · ------------- install -------- order --------- line C, please read the back first Please note this page before filling in this page) 1088 461079 'A7 _____B7 _ V. Description of the invention (2) (Please read the notes on the back before filling this page) In general semiconductor memory devices, the recorded data is usually 2n bit (η is a natural number), the number of arranged block rows, and the number of memory cells arranged in each block are also set to an integer power of two. So 'as shown in Figure 1, blocks B1 to B84 are arranged into 8 rows with 4 in each row; or as shown in figure 2, the same 32 zones are arranged with B11 to B84 arranged in 8 rows. 4 rows of blocks M1 to M4% In semiconductor memory devices, since the shape of all memory cells is equal in principle, once the number of memory cells in each block determines the number of blocks The size will be constant. At the same time, once the number of block rows is determined, the entire device, that is, the chip size, has also been determined. Therefore, the size of the wafer depends on the arrangement of the blocks; when the number of memory cell arrays and the number of block arrays are limited to an integer power of two, the size of the wafer is also limited. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. For example, as shown in Figure 1, if 32 blocks B11 to B84 are arranged in 8 rows with 4 rows, the size of the row direction is too large. 2 The map changes the blocks B11 to B84 into 8 rows with 8 rows each. However, as shown in Figure 2, when the four-row block rows M1 to M4 are formed, the size in the row direction can be halved, but the size in the row direction is doubled. Chip size. "In the above-mentioned semiconductor memory device, a peripheral circuit corresponding to the number of bits of the blog information is constructed." When the information is stored as 8-bit information, the memory cell in each block B11 to B84 is 8 The number of rows is configured as an integer multiple (for example, 8x32 = 2 56 rows), and the peripheral circuits Pi and P2 can select a unit of memory cells of 8 units in each column of the memory cell, and a certain number can be stored (for example, this paper applies National Standard (CNS) A4 Specification (210 x 297 Public Love) 2 311088 B7 B7 Employee Consumption of Intellectual Property Bureau of the Ministry of Economic Affairs " " ::: ... ) 32 bits of 8-bit information "Therefore, the 'structure of peripheral circuits P1 and P2' already depends on the number of bits of discreet information in advance, and it is impossible to directly record the memory of the vanadium with a number of bits different from the set Unit cell. Therefore, when the number of bits of information to be recorded is changed, the structure of the peripheral circuit of the memory cell must also be changed accordingly. In the semi-conductive memory device formed by integration, in fact, it stores information Changing the number of bits is not possible. [Summary of the Invention] The present invention is a semiconductor memory including a block array in which a number of memory cells corresponding to the number of bits of memory data are arranged in rows and rows, and the block is mostly arranged in the row direction. Device; a first block row having a first number of memory cell blocks arranged in a row direction, and a second block row having a greater number of memory cell blocks arranged in a row direction, and Peripheral circuits that are connected to the first block row and the second block row to control the circuit operation: the first block row and the second block row are arranged in parallel with each other on a semiconductor substrate, and, It is characterized in that at least a part of the peripheral circuit is arranged adjacent to the end of the first block row. According to the present invention, since there are two types of block rows with different lengths, the total number of blocks is suitable for memorizing the number of data bits, and the number of block rows can be freely selected. When the row is short, the peripheral area can be configured with peripheral circuits without wasting the area. Rain can suppress the increase of the chip area. That's why the present invention contains a unit cell with the age of a corresponding to the number of bits of memory data. It is configured into two blocks ^: h :: H n Decision Zone Shovel (Please read first Note on the back, please fill in this page again) 'Installation -------- Order --------- Line ------- A7 4 6 1 0 7 9 ______B7___ 5. Description of the invention ( 4) a semiconductor memory device of a block row (mat) arranged mostly in the row direction; having a first block row in which the first number of memory cell blocks are arranged in the row direction; 2 number of memory cell blocks are arranged in the row direction of the second block row, and peripheral circuits connected to the above first block row and the second block row to control its circuit operation; The block row and the second block row are arranged parallel to each other on the semiconductor substrate, and at the same time, each end corresponding to the first block row and the second block row is arranged at the end of the first block row. A preliminary memory cell row is provided for the memory cell row in the block, and an upper part including a control circuit for controlling the operation of the preliminary memory cell row is arranged adjacent to the end of the first block row. At least a portion of its characteristic peripheral circuit. According to the present invention, since there are two types of block rows with different lengths, the first block row with a shorter row direction can be arranged at the end of the first block row to remedy the defective part, and the first block row can be arranged. The vacant blank area is configured with peripheral circuits including the control circuit of the preparatory block to clear the idle area and suppress the increase of the chip area. Furthermore, the present invention is a semiconductor memory device including a plurality of memory cells arranged in rows and columns, and a plurality of these blocks are arranged in a row in a row direction: a semiconductor memory device having 2η rows (η Is an integer greater than 2), and is arranged adjacent to the above 2ri row block row. It is used to select the majority of the column decoders of the memory cell row in the above block row (Column Decoder) * and configuration Row Decoder for selecting η rows of the memory cell row in the block row at intervals of 2 rows in the block row of the 2n row and adjacent to one end of the block row Configuration control -------------- Dong · 11! 1 Order --------- 'IJ (Please read the precautions on the back before filling this page) Ministry of Economy The paper size printed by the Intellectual Property Bureau employee consumer cooperative is applicable to the Chinese National Standard (CNS) A4 specification (210x297 mm) 4 311088 A7 A7 Intellectual Property Bureau of the Ministry of Economic Affairs_Industrial and Consumer Cooperation: c-fi-! V. Description of the invention (5 The block row, the above row solution. Code 15 and the peripheral circuits of the above column decoder circuit operation; The decoder switches between the second operation mode in which one of the adjacent block rows on both sides operates and the second operation mode in which both the adjacent block rows on both sides operate.: This invention '于The two rows of block rows are provided with a selection of two block rows, a unit column decoder; when the column decoder selects one of the block rows, the set bit opening can be recorded. ≫ Farm ~ Township Information about the number of bits, and when the block arrangement of the two is selected, the information of twice the number of bits can be recorded. [Simplified description of the figure] Figure 1 shows a plan view of an example of a conventional semiconductor memory device. Fig. 2 is a plan view showing another example of a conventional semiconductor memory device. Fig. 3 is a plan view showing a first embodiment of the semiconductor memory device of the present invention. Fig. 4 is a plan view showing a second embodiment of the semiconductor memory device of the present invention. Figure 5 shows a plan view of a third embodiment of the semiconductor memory device of the present invention. Figure 6 shows a plan view of a fourth embodiment of the semiconductor memory device of the present invention. Figure 7 shows a view of the semiconductor memory device of the present invention. 5 a plan view of the form of embodiment. FIG. 8 a block diagram of an explanatory block symbol element is constructed in the column decoder
’I- ' ^ '·· | 1111 | III -艾適弔Φ g國家標：选 _________ I___---------. ________ (請先閱讀背面之注意事項再填寫本頁) i 6 1079 A7 __-__B7______ 五、發明說明（6 ) Μ 區塊排 PI、Ρ2 周邊電路 [發明之實施形態] (請先閱讀背面之注意事項再填寫本頁) 第3圖係顯示本發明之半導體記憶裝置的第1實施形 態之平面圖。在此圖令，如第1圖，顦示由32個區塊Β11 至Β84配置而構成之情。 將一定數目的記憶晶胞作行列配置，每列各連接字元 線、每行各連接位元線，構成記憶晶胞區塊Β。例如’將 記憶晶胞以128列χ256行配置，構成各具約32Kb之記憶 容量的區塊Bl 1至Β84»這些區塊B11至B84本身是與第1 圖所示之半導體記憶裝置具有相同的結構。 第1之區塊排Μ卜M2是將區塊B11至β14、Β21至B24 各以4個一行配置而成；第2之區塊排M3至Μ6是以區塊 Β31至Β64各以4個一行配置，再將區塊Β71至Β84之内 的2個配置於一行；合計配置成6個單位》將這些區塊排 Ml至Μ6的一端對齊而互相平行排列。在本實施形態中， 經濟部智慧財產局員工消費合作社印製 第1之區塊排配置於中央、第2之區塊排M3至M6則成左 右對稱，各以2區塊排配置於第1之區塊排Ml、M2之兩側。 如此地配置第1及第2之區塊排Ml至M6，可於第1之區 塊排Ml、M2之另一端，空出2區塊x2之空白區域。 第1周邊電路P1是沿第1區塊排及第2區塊排之區塊 排Ml至M6之對齊的一端而配置。第2周邊電路P2則是配 置於第1區塊排Ml、M2之另一端所形成之第2區塊排M4、 M5之間的空白區域。這些周邊電路P1、P2’與第1圖所示 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 2犯公釐） 6 311088 經 濟 智 慧 財 產 局 消 費 合 η Λ7 —--- Β7__ 五、發明說明（7 ) 之周邊電路Ρ1、Ρ2具有相等的機能，含有解碼器、寫入放 大器、讀取放大器等，可指定各區塊β11至Β84内的特定 記憶晶胞，作數據之寫入與讀取。 各區塊排Ml至Μ6，於同一區塊排内之各區塊Bll至 B84,各記憶晶胞於同一行在行方向共有一位元線。且各區 塊Bl 1至B84於同一區塊内之各記憶晶胞，其同一列於列 方向共有一字元線。由此，於各區塊排M1iM6内之24 個區塊，如第丨圖所示之記憶裝置，回應位址數據而指定 列（字線）及行（位元線）。 第2之區塊排诞3至对6内之各2個（χ4行）之區塊β7ΐ 至Β74、Β81至Β84，係與第1圖之記憶裝置中的第7、8 排之區塊排Μ7、Μ8對應，經指定其位址後，選擇才有效， 此時與第7條區塊排Μ7對應之行位址為第2之區塊排趵、 Μ4所取代，與第8條區塊排似對應之行位址為第2之區 塊排Μ5、Μ6所取代。因而，從裝置之外部，可以藉與如第 1圖所示之將8條區塊排Ml至《8並排配置時相當之位址 指定，得以進行數據之寫入及讀取。 第4圖為顯示本發明之半導體記憶裝置之第2實施形 態的平面圖《在此圖中，第i之區塊排M 1、M2及第2之區 塊排M3至恥，與第3圖相同·係將—定數目的記憶晶胞 以行列配置成區塊Bil至B84，再各將其4個或6個配置 為-··區塊排。 將第1之區塊排Μ丨Μ 及第？之區塊排㈣至n於 端對齊後相互平行排列本實施形態是將第2之區塊排 --------------裝-------—訂-------- (請先閱讀背面之注意事項再填寫本頁) -¾ 6 4 07 9 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明（8) M3至M6配置於中央’第1之區塊排Ml、M2則左右對稱， 於第2之區塊排M3至M6的兩側各配置一區塊排。如此配 置第1及第2之區塊排Ml至M6之後’在第1之區塊排Ml、 M2之另一端的兩處，分別產生相當於兩個區塊之空白區 域。 第1至第3周邊電路P1至P3是與各區塊排Ml至M6 相鄰而配置。這些周邊電路至P3，是相當於第3圖所 示之第1及第2周邊電路P1、P2。第1周邊電路P1是沿 第1及第2之區塊排Ml至M6之對齊的一端而配置。至於 第2及第3周邊電路P2、P3’是相當於將如第3圖所示之 第2周邊電路一分為二而構成，而分別配置於第2之區塊 排M3至M6之兩側、於第1之區塊排Ml、M2的另一端所產 生之空白區域。 在本第2實施形態中，各區塊内之字線及位元線的配 置與第1實施形態大致相同亦即，於第2實施形態中， 若與第1實施形態比較，則只有第1之區塊排、M2及第 2之區塊排M3至Μ6之列方向的位置反轉，同一區塊排内 之各區塊Bl 1至Β84的各記憶晶胞，以同一行於行方向共 有一位元線，且以同一列於列方向共有一字元線。並且對 各記憶晶胞之位址指定’是以相同於第1實施形態之方式 為之。 以上的半導體記憶裝置中，在進行對應於2η位元之記 憶數據的位址之分配的同時，可無關於記憶數據之位元數 而設定區塊排之配置。而且相對於第2周邊電路Ρ2的第1 --------------Μ·------ 訂--------線· — (請先閱讀背面之注意事項再填窵本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公爱） 8 311088 經濟部智慧財產局員H消費合作社印踅 A7 B7 五、發明說明（9 ) 之區塊排Mb M2及第2之區塊排M3至M6排成左右對稱配 置’對應於第2周邊電路P2之各區塊Bii至B8 4的每一 3己 線差所導致之動作特性變異也可以縮小。但是，通常之半 導體記憶裝置因係使用電阻小的鋁配線而形成位元線，故 記憶容量小時’無須將區塊排對於周邊電路配置成對稱。 依本發明，可不受記憶數據之位元數所限制，可以按 照理想之晶片大小作記憶晶胞區塊之配置。因此，能夠配 置成接近所期望的晶片大小的形狀，故得以防止封裝成本 的增大。而且’將長度各不同的區塊排混合配置’也能將 晶片上的空白區域縮到最小，而得以抑制晶片面積的增 大。 第5圖是顯示本發明之半導體記憶裝置之第3實施形 〜、的平面®在此圖中，如同第】圖表示以Μ個區塊川 至B84加以配置而構成之情形。 ^定數目的記憶晶胞作行列配置，每列各連接字 線每仃各連接位元線，構成記憶晶胞區塊B。例如記 憶晶胞以1 2 8 ?!丨y 9 & ft > f 2 56仃配置，構成各具約32Kb之記憶容 量的區塊Bl 1至b84 f+,將褚 將預備Z憶晶胞•以與區塊B内之 記憶晶胞行數相笙 行數相等之教目配置於列之方向、以 '定數目配 置於仃之方向，嫌士益址广 以8列心 預儀區塊卜例如，將預備記憶晶胞 以8列χ.256行配晋，八則址上、 ^ . . . D 刀引構成能補救8列份的記憶晶胞之 TO M Sjs·塊 R i , p ^， R9 ,.. 、區塊BU至B84及預潢區塊R]、 l本身係具有與第：1圖外 構， ’ 、’導體π憶裝置相同的結 規格 (請先閱讀背面之注意事項再填寫本頁} --裝--------訂---------線------- η娜 461079 A7 __________ B7 五、發明說明（lG) (請先閱讀背面之注意事項再填寫本頁) 第1之區塊排Ml、M2，係將區塊B11至Β14、β21至 Β24各以4個為一行配置而成，再將預備區塊以”於其 端部各配置一個：第2之區塊排Μ3至Μ6，係將區塊β31 至Β64各以4個_行配置、再將區塊β71至Β84内之2個 配置於一行，合計配置成6個單位。這些區塊排M1至Μ6， 可將與配置有預備區珠的一端相反之一端對齊、互相平行 排列。在本實施形態中’各以2條配置於第丨之區塊排M1、 M2的兩側。而將第1之區塊排M1、m2配置於中央，第2 之區塊排M3至M6則成左右對稱e如此配置第1及第2之 區塊排Ml至M6後，於第1之區塊排η、M2之端部產生比 2區塊x2條份之面積小預傍區塊之部份的空白區域。實際 上，區塊B11至B14、B21至B24是由128列的記憶晶胞所 構成’相對地，預備區塊Rl、R2是由8列的預備記憶晶胞 所構成，故預備區塊R1、R2所佔之面積遠小於—個區塊之 面積（理論上是1/16)’不致縮減空白區域之面積。 經濟部智慧則產局員工消費合作社印製 第1周邊電路P1是沿第1及第2之區塊排Ml至M6 之對齊的一端而配置，第2周邊電路P2則是配置於產生在 第1之區塊排Ml、M2的另一端之位於第2之區塊排M4、 M5之間的空白區域。這些周邊電路ρ〗、p2,與第1圖所示 之周邊電路P1、P2具有相等的機能，含有解碼器、寫入琴 大器、讀取放大器等’可指定各區塊811至^84内的特定 記憶晶胞’而作數據之寫入與讀取e其中，第2周邊電路 P2含有為了要以預備區塊R1、R2之各預備記憶晶胞列取 代各區塊Bl 1至B84内之含有不良部位的記憶晶胞列而設 本紙張尺度適用中國國家標準（CNS〉A4規格（21〇 X 297公爱） 10 311088 A7 B； 五、發明說明（11) 置之切換電路^例如’含有可以物理方式切斷的多數熔斷 器’及可由於各熔斷器之切斷而動作的電晶體；以對應於 不良部位之方式切斷熔斷器之切斷部位，由此將含有該不 良部位之記憶晶胞列以列作單位 '被預備區塊R丨，R2之各 預備記憶晶胞列取代。 各區塊排Ml至中’於同一區塊排内之各區塊} 至B84的各記憶晶胞，以同—行之行方向共有位元線而 在各區塊BU至Β84的同一區塊内之各記憶晶胞，於同一 列之列方向共有字線。因而’各區塊排扪至祕"的Μ 個區塊’有如第^圖所示之記憶裝置，可回應位址數據而 同時指定列（字線）及行（位元線）與區埯Β丨丨至之一。 此時’若於特定的位址有不良部位， π ^ 而對應於該位址之控 制電路的熔斷器被切斷，則含有該 ^ 3 ,通位址之記憶晶胞列即被 指疋時，轉而選擇預備區塊r1、r2内11〜狩疋之仃。 此外，第2之區塊排M3至_，其各2個（^行）之，塊州㈣㈣liLB84，在第μ所示之記憶裝置中， -對應於第條之區塊排Μ7、Μ8，而當其位址經指定 請先閱讀背面之注意事項再填寫本頁)'I-' ^ '·· | 1111 | III-Ai Shihang Φ g National Standard: Select _________ I ___---------. ________ (Please read the notes on the back before filling this page) i 6 1079 A7 __-__ B7______ V. Description of the invention (6) M Blocks PI, P2 Peripheral Circuit [Implementation Mode of the Invention] (Please read the precautions on the back before filling this page) Figure 3 shows the semiconductor of the invention A plan view of the first embodiment of the memory device. In this figure, as shown in Fig. 1, it is shown that 32 blocks B11 to B84 are arranged. A certain number of memory cells are arranged in rows and columns, each column is connected to a character line and each row is connected to a bit line to form a memory cell block B. For example, 'the memory cells are arranged in 128 columns x 256 rows to form blocks Bl 1 to B84 each having a memory capacity of about 32Kb »These blocks B11 to B84 themselves are the same as the semiconductor memory device shown in FIG. 1 structure. The first block row M2 and M2 are arranged in blocks of four blocks B11 to β14 and B21 to B24; the second block row M3 to M6 are blocks of four rows B31 to B64. Configure, and then arrange 2 of the blocks B71 to B84 in a row; a total of 6 units are arranged. Align one end of these block rows M1 to M6 and arrange them in parallel with each other. In this embodiment, the first consumer bank printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperatives is arranged in the center, and the second consumer bank M3 to M6 are left-right symmetrical, and each is arranged in the first bank in the second bank. The blocks are arranged on both sides of M1 and M2. By arranging the first and second block rows M1 to M6 in this way, a blank area of the second block x2 can be vacated at the other end of the first block row M1 and M2. The first peripheral circuit P1 is arranged along the aligned ends of the block rows M1 to M6 of the first block row and the second block row. The second peripheral circuit P2 is a blank area disposed between the second block rows M4 and M5 formed at the other end of the first block rows M1 and M2. These peripheral circuits P1, P2 'and the paper size shown in Figure 1 are applicable to the Chinese National Standard (CNS) A4 specification (210 X 2 criminal mm) 6 311088 Consumption of Economic and Intellectual Property Bureau η7 Λ7 ----- Β7__ V. Description of the Invention (7) The peripheral circuits P1 and P2 have equivalent functions, including a decoder, a write amplifier, a read amplifier, etc., and a specific memory cell in each block β11 to B84 can be designated to write data and Read. Each block row M1 to M6, in each block B11 to B84 within the same block row, each memory cell has a single bit line in the same row in the row direction. And each memory cell of each block Bl to B84 in the same block has a word line in the same column in the column direction. Therefore, the 24 blocks in each block row M1iM6, such as the memory device shown in Figure 丨, specify the columns (word lines) and rows (bit lines) in response to the address data. The second block row is 2 blocks (7 rows) of 3 to 6 pairs β7ΐ to B74, B81 to B84, which correspond to the 7th and 8th row blocks in the memory device of FIG. 1 Corresponding to M7 and M8, the selection is valid only after the address is specified. At this time, the row address corresponding to the 7th block row M7 is replaced by the 2nd block row, M4, and the 8th block. The corresponding row address is replaced by block rows M5 and M6. Therefore, from the outside of the device, it is possible to write and read data by designating an address equivalent to the eight blocks M1 to "8 arranged side by side as shown in Fig. 1. FIG. 4 is a plan view showing a second embodiment of the semiconductor memory device of the present invention. In this figure, the i-th block row M1, M2, and the second block row M3 are the same as those in FIG. • A certain number of memory cells are arranged in blocks Bil to B84 in rows and columns, and 4 or 6 of them are each configured as a block row. Will the first block be ranked M 丨 M and the first? The blocks are arranged in parallel to each other after being aligned at the end. This embodiment is to arrange the second block -------------------------- ------- (Please read the notes on the back before filling out this page) -¾ 6 4 07 9 Α7 Β7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (8) M3 to M6 are configured in The first block rows M1 and M2 of the center are symmetrical left and right, and one block row is arranged on each side of the second block rows M3 to M6. After arranging the first and second block rows M1 to M6 in this way ', two blank spaces corresponding to the two blocks are generated at the two ends of the first block row M1 and M2, respectively. The first to third peripheral circuits P1 to P3 are arranged adjacent to each of the block rows M1 to M6. These peripheral circuits to P3 correspond to the first and second peripheral circuits P1 and P2 shown in FIG. 3. The first peripheral circuit P1 is arranged along the aligned ends of the first and second block rows M1 to M6. As for the second and third peripheral circuits P2 and P3 ', it is equivalent to dividing the second peripheral circuit shown in FIG. 3 into two, and is arranged on both sides of the second block row M3 to M6. A blank area generated at the other end of the first block row M1, M2. In the second embodiment, the arrangement of word lines and bit lines in each block is substantially the same as that in the first embodiment. That is, in the second embodiment, only the first line is compared with the first embodiment. The position of the row direction of the block row, M2 and the second block row M3 to M6 is reversed, and the memory cells of the blocks B1 to B84 in the same block row are shared in the same row and row direction. One bit line, and one word line in the same column in the column direction. The address designation of each memory cell is the same as that of the first embodiment. In the above semiconductor memory device, the allocation of addresses corresponding to 2n-bit memory data is performed, and the arrangement of the block rows can be set regardless of the number of bits of the memory data. And with respect to the first peripheral circuit of the second peripheral circuit P2 -------------- M · ------ order -------- line ·-(Please read the back first Note for refilling this page) This paper size applies Chinese National Standard (CNS) A4 (210 χ 297 public love) 8 311088 Member of the Intellectual Property Bureau of the Ministry of Economic Affairs H Consumer Cooperative Seal A7 B7 V. Description of Invention (9) The block rows Mb M2 and the second block rows M3 to M6 are arranged symmetrically to the left and right. 'Corresponding to each 3H line difference of each of the blocks Bii to B8 of the second peripheral circuit P2 4 is also changed. Can be reduced. However, in general, semiconductor memory devices use bit lines with low resistance to form bit lines. Therefore, when the memory capacity is small, it is not necessary to arrange the block rows symmetrically to peripheral circuits. According to the present invention, it is not limited by the number of bits of memory data, and the memory cell block can be configured according to the ideal chip size. Therefore, it can be arranged in a shape close to a desired wafer size, and an increase in packaging cost can be prevented. In addition, the 'mixed arrangement of blocks of different lengths' can also minimize the blank area on the wafer, thereby suppressing an increase in the area of the wafer. Fig. 5 is a plan view showing the third embodiment of the semiconductor memory device according to the present invention. In this figure, as shown in Fig. 5, the figure shows a configuration in which M blocks are arranged to B84. A predetermined number of memory cells are arranged in rows and columns, and each connected word line in each column and each connected bit line constitute a memory cell block B. For example, the memory cell is configured with 1 2 8?! Y 9 & ft > f 2 56 仃, forming blocks Bl 1 to b84 f + each with a memory capacity of about 32Kb, and will prepare the Z memory cell • It is arranged in the direction of columns with the same number of rows as the number of memory cell rows in block B, and is arranged in the direction of 仃, and the suspects are widely used in 8 columns. For example, the prepared memory cell is arranged in 8 columns of χ.256 rows, and ^... D on the eight addresses forms a TO M Sjs · block R i, p ^ that can remedy 8 columns of memory cells. , R9, .., block BU to B84 and pre-decorated block R], l itself has the same junction specifications as the outer structure of the figure: 1 and ',' the conductor π memory device (please read the precautions on the back first) Fill out this page again} --- install -------- order --------- line ------- η 娜 461079 A7 __________ B7 V. Description of Invention (lG) (please first Read the notes on the back and fill in this page.) The first block rows M1 and M2 are made up of four blocks B11 to B14 and β21 to B24. One at each end: the second row of blocks M3 to M6 is the block β31 to B64 are each arranged in 4 rows, and then two of the blocks β71 to B84 are arranged in a row, and the total number is 6 units. These blocks are arranged from M1 to M6. The opposite ends are aligned and parallel to each other. In this embodiment, 'two are arranged on both sides of the first block row M1 and M2. The first block row M1 and m2 are arranged in the center, The second block rows M3 to M6 are left-right symmetrical e. After the first and second block rows M1 to M6 are arranged in this way, the end of the first block row η, M2 produces 2 x 2 blocks The area is smaller than the blank area of the block. In fact, blocks B11 to B14 and B21 to B24 are composed of 128 rows of memory cells. In contrast, the preliminary blocks R1 and R2 are composed of 8 It is composed of a row of preliminary memory cells, so the area occupied by the preliminary blocks R1 and R2 is much smaller than the area of one block (theoretically 1/16) 'does not reduce the area of the blank area. The first peripheral circuit P1 printed by the employee consumer cooperative is arranged along the aligned ends of the first and second block rows M1 to M6, and the second peripheral circuit P2 is It is a blank area arranged between the second block rows M4 and M5 generated at the other end of the first block row M1 and M2. These peripheral circuits ρ〗, p2, and the periphery shown in FIG. 1 The circuits P1 and P2 have the same functions, including decoders, writers, amplifiers, and read amplifiers. 'Specific memory cells in each of the blocks 811 to ^ 84' can be specified to write and read data. Among them, the second peripheral circuit P2 contains the memory cell row containing defective parts in each of the blocks B1 to B84 with the preliminary memory cell rows of the preliminary blocks R1 and R2. Standard (CNS> A4 specification (21〇X 297 public love) 10 311088 A7 B; V. Description of the invention (11) Switching circuit installed ^ For example, "including most fuses that can be physically cut off" and can be The transistor that operates when being cut off; cuts off the cut-off portion of the fuse in a manner corresponding to the defective portion, thereby arranging the memory cell row containing the defective portion as a unit 'prepared block R 丨, R2 Each of the prepared memory cell rows is replaced. Each block row M1 to middle 'each block in the same block row] to B84 memory cells share bit lines in the same row direction and the same block in each block BU to B84 Each of the memory cells in the memory shares word lines in the same column direction. Therefore, the 'M blocks of each block are lined up to the secret " has a memory device as shown in Fig. ^, Which can respond to the address data and specify the column (word line) and row (bit line) and area at the same time. Β 丨 丨 to one. At this time, if there is a defective part at a specific address, π ^ and the fuse of the control circuit corresponding to the address is cut off, then the memory cell array containing the ^ 3 and the through address is referred to. Then, select 11 ~ Kariyuki in the preliminary blocks r1 and r2. In addition, the second block row M3 to _, of which 2 (^ rows) each, the block state ㈣㈣ LBLB84, in the memory device shown in μ,-corresponds to the block row M7, M8 of the first, and (When its address is specified, please read the notes on the back before filling out this page)
It 丨-ί —丨~_ 3- I It 裝---- 訂. 經^部智慧財產局绔.1..消費合^社41.: 後各區塊Β71至Β74、Β81至Β84 之選擇即為有效。此時 二應於第7條之區塊排Μ7之行位址係為第2之區塊排Μ3' ⑻所取代，而第8條之行位址則為第2之區塊 『取代1於這些第2之區塊㈣""各2個之區塊 」^374 ’如至884也進行對上述的24個區塊川 至β64之不.良部位的取氏之同..，動作因 # ’經由如第；圖印斤之.，α 8硌區塊排g • ^ ^ ：y： λ 二一· ..r> 二從裝置之外 至料，並排配置 Μ1088 --------線---------------- 經濟部智慧財產局員工消費合作社印製 6 1079 A7 ___B7 ' ----： ---—. 五、發明說明（12 ) 時相當的位址指定，可作數據之寫入及讀取β 第6圖是顯示本發明之半導體記憶裝置之第4實拖形 態的平面圖。在此圖中，第1之區塊排Ml、M2及第2之區 塊排M3至M6’如第5圈’係以一定數目之記憶晶胞緩行 列配置而成的區塊B11至B84,各以每行四個或六個配置； 再於第1之區塊排Ml、M2各配置一個預備區塊R1、R2而 成。 第1之區塊排Ml、M2及第2之區塊排M3至M6,其— 端對齊而互相平行排列。在此實施形態中，第2之區塊排 M3至M6係配置於中央’而第1之區塊排M1、M2則左右鮮 稱、其一各配置於第2之區塊排M3至M6的兩側。如此配 置第1及第2之區塊排Ml至M6，於第1之區塊排Ml、M2 的另一端之二處即可各空出一個相當於2個區塊減去預偉 區塊R1、R2之份的空白區域。 第1至第3周邊電路P1至P3是與區塊排Ml至M6相 鄰配置。這些周邊電路是相當於第5闺所示之第1及第2 周邊電路PI、P2。第1周邊電路P1是沿第】及第2之區 境排Ml至M6的對齊的一端配置。第2及第3周邊電路P2、 P3則是將相當於如第5圖所示之第2周邊電路P2 —分為 二所構成’各配置於第2之區塊排M3至M6的兩側於第1 之區塊排Ml、M2的另一端所產生的空白區域β 在本第4實施形態中’各區塊内之字線及位元線的配 置疋幾乎與第3實施形態完全相同。亦即，在第4實施形 態令’由與第3實施形態比較可知，只有第1之區塊排Μ1、 -------------."-t--------訂---------線— (請先閱讀背面之注意事項再填寫本莨) 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 x 297公釐） 12 311088 A7 A7 經濟部智慧財產局員工消費合作私印¥ ___B：____ 五、發明說明（13 ) M2與第2之區塊排M3至M6在列的方向其位置相反，而同 一區瑰排内的各區塊B11至B84之各記憶晶胞，在同一行 内行方向共有一位元線’而同一列在列方向共有一字線。 因此，可以進行與第3實施形態相同的位址指定及不良部 位的補救處理。 以上之半導體記憶裝置中’在進行對應於。位元之記 憶數據的位址分配時，區塊之配置設定就可以不受限於記 憶數據之位元數。再者，相對於第2周邊電路P2之第1 之區塊排M1、M2及第2之區塊排M3至M6因是左右對稱配 置’第2周邊電路P2所對應之各區塊B11至B84的個別配 線段差所引起的動作特性變異可得以縮小。但是，通常半 導體記憶裝置因係使用電阻小的鋁配線形成位元線等，故 記憶容量低時’無須將區塊排作對稱於周邊電路的配置。 依本發明，可以不受限於記憶數據之位元數，而將記 憶晶胞區塊按理想晶片大小作配置，在此，行方向較短的 第1之區塊排的端部可以配置補救不良部位用之預備區 塊’而包含為作補救處理而設之控制電路的周邊電路，可 與廷些預備區塊相鄰、配置於第}之區塊排的端部所產生 的工白區域。因此.晶胞上之空白區域可以縮減到最小， 而抑制晶片面積的增大，可得近於理想之晶片大小c 再者’第丨之區塊排及第2之區魄排是左右對稱於周 邊電路而配置s各區塊排之個別動作特性變異可以縮到最 卜有助於電路動作之安定化. 第7圖是顯示本發明之本導體紀憶裝置的第3實跑形 • ____ -----.... 、’’…一足遣呷中國國家螵渫:ΤΤΤΓΐΓ·—---------—!一，~——————— 17 Hum ------- ----I t -------I I ^ -----I-- c請先閱讀背面之注意事項再填寫本頁) A7 461079 _ B7 _ 五、發明說明（14 ) 態之平面圖在此圖中，與第1圖相同’是由32個區塊 B11至B84配置而構成。 (請先閱讀背面之注意事項再填寫本頁) 將一定數目的記憶晶胞作行列配置，每列各連接以一 字線、同時每行各連接以一位元線，構成記憶晶胞區塊B。 例如，記億晶胞以128列χ256行配置，構成各具約32Kb 之記憶容量的區塊B11至B84。這些區塊B11至B84本身 是與第1囷所示之半導體記憶裝置具有相同的結構。 第1之區塊排祕1、|^2，是將區塊^1至814、821至 B24各以每4個為一行配置而成；第2之區塊排M3至M6， 是將區塊B31至B64各以每4個一行配置，再將區塊B71 至B84内之2個各於其一行配置；合計構成6個單位。將 這些區塊排Ml至M6的一端對齊而互相平行排列。在本實 施形態中’第1之區塊排Ml、M2係配置於中央、第2之區 塊排M3至M6則成左右對稱’各將其2配置於第1之區塊 棑U2的兩側。如此配置第i及第2之區塊排Ml至M6 , 則於第1之區塊排Ml、M2之另一端，可以產生2區塊χ2 條之空白區域。在本實施形態’第2之區塊排M3至Μ6， 與第1圖之於第7、第8行配置區塊Β71至Β84相比，配 置區域的列方向之長度可以比第1圖的短。因此，即使下 述之列解碼器R1至R3各配置於區塊排Ml至Μ6之間，木 能防止各配置區域在行方向之過度擴大。而因周邊電路 是配置於第1之區塊排jy、M2的端部所產生之空白區域， 故也可將行方向的擴大抑制於最低限度。 第1之行解碼器C1、C2是鄰接第1之區塊 尺_度適用中國國家標準（CNS)A4規格（210 X 297公釐）— 一~~ ------ A7 五、發明說明（) 的一端而配置，第1之列解 uo 〗解碼15 是配置於第I之區塊排It 丨 -ί — 丨 ~ _ 3- I It installation ---- order. Ministry of Intellectual Property Bureau 11 .. 消费 合 合 41 .: Choice of the following blocks B71 to B74, B81 to B84 That is effective. At this time, the row address of the block row M7 that should be in Article 7 is replaced by the second row row M3 '2, and the row address of Article 8 is the block 2 of the "Replace 1 in These second blocks ㈣ " " 2 blocks each "^ 374 'If you go to 884, you also perform the difference between the above-mentioned 24 blocks and β64. The difference between the good parts is ... # 'Through the first; the picture is printed., Α 8 硌 block row g • ^ ^: y: λ two one · .. r > two from outside the device to the material, side by side configuration M1088 ------ --Line ---------------- Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 6 1079 A7 ___B7 '----: -----. V. Description of the Invention (12 ) Is equivalent to the address designation, which can be used for data writing and reading. Β FIG. 6 is a plan view showing a fourth embodiment of the semiconductor memory device of the present invention. In this figure, the first block rows M1, M2, and the second block rows M3 to M6, such as the fifth circle, are blocks B11 to B84 configured with a certain number of memory cells slowly arranged, Each row has four or six configurations; and a first block row M1 and M2 are each configured with a preliminary block R1 and R2. The first block rows M1, M2 and the second block rows M3 to M6 are aligned at one end and arranged parallel to each other. In this embodiment, the second block rows M3 to M6 are arranged in the center, and the first block row M1 and M2 are called left and right. One of them is arranged in the second block row M3 to M6. On both sides. In this way, the first and second block rows M1 to M6 are arranged, and one of the two blocks at the other end of the first block row M1 and M2 can be vacated, which is equivalent to 2 blocks minus the pre-block R1. , R2 blank area. The first to third peripheral circuits P1 to P3 are arranged adjacent to the block rows M1 to M6. These peripheral circuits are equivalent to the first and second peripheral circuits PI and P2 shown in the fifth figure. The first peripheral circuit P1 is arranged along the aligned ends of the first and second area rows M1 to M6. The second and third peripheral circuits P2 and P3 are equivalent to the second peripheral circuit P2 shown in FIG. 5-divided into two, each of which is disposed on both sides of the second block row M3 to M6 on The blank area β generated at the other end of the first block rows M1 and M2 is almost the same as the third embodiment in the arrangement of the word lines and bit lines in each block. That is, in the fourth embodiment, it is known from the comparison with the third embodiment that only the first block row M1, -------------. &Quot; -t ---- ---- Order --------- Line— (Please read the notes on the back before filling in this card) This paper size applies to China National Standard (CNS) A4 (21〇x 297 mm) 12 311088 A7 A7 Private Print of Employees' Cooperative Cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs ¥ ___B: ____ 5. Description of the Invention (13) M2 and the second block row M3 to M6 are in opposite directions in the column, and the rows in the same row Each memory cell of each block B11 to B84 has a bit line in the row direction in the same row and a word line in the column direction in the same column. Therefore, the same address designation and defective part remedial processing as in the third embodiment can be performed. In the above-mentioned semiconductor memory device, "'is being processed. When the bit address of memory data is allocated, the block configuration setting can be not limited to the number of bits of memory data. In addition, the first block rows M1, M2, and the second block rows M3 to M6 relative to the second peripheral circuit P2 are symmetrically arranged, and the blocks B11 to B84 corresponding to the second peripheral circuit P2 Variations in operating characteristics caused by differences in individual wiring segments can be reduced. However, semiconductor memory devices generally use aluminum wiring with low resistance to form bit lines, and so when the memory capacity is low, it is not necessary to arrange the blocks symmetrically to the peripheral circuits. According to the present invention, the memory cell block can be arranged according to the ideal chip size without being limited to the number of bits of the memory data. Here, the end of the first block row with a shorter row direction can be provided with a remedy. Preparatory blocks for defective parts' include peripheral circuits that contain control circuits for remedial processing, and can be adjacent to these preparatory blocks and can be located at the end of the block row at the {} white area. . Therefore, the blank area on the unit cell can be reduced to a minimum, and the increase in the area of the wafer can be suppressed, which can be close to the ideal wafer size c. Furthermore, the first and second block rows are symmetrical about left and right. Peripheral circuits and the individual operating characteristic variations of each block row can be reduced to the greatest extent and contribute to the stabilization of the circuit operation. Figure 7 shows the third running shape of the conductor memory device of the present invention • ____- ----...., `` ... delivered to the Chinese State: ΤΤΤΓΐΓ · ——-----------! I, ~ ———————— 17 Hum ---- --- ---- I t ------- II ^ ----- I-- c Please read the notes on the back before filling this page) A7 461079 _ B7 _ V. Description of the invention (14 The plan view of the state in this figure is the same as in the first figure. It is composed of 32 blocks B11 to B84. (Please read the precautions on the back before filling this page) A certain number of memory cells are arranged in rows and columns, each column is connected with a word line, and each row is connected with a bit line to form a memory cell block B. For example, a billion cell is arranged in 128 columns and 256 rows, and constitutes blocks B11 to B84 each having a memory capacity of about 32Kb. These blocks B11 to B84 themselves have the same structure as the semiconductor memory device shown in Fig. 1 (a). Block 1 of the first block 1, | ^ 2 is a block arrangement of blocks ^ 1 to 814 and 821 to B24 each; the block 2 of blocks M3 to M6 is a block B31 to B64 are arranged in rows of four, and two in blocks B71 to B84 are arranged in one row; a total of 6 units are formed. One ends of these block rows M1 to M6 are aligned and aligned in parallel with each other. In this embodiment, 'the first block rows M1 and M2 are arranged in the center, and the second block rows M3 to M6 are left-right symmetrical', and each of them is arranged on both sides of the first block 棑 U2 . If the i and the second block rows M1 to M6 are configured in this way, a blank area of the two blocks x2 can be generated at the other end of the first block row M1 and M2. In the block rows M3 to M6 of the second embodiment, compared with the arrangement blocks B71 to B84 on the seventh and eighth rows in FIG. 1, the column direction length of the arrangement area can be shorter than that in FIG. 1. . Therefore, even if the decoders R1 to R3 described below are each arranged between the block rows M1 to M6, it is possible to prevent the arrangement areas from being excessively enlarged in the row direction. And because the peripheral circuit is a blank area generated at the end of the first block row jy, M2, the expansion in the row direction can also be suppressed to a minimum. Decoders C1 and C2 on the first row are block sizes adjacent to the first. _ Degree applies to China National Standard (CNS) A4 specification (210 X 297 mm) — 1 ~~ ------ A7 5. Description of the invention () Is configured at one end, and the first column is solved uo 〖Decoding 15 is configured in the first block row
Ml、M2之間。第2之行解 解碼器C3至C6則是鄰接第2之區 塊排M3至Μβ的一·端而配署，楚〇 配置第2之列解碼器R2、R3則是 各配置於第2之區Miifc u。 lf, 弟Z之L塊排M3、M4之間及第2之區塊排M5、 M6之間。 1周邊電路P1 ’是沿第}及第2之區塊棑Mi至j6 的對齊的—端配置，而第2周邊電路P2是配置於第】.之區 塊排 Μ 1、2 之另一^ 0C. li. Ρ5 λ 端所產生且介於第2之區塊排Μ5、Μ6 之間的空白區域。這些周邊電路〜？2，含寫人放大器 讀取放大器等’是構築成可經行解碼器π至U及列解碼 器至R3指疋各區塊β1 i至β84内之特定記憶晶胞對 其進行寫入或讀取。 各區塊棑Ml至Μ6’在同一區塊排内之各區塊By至 B84中，各記憶晶胞在同一行、於行方向共有一位元線。 因之’各行解碼器CliC6’即回應行選擇資訊，選擇各 區塊排MI至M6内之特定記憶晶胞行而予以活性化。例如， 於各區塊排Ml至M6所配置之256行的記憶晶胞行， 行選擇資訊而以8行為單位被選擇a而各區塊…至_ 之同-區塊内的各記憶晶豸，在同—列的列方向共有— 線各列解碼器R }纟⑸可對其兩側所配置之區塊排& 謂内的每-區境Βδ4作記憶晶胞列之選擇而予口 活性化H列解碼$ Ri至㈣是構築成若於第心 模A則選擇兩側之任而若是，第2動作模式則兩預二 ί 1· I 1 II f (請先¾讀背面之注意事項再填寫本頁 裝 經濟却智慧財產€員<-.'.!!費ώ'~作hr.-:· J1T---------線------ 時選擇，例如於各區.塊i⑴至M4 η ].(_ 經濟部智慧財產局員Η消費合作社印製 Α7 Β7 五、發明說明（16) 晶胞列’若是在第1動作模式，則逐列選擇區塊B丨丨至B84 之一’而於第2動作模式則逐行將各區塊丨至B84之内 之相鄰的兩者皆予選擇。此時，列解碼器R1至r3若將各 區塊排Ml至M6的記憶晶胞行每8行作選擇，則於第1動 作模式進行8位元的數據之寫入或讀取；而於第2動作模 式進行16位元的數據之寫入或讀取。 再者’第2之區塊排s(3至M6的各2(x4行）的區塊B71 至B74、B81至B84，係相當於第1圈所示之記億裝置中的 第7、第8排區塊排其位址若經指定，選擇即成 有效。在本實施形態’第7棑區塊排M7所對應之行位址為 第2之區塊排M3、M4所取代’第8排之區塊排M8所對應 之行位址為第2之區塊排M5、M6所取代。因此，從裝置之 外部’可經與如第1圖所示之8排區塊排Ml至M8並排配 置時相當之位址指定而得以寫入或讀取數據。 第8圖是顯示列解碼器R1的構造之—例的區塊圖。此 圖顯示’回應列選擇信號RD及區塊選擇信號BD，而選擇 特定的區塊内的特定列之情況。 列解碼器R1是由列選擇電路1、第1之區塊選擇電路 2、第2之區塊選擇電路3及XOR閘極4所構成。列選擇電 路1，於回應列選擇信號RD時，選擇1區塊内的晶胞列& 一而產生選擇信號S〇、SE。例如，對應配置於1區塊的 128列之記憶晶胞列構成7位元的列選擇信號rd，對應於 列選擇信號RD之内容’引發128單元輪出中之一而產生選 擇信號50、$£。第1及第2之區塊選擇電路2、3，係被 ------------νι^--------訂·--------線·: (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 16 311088 A7 B7 五、發明說明（17) 設定為各對應於奇數行的區塊排M1及偶數行的區塊排 M2 ’共同回應所收受之區塊選擇信號βΙ)而將各選擇信號 s〇、sE -分為四’對各區塊β11至β24送出選擇信號％! 至S〇4、SE^ sE〆而第2之區塊選擇電路3,收受選 擇奇數行或偶數行之任—的選擇信號1之區塊選擇 電路2則收受由X0R閘極而來的選擇信號〇£及楔式設定信 號MS之互斥邏輯和。在此，第}及第2之區塊選擇電路卜 3係被構築成可以回應選擇信號〇£及模式設定户號以之 邏輯和，及選擇信號GE本身而作動。因此，模式°設定信號 MS是高電位時，選擇信號〇E就反轉而供給第i之區塊選 擇電路2’故可依選擇信號QE之指示，對第}及第2之區 塊選擇電路2'3擇一啟動。再者，若模式設定信㈣是 低電位時®為選擇信號〇E能直接供給第i之區塊選擇電 路2’故經選擇信號0E之指示可同時啟動第i及第2之區 塊選擇電路2、3。因此，笛 經濟部智慧財產局員-消費合^"" 四此第2動作模式才得以進行二倍於 第】動作模式之位元數的數據之寫入與讀取。而至於模式 設定信號MS，因係固定於高電位或低電位之信號，一旦決 定之後’大體上並無變更之必要。因此模式設定信號MS 在製造步驟上’係先形成可物理方式切斷的炼斷器.或非 揮發性的記憶晶胞，藉溶斷器之切斷，或寫入記憶晶胞而 得以選擇電源電位或接地電位。再者1使沒有焰斷器或 記憶晶胞之形成配線的部分變更也能進行對電源電 位或接地電位之選擇此時’若對最上層之配综加以變L 大部份的袈造步驟就可共同進行。 i!:."-)扪 4 δ 1 07 9 ' Α7 ______Β7 五、發明說明（18 ) 再者’以上實施形態之中’除已例示之將第1之區塊 排Ml、M2及第2之區塊排M3至M6的一端對齊而配置之外， 也可以配置成使空白區域形成於第1之區塊排Ml、M2的兩 端外側並且，記憶晶胞之形式也非特定；此類半導體記 憶裝置，可以是靜態RAM、或動態RAM、或各種ROM。 --------— — — — — - i t ) I I I I I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 18 311088Between Ml and M2. Decoders C3 to C6 of the second row are deployed adjacent to one end of the second block row M3 to Mβ, and the decoders R2 and R3 of the second column are arranged in the second one. District Miifc u. lf, between Z's L block rows M3 and M4 and second block row M5 and M6. 1 Peripheral circuit P1 'is arranged along the alignment of the first and second blocks 棑 Mi to j6, and the second peripheral circuit P2 is arranged at the second block. The other row of blocks 1,2, ^ 0C. Li. P5 The blank area generated by the λ end and between the second block rows M5 and M6. These peripheral circuits ~? 2. Includes writer amplifier, read amplifier, etc. 'is constructed so that it can be written to or read by specific memory cells in each block β1 i to β84 via row decoders π to U and column decoders to R3. take. Each of the blocks 棑 M1 to M6 'is in each of the blocks By to B84 in the same block row, and each memory cell has one bit line in the same row in the row direction. Therefore, the 'decoder CliC6' of each row responds to the row selection information and selects a specific memory cell row in each block row MI to M6 to be activated. For example, in the memory cell rows of 256 rows arranged in each block row M1 to M6, row selection information is selected in 8-row units a and each block ... to _ is the same as each memory cell in the block In the column direction of the same column, the line decoder R} can be used to select the memory cell column for each of the block arrays & The activation H column decoding $ Ri to ㈣ is constructed so that if it is in the first heart mode A, choose either of the two sides and if it is, the second action mode is two preliminaries ί 1 · I 1 II f (Please read the note on the back first Fill in the matter again and fill in this page to install the economic but intellectual property members <-. '. !! Fee for free' ~ for hr .-: · J1T --------- line ------ choose when, For example, in each area. Blocks i⑴ to M4 η]. (_ Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by the consumer cooperative A7 B7 V. Description of the invention (16) If the unit cell column is in the first operation mode, select the block column by column B 丨 丨 to B84 ', and in the second action mode, each block within the block 丨 to B84 is selected row by row. At this time, the column decoders R1 to r3 Memory cells from M1 to M6 are selected every 8 rows , Then 8-bit data is written or read in the first action mode; 16-bit data is written or read in the second action mode. Furthermore, the second block row s ( Blocks B71 to B74 and B81 to B84 of 2 (x4 rows) from 3 to M6 are equivalent to the 7th and 8th row blocks of the billion device shown in the first circle if their addresses are specified The selection is valid. In this embodiment, the row address corresponding to the seventh row block row M7 is replaced by the second row row M3 and M4. The row row corresponding to the row row M8 of the eighth row The address is replaced by the second row of blocks M5 and M6. Therefore, from the outside of the device, it can be written by specifying an address equivalent to that of the eight rows of blocks M1 to M8 as shown in Fig. 1 Figure 8 is a block diagram showing an example of the structure of the column decoder R1. This figure shows the 'response to the column selection signal RD and the block selection signal BD, and select a specific block in a specific block. The column decoder R1 is composed of a column selection circuit 1, a first block selection circuit 2, a second block selection circuit 3, and an XOR gate 4. The column selection circuit 1 is in the response column. When the selection signal RD is selected, the unit cell sequence in the 1 block is selected, and the selection signals S0 and SE are generated. For example, a memory cell row corresponding to 128 columns arranged in the 1 block constitutes a 7-bit column selection signal rd, corresponding to the content of the column selection signal RD, causes one of the 128 unit rotations to generate a selection signal of 50, $ £. The first and second block selection circuits 2, 3 are ------ ------ νι ^ -------- Order · -------- Line ·: (Please read the precautions on the back before filling out this page) This paper size applies to Chinese national standards ( CNS) A4 specification (210 X 297 mm) 16 311088 A7 B7 V. Description of the invention (17) Set the block row M1 corresponding to the odd row and the block row M2 of the even row each to respond to the blocks received (Selection signal β1) and divide each selection signal s0, sE-into four 'to send the selection signal% to each block β11 to β24! To S04, SE ^ sE〆 and the second block selection circuit 3, receives The block selection circuit 2 which selects either the odd-numbered row or the even-numbered row-selection signal 1 receives a mutually exclusive logical sum of the selection signal 0 from the X0R gate and the wedge-type setting signal MS. Here, the block selection circuits B3 and B3 are constructed so as to be able to respond to the logical sum of the selection signal 0 and the mode setting account number, and the selection signal GE itself. Therefore, when the mode ° setting signal MS is at a high potential, the selection signal 0E is inverted and supplied to the i-th block selection circuit 2 '. Therefore, according to the instruction of the selection signal QE, the} and the second block selection circuits can be selected. 2'3 start one. Furthermore, if the mode setting signal is low, ® is the selection signal 0E can be directly supplied to the i-th block selection circuit 2 ', so the i-th and second block selection circuits can be activated at the same time by the instruction of the selection signal 0E. 2, 3. Therefore, the member of the Intellectual Property Bureau of the Ministry of Economic Affairs-Consumption Coordination ^ " " Fourth, the second operation mode can be written and read twice the number of bits of the operation mode. As for the mode setting signal MS, since it is a signal fixed at a high potential or a low potential, once it is determined, it is generally not necessary to change it. Therefore, in the manufacturing steps, the mode setting signal MS is to form a circuit breaker that can be physically cut off, or a non-volatile memory cell. The power source can be selected by cutting off the fuse or writing to the memory cell. Potential or ground potential. In addition, 1 can make the selection of the power supply potential or the ground potential without changing the formation of the wiring of the flame interrupter or the memory cell. At this time, 'if the top layer is changed, most of the fabrication steps will be changed. Can be done together. i!:. "-) 扪 4 δ 1 07 9 'Α7 ______ Β7 V. Description of the invention (18) Furthermore,' in the above implementation form ', except for the example, the first block is ranked M1, M2, and the second In addition to the arrangement of one end of the block rows M3 to M6, it can also be configured so that a blank area is formed outside the two ends of the first block row M1 and M2 and the form of the memory cell is not specific; The semiconductor memory device may be a static RAM, a dynamic RAM, or various ROMs. --------— — — — —-it) IIIII (Please read the notes on the back before filling out this page) Printed on paper scales of the Intellectual Property Bureau of the Ministry of Economic Affairs's Consumer Cooperatives to apply Chinese National Standards (CNS) A4 size (210 X 297 mm) 18 311088