JP2993684B2 - Semiconductor memory device with defect relieve circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a semiconductor memory, and more particularly to a technique for repairing a defective memory cell by replacing the defective memory cell with a spare memory cell.

[Prior art]

High integration of semiconductor memory has been rapidly progressing in recent years,
Megabit-class products are also being mass-produced. However, there has been a problem that the yield is reduced due to the miniaturization of elements and the increase in chip area accompanying the high integration.
As a countermeasure, there is a so-called defect remedy technique in which a defective memory cell is repaired by replacing it with a spare memory cell provided on a chip in advance. This technology is described in, for example, IEE, Journal of Solid State Circuits, Vol. 16, No. 5,
Pages 479 to 487, October 1981 (IEEE, Journal of So
lid-State Circuits, vol.SC-16, No.5, pp.479-487, Oc
t, 1981), it is a very effective technique for improving the yield of semiconductor memories. FIG. 25 shows an example of the configuration of a semiconductor memory to which defect relief is applied. In FIG. 1, reference numeral 10 denotes a memory array in which memory cells are arranged in a matrix, and includes an area 11 in which regular memory cells are arranged and an area 12 in which spare memory cells are arranged. The region 11, N _W of word lines W [i]
(I = 0~N _W -1) and N _B bit lines B [j] (j = 0
The intersection of the to N _B -1), is N _W × N _B number of memory cells are arranged. In the area 12, the intersection of the spare word line SW [k] (k = 0 to L) and N _B bit lines of L present (here L = 4), the L × N _B number of memory cells Are located. Note that the bit line is formed of two wires in the case of the so-called folded bit line method, but is represented by one line here for simplicity. 20 is a sense amplifier for amplifying a signal read from the memory cell and an input / output line for transferring data, and 30 is a row address signal A _X [i] (i = 0
Nn _W −1, n _W = log ₂ N _W ) and an X decoder 40 for selecting one of the N _W word lines, and a column address signal A _Y [j] (j = 0) _{~n B -1, n B = log} 2 n B) receiving and n _B present in Y decoder for selecting one of the bit lines, 50 is a defect redundancy circuit, 60 an output of the defect relief circuit A spare word line selection circuit for receiving and selecting a spare word line, 701 is a data input buffer, and 702 is a data output buffer. Since the present memory is provided with a word line defect relief circuit, if a normal word line is defective, it can be repaired by replacing it with one of the spare word lines. Defect relief circuit 50 and spare word line selection circuit
60 controls this. One for each of the L spare word lines
Address comparison circuits AC [k] (k = 0 to L−
There is 1). Each address comparing circuit stores a row address of a defective spare word line, and compares it with an address requested to be accessed. The output XR [k] of the address comparison circuit AC [k] becomes high level when the comparison result is “match”. The spare word line selection circuit 60
As shown in FIG. 26, it is composed of L spare word drivers 650. The spare word driver is activated when XR [k] is at a high level, and the spare word line SW [k] is selected by the word line drive signal φx. On the other hand, the output of the NOR gate 501 goes low, thereby disabling the X-decoder 30 and preventing the normal word line that should have been selected from being selected. That is, the normal word line is replaced by the spare word line SW [k]. FIG. 32 shows another example of the configuration of the semiconductor memory to which the defect relief is applied. In the figure, reference numeral 10 denotes a memory array in which memory cells are arranged in a matrix, and includes an area 14 in which normal memory cells are arranged and an area 15 in which spare memory cells are arranged. The regions 14, N _W of word lines W [i]
(I = 0~N _W -1) and N _B bit lines B [j] (j = 0
The intersection of the to N _B -1), is N _W × N _B number of memory cells are arranged. In the area 15, N _W × L memory cells are provided at the intersections of L (here L = 4) spare bit lines SB [k] (k = 0 to L) and N _W word lines. Are located. 20 input and output lines for transferring the sense amplifier and the data for amplifying the signal read from the memory cell, 30 is a row address signal A _X [i] _{(i = 0~n W -1, n} W = log
X decoder for selecting one of the M _W of word line receives ₂ N _W), 40 is a column address signal A _Y [j]
_{(J = 0~n B -1, n} B = log 2 N B) receiving and N _B present in Y decoder for selecting one of the bit lines, 50 is defect relief circuit, 63 is a defect repair A spare bit line selection circuit for selecting a spare bit line in response to an output of the circuit. Since this memory is provided with a bit line defect repair circuit, if a normal bit line is defective, it can be repaired by replacing it with one of the spare bit lines. Defect relief circuit 50 and spare bit line selection circuit
63 controls this. One for each of the L spare bit lines
Address comparison circuits AC [k] (k = 0 to L−
There is 1). Each address comparison circuit stores the column address of the defective spare bit line and compares it with the address requested for access. The output YR [k] of the address comparison circuit AC [k] indicates that the comparison result is "match".
In the case of, it will be a high level. Spare bit line selection circuit 63,
As shown in FIG. 33, it is composed of L drivers 680. Driver YR [k] is activated when a high level, the bit line selection signal phi _Y, spare bit line SB [k] is connected to the input and output lines I / O via the MOS transistor 690, 691.
On the other hand, the output of the NOR gate 501 goes low, thereby disabling the Y decoder 40 and preventing the normal bit line that should have been selected from being selected. That is,
The normal bit line is replaced by the spare bit line SB [k].

[Problems to be solved by the invention]

In the above-described conventional defect rescue technique, the following problem occurs with the increase in memory integration. First, since the number of memory cells that are simultaneously replaced by the defect relief increases, the probability that the spare memory cell itself has a defect increases. This is because the number of memory cells on one word line or bit line increases. For example, 256K bit memory (N _W = N _B = 51
In the case of 2), the number of memory cells to be replaced at the same time is 512, but in the case of a 16-Mbit memory (N _W = N _B = 4096), it is 4096.
It will be individual. If a spare memory cell replaced with a regular memory cell has a defect, the chip becomes defective. This is because the defect remedy technique is based on the premise that the spare memory cell has no defect. Therefore, in the prior art, the effect of improving the yield cannot be improved with the high integration of the memory. This problem is exacerbated when it becomes necessary to divide the memory array as the memory becomes larger. Generally, as the size of the memory increases, one word line, one word line,
Since the number of memory cells connected to the bit line is increased, the wiring length is increased, which causes a problem of an increase in signal propagation time and a decrease in signal / noise ratio due to an increase in parasitic resistance and parasitic capacitance of the wiring. For this purpose, it is widely practiced to divide a memory array into a plurality of memory mats and reduce the length of one word line and one bit line. However, when a conventional defect remedy technique is applied to a semiconductor memory divided into mats, the following problem occurs. FIG. 27 shows an example of a configuration in the case where the memory array is divided into four memory mats (the load line is divided into two and the bit lines are divided into two) in the semiconductor memory of FIG. In the figure, 100 to 103 are memory mats, 200 to 203 are sense amplifiers and input / output lines, 300 and 301 are X decoders, 400 is a Y decoder, 610 and 611 are spare word line selection circuits, 700 is a multiplexer, and 701 is data. An input buffer 702 is a data output buffer. Each memory mat includes regions 110 to 113 in which regular memory cells are arranged and regions 120 to 123 in which spare memory cells are arranged. Regions 110, 111, 11
2, 113 (corresponding to 11A, 11B, 11C, 11D in FIG. 25, respectively)
, N _W × N _B / 4 memory cells are arranged at intersections of N _W / 2 word lines and N _B / 2 bit lines.
In each of the regions 120 to 123, at the intersection of L (here L = 4) spare word lines and N _B / 2 bit lines, L × N _B / 2
Spare memory cells are arranged. For example, in the example described in the above document, N _W / 2 = 64 and N _B / 2 = 12
8, L = 4. First, a method of selecting a word line in this memory will be described. In this example, a word line is selected every two mats. For example, a word line W having a memory mat 110
When [i, 0] is selected, the corresponding word line W [i, 2] of the memory mat 112 is also selected at the same time. At this time, the word lines of the memory mats 111 and 113 are not selected. vice versa,
When the word lines of the memory mats 111 and 113 are selected,
The word lines of the memory mats 110 and 112 are not selected. This means that the word lines W [i, 0] and W [i, 2] are originally one word line divided into two, and are physically two word lines, but logically This is because it can be regarded as one word line. Select memory mats 110 and 112, or
Whether to select 111 or 113 is determined by one of the row address signals (here, the highest A _X [n _W −1]). In addition,
The final memory cell selection is the column address signal A
Carried out by _{the Y} [j] (j = 0~n _B -1). At this time,
Whether the memory cell in the memory mat 110 or 111 or the memory cell in the memory mat 112 or 113 is selected is determined by the multiplexer 700 by using one of the column address signals (here, the most significant A _Y [n _B − 1)). In this example, each address comparison circuit compares the row address signals except for the highest-order A _X [n _W −1]. The output XR [k] of the address comparison circuit AC [k] is commonly supplied to each spare word line selection circuit. The spare word line selection circuit, as shown in FIG. 28, takes the logical product of XR [k] and the row address signal A _X [n _W -1] (or its complement) to select the selected memory. Only the spare word line of the mat is driven. In this memory, replacement of a regular line with a spare line is performed simultaneously for all memory mats. This will be described with reference to FIG. This figure shows an example of a word line replacement method. Here, the defective word line [0,
0], W [2,0], W [1,1], W [3,3] are reserved word lines SW [0,0], SW [1,0], SW [2,1], SW [3,
3]. However, other word lines are also replaced at the same time. For example, if W [0,0] is replaced by SW [0,0], the corresponding word line W of another memory mat is replaced.
[0,1], W [0,2], W [0,3] are also SW
Replaced by [0,1], SW [0,2], SW [0,3]. The example shown in FIG. 27 has the following problems. First
The problem is that the area for the spare word line increases by dividing the mat, as is apparent from a comparison between FIG. 25 and FIG. This is because L spare word lines are provided for each of the divided mats. No.
Since the area 12A in FIG. 25 corresponds to 120 and 121 in FIG. 27, and the area 12B corresponds to 122 and 123 in FIG. 27, the area for the spare word line is doubled. In general, the word line M _W divided, if the bit line is divided M _B, the area of the spare word line is in M _B times, spare bit lines (Figure 25, not described in FIG. 27) for The area becomes _MW times. This leads to an increase in chip area. The second problem is that the number of memory cells to be replaced at the same time increases due to word line defect relief. this is,
This is because the replacement of the regular line with the spare line is performed simultaneously for all the memory mats as described above. Generally, the word line is _MW
Dividing, when the bit line is divided M _B, the number of memory cells to be replaced at the same time by a defect repair word lines in M _B times, the number of memory cells to be replaced at the same time by the defect bit line relief becomes M _W times. As described above, this causes a decrease in yield due to an increase in the number of memory cells to be simultaneously replaced. These problems are especially, M _W, by a large high density memory of M _B, becomes very serious. As a method of applying the defect remedy to the memory divided into mats, the method shown in FIG. 30 can be considered. here,
Address comparison circuits are provided for all the spare lines of all the memory mats. Therefore, the number of address comparison circuits is 4L (here, 8). Each address comparison circuit outputs a row address signal A _X

[0] to A _X (n _W
-1) and A _Y [n _B −
1) is also compared. FIG. 31 is a diagram showing an example of a word line replacement method in the memory of FIG. As is clear from comparison with FIG. 29, the method shown in FIG. 30 is superior to the method shown in FIG. 27 in the following point. The first point is that the use efficiency of spare lines is good, and the same number of defects can be repaired even if the number L of spare lines per memory mat is small. This is because the probability that many defects are concentrated on one memory mat is small. The second point is that the number of memory cells to be replaced at the same time is small. However, the method shown in FIG. 30 has a problem that the number of address comparison circuits increases. In general, the word line M _W divided, if the bit line is divided M _B, the address comparison circuit number is M _W M _B L. This leads to an increase in chip area. In particular, M _W, by a large high density memory of M _B, becomes very serious. In addition, there is a method proposed in Japanese Patent Application Laid-Open No. Sho 60-130139. This is to make it possible to mutually replace a normal line and a spare line between memory mats. However, this method has a problem that the control of memory mat selection becomes complicated, particularly when the number of mat divisions is large. This is because the memory mat to be selected must be changed depending on whether the access requested address is defective. In particular, in the case of a DRAM, changing the selected memory mat involves changing the sense amplifier to be operated, thereby increasing the access time. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide a defect remedy system having a small area and a large yield improvement effect.

[Means for Solving the Problems]

In order to achieve the above object, according to the present invention, when the memory array is divided into M (M ≧ 2) memory mats, the number m of word lines or bit lines simultaneously replaced by the defect relief is reduced to M smaller than M. Make it a divisor. Further, not only “0” and “1” but also a don't care value “X” can be stored in the address comparison circuit. The don't care value is a value at which the comparison result becomes “match” regardless of whether the comparison partner (input address) is “0” or “1”. FIG. 13 shows a list of the comparison results.

[Action]

By making m smaller than M, the number of memory cells that are simultaneously replaced by the defect relief decreases. As a result, the probability that the spare line itself has a defect is reduced, so that even in a highly integrated memory, a defect relief circuit having a large yield improvement effect can be manufactured. By allowing the don't care value “X” to be stored in the address comparison circuit, it is possible to select whether or not to compare each bit of the address. As shown in FIG. 13, when “0” or “1” is stored in the address comparison circuit,
According to the input address, the comparison result is “match” or “mismatch”. That is, the bit of the input address is compared with the stored address. On the other hand, when "X" is stored in the address comparison circuit, the comparison result is "match" regardless of the input address. That is, the corresponding bits of the input address are not compared. As a result, for example, the following defect remedy becomes possible. If all bits of the address (including the row address and the column address) are compared, the normal memory cell and the spare memory cell are replaced in units of one bit. If only the column address is compared, the replacement is performed on a bit line basis. If only the least significant bit of the column address is not compared, replacement is performed in units of two bits. As described above, various failures of the semiconductor memory, such as a bit failure, a bit line failure, and a bit failure, can be dealt with in a finer manner.

【Example】

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, a case will be described in which defect repair is introduced into a DRAM (dynamic random access memory), particularly a DRAM using a one-transistor, one-capacitor type memory cell. However, the present invention relates to an SRAM (static random access memory), The present invention is also applicable to other semiconductor memories such as an EPROM (rewritable read-only memory) and an EEPROM (electrically rewritable read-only memory). Also, mainly
Although a semiconductor memory using CMOS technology will be described, the present invention is directed to other technologies, for example, a unipolar MOS transistor,
The present invention is also applicable to a semiconductor memory using a bipolar transistor or a combination thereof. Embodiment 1 FIG. 1 shows an embodiment of the present invention. In the figure, 100 to 103 are memory mats, 200 to 203 are sense amplifiers and input / output lines, 300 and 301 are X decoders, 400 is a Y decoder, 500 is a defect rescue circuit, and 600 is a spare word line selection circuit (the configuration is 26
700 is a multiplexer, 701 is a data input buffer, and 702 is a data output buffer. Each memory mat has an area 110 to 1 where a regular memory cell is arranged.
13 and regions 120 to 123 in which spare memory cells are arranged. Each of the regions 110-113, N _W / 2 word lines W [i, n] _{(i = 0~N W / 2-1,} n = 0~3) and N _B / 2 bit lines B [j, n] _{(j = 0~N B / 2-1,} n = 0~3) at the intersection of the, and n _W × n _B / 4 memory cells are arranged. region
Each of 120 to 123 has L (here L = 2) spare word lines SW [k, n] (k = 0 to L−1, n = 0 to 3) and N _B / 2
L × N _B / 2 spare memory cells are arranged at intersections with the bit lines. Although the array system of this embodiment is a folded bit line system, the present invention can be similarly applied to an open bit line system memory. In the case of the folded bit line system, the bit line is composed of two wires, but is represented by one line here for simplicity. For details of the folded bit line method and the open bit line method, see, for example,
Volume 130, Part 1, Issue 3, pages 127 to 135, June 1983 (IEE PROC., Vol. 130, Pt. I, No. 3, pp. 127-135, June 198)
It is described in 3). Hereinafter, a description will be given of word line defect relief in this embodiment. First, a method for selecting a word line will be described.
In this embodiment, the word lines are selected every two mats. For example, when a certain word line W [i, 0] of the memory mat 110 is selected, the corresponding word line W [i, 2] of the memory mat 112 is selected at the same time. At this time, memory mat 1
Word lines 11 and 113 are not selected. Conversely, when the word lines of the memory mats 111 and 113 are selected, the word lines of the memory mats 110 and 112 are not selected. This is because the word lines W [i, 0] and W [i, 2] are originally one word line divided into two, and are physically two word lines.
This is because it can be logically regarded as one word line. Whether to select the memory mats 110 and 112 or the memory mats 111 and 113 is determined by one of the row address signals (here, the highest A _X [n _W −1]). Note that the final selection of the memory cell is based on the column address signal A _Y [j] (j =
Carried out by 0 to n _B -1). At this time, memory mat 11
Whether the memory cell in 0 or 111 is selected or the memory cell in 112 or 113 is selected
00 is determined using one of the column address signals (here, A _Y [n _B -1] at the highest level). Next, a method of replacing a defective word line with a spare word line will be described. In the conventional example shown in FIG. 27, as shown in FIG. 29, replacement of a normal word line and a spare word line is performed simultaneously by four memory mats. For example, memory mat
When the word line W [0,0] of the 110 is defective, not only W [0,0] but also the corresponding word line W [0,0] of another memory mat.
1], W [0,2] and W [0,3] are also replaced with spare word lines at the same time. However, in the present embodiment, replacement is performed simultaneously with two memory mats selected at the same time. FIG. 2 shows an example of a word line replacement method in this embodiment. For example, if the word line W [0,0] of the memory mat 110 is defective, W [0,0] and W [0,2] are simultaneously replaced with a spare word line. However, the word lines of the memory mats 111 and 113 are not replaced. In order to realize such a replacement method, an uppermost row address A _X [n _W −1] is compared by an address comparison circuit. The row address A _X [n _W −1] is an address that determines a memory mat to be selected as described above. In the conventional example shown in FIG. 27, the replacement by the spare word line is performed simultaneously for all the mats, so that the row address A _X [n _W −1] is not compared in the address comparison circuit. On the other hand, in the present embodiment, the above replacement method is realized by comparing the row addresses A _X [n _W −1]. A first advantage of the present invention is that the number of memory cells simultaneously replaced is reduced by the above replacement method. In the conventional example shown in FIG. 27, N _B
/ 2 × 4 = 2N _B , but in the conventional example of FIG. 1, N _B / 2 × 2
= N _B number to half. As a result, the probability that a spare memory cell in which a normal memory cell has been replaced has a defect is smaller than in the conventional case, and the yield is improved. In this embodiment, the effect is not so remarkable because the number of divisions of the memory array is relatively small, but the effect is very large in a highly integrated memory having a large number of divisions. This is because the probability that all the spare memory cells are not defective is inversely proportional to the exponential function of the number of memory cells. In general, the word line M _W divided, in a memory the bit line is divided M _B, m mat (m is a divisor of M _W M _B) when replacing simultaneously spare word line normal word lines are simultaneously replaced that the number of memory cells, in the conventional method (total mat simultaneous substitution) M _B N _B
MN _B / M _{W in the} method according to the present invention, and the conventional m / M _W
Becomes M _B times (in the example of FIG. _{1, M W = 2, M B} = 2, m =
2). For example, N _W = N _B = 4096, M _W with 16M bit memory
= 4, in the case of M _B = 16, m = 8, the number of memory cells to be replaced at the same time, 65,536 in the conventional method, becomes 8192 and 1/8 in a manner according to the present invention, there is a defect in the spare memory cell The probability is much smaller than before. A second advantage of the present invention is that the use efficiency of spare memory cells is higher than in the conventional method. For example, consider a case where the word line W [i ₁ , 0] of the memory mat 110 and the word line W [i ₂ , 1] (i ₁ ≠ i ₂ ) of the memory mat 111 are defective.
In the conventional system shown in FIG. 27, in order to repair such a defect, a total of eight spare word lines are required, two per memory mat. For example, W [i _1, 0] ~W [i _1, 3] to SW [0,
0] In ~SW [0,3], W [i _2, 0] ~W [i _2, 3] and SW [1,
0] to SW [1,3]. On the other hand, in the case of the present embodiment, repair can be performed with a total of four spare word lines, one for each memory mat. For example, W [i ₁ , 0] and W
[I ₁ , 2] is replaced by SW [0,0] and SW [0,2], and W [i ₂ , 1] and W
[I ₂ , 3] may be replaced by SW [0,1] and SW [0,3], respectively. Therefore, the spare word lines SW [1,0] to SW [1,3]
Can be used for repairing other defects, and an improvement in yield can be expected. Another advantage of the present invention is that the degree of freedom in selecting the number of spare word lines L per memory mat and the number of address comparison circuits R is large. In the conventional method, the normal word line is replaced with the spare word line at the same time for all mats.
Must be R. For example, in FIG. 27, L = R = 4
It is. On the other hand, in the method according to the present invention, since L and R can be selected relatively freely, it is possible to produce an efficient defect relief circuit with a small area. Next, the relationship between L and R will be described. Generally, when replacing simultaneously spare line normalized line of m _{mats, L ≦ R ≦ LM W M} B / m (1) is satisfied. The inequality sign on the left indicates that it is meaningless to provide more spare lines than the number of address comparison circuits in each memory mat. The inequality sign on the right has the following meaning: Each memory mat has spare lines L present, because the number of mats is M _W M _B, the physical has LM _W M _B present in spare line throughout. However, since it is replaced Among m this by simultaneously logical spare line number is LM _W M _B / m present. The inequality sign on the right side of the equation (1) indicates that it is meaningless if the number of address comparison circuits is larger than the number of logical spare lines.
In the conventional method, since m = M _W M _B , L = R must be satisfied. On the other hand, in the method according to the present invention, L, R
Can be freely selected within a range satisfying the expression (1). From the viewpoint of the chip area, it is desirable to increase R rather than L. This is because the area increase due to the provision of one address comparison circuit is usually smaller than the area increase due to the provision of one spare line for all memory mats. In the conventional method, it is impossible to increase only R due to the relation of L = R, but according to the present invention, it is possible. Therefore, by setting L to be relatively small and R to be relatively large, a small-area and efficient defect relief circuit can be produced. That is, the feature of the present invention is to be (1) relationship, excluding the left side of the equal sign from the _{equation, L <R ≦ LM W M} B / m (2). For example, in the embodiment of FIG.
Since M _W = M _B = 2 and m = 2, the expression (2) is L <R ≦ 2L
(Actually L = 2, R = 4). By making R larger than L, there may be cases where the number of defective lines cannot be repaired even though the number of defective lines is R or less. For example, there is a case where defective lines are concentrated on one memory mat, and the number of defective lines is more than L and not more than R. In this case, although the number of address comparison circuits is sufficient, repair is impossible because the number of physical spare lines of the defective memory mat is insufficient. However, the probability that a large number of defects are concentrated on one memory mat is small.
Is set to, for example, two or more, the above problem hardly occurs. This embodiment can be applied to a memory of an address multiplex system and a memory of a non-address multiplex system. Embodiment 2 As is clear from the above description, it is desirable that the number m of word lines simultaneously replaced by the defect relief is smaller. Third
The figure shows an example in which m = 1. The difference from the embodiment of FIG. 1 lies in the method of selecting word lines and the method of replacing defective word lines. In the case of FIG. 1, the word lines are simultaneously selected by two mats at a time, and the replacement with the spare word line is also performed simultaneously by two mats. In this embodiment, the selection of the word line and the replacement with the spare word line are performed for each mat. To achieve this, the column address signal A _Y [n _B
-1] is used. A _Y [n _B −1] is an address for distinguishing the memory mats 110 and 112 and 111 and 113 as described above. First, not only the row address but also A
_Y [n _B -1] is input and one of the four memory mats is input.
Make sure only one is selected. Next, the address comparison circuit compares not only the row address but also A _Y [n _B -1], so that the replacement between the normal word line and the spare word line is one.
Let the mat be done one by one. Accordingly, spare word line selection circuits 610 to 613 are changed as shown in FIG. 8 (a). Here, XR [k] and column address signal A
By taking the logical product with _Y [n _B -1] (or its complement), only the spare word line of the selected memory mat is driven. As described above, the feature of the present embodiment is that the column address is used for word line defect relief. In the conventional defect relief technology, only the row address is used for word line defect relief,
Only the column address was used for the bit line defect relief. However, in a memory divided into mats, the following effects can be obtained by using a column address for repairing a defect of a word line and using a row address for repairing a defect of a bit line as in this embodiment. Is obtained. FIG. 4 shows an example of a word line replacement method in this embodiment. Since the number m of word lines to be replaced at the same time is m = 1, the number of memory cells to be replaced at the same time is as small as 1/2 of the embodiment of FIG. Therefore, the probability that the spare memory cell has a defect is further reduced, and the effect of improving the yield is further increased. Further, since the number of word lines to be replaced at the same time is reduced, the utilization efficiency of the spare memory cell is further improved as compared with the embodiment of FIG. For example, if the word lines W [i ₁ , 0] and W [i ₂ , 1] (i ₁ ≠ i ₂ ) are defective, the embodiment of FIG. 1 requires four spare word lines for repair. Met. On the other hand, in the present embodiment, repair can be performed with two spare word lines. In this embodiment, the number m of word lines to be replaced at the same time is the first
Since it is smaller than that in the case of FIG. 1, the degree of freedom in selecting the number R of address comparison circuits is larger than that in the case of FIG. Therefore, a more efficient defect relief circuit can be made according to the state of occurrence of the defect. This is clear when the present embodiment is compared with the conventional example shown in FIG. For Figure 30, since the provided address comparison circuits corresponding to all of the spare word lines of all the memory mats, R = LM _W L _B, that is, the right side of the equal sign of equation (1) holds. However, in the present invention, the equal sign on the right side of Expression (1) does not always need to hold. This means that if the number of defects is not so large, R can be reduced as compared with the case of FIG. Therefore, an increase in the chip area due to the address comparison circuit can be suppressed.
In the present embodiment, because it is m = 1, L = 2, a L = 2 ≦ R ≦ 8 = LM W M B / m, in practice a R = 4. Third Embodiment FIG. 5 shows a third embodiment of the present invention. In this embodiment, the address comparison circuit and the spare word line selection circuit are not directly connected, but are connected to the switch circuit 510 via the OR gates 505 and 506. However, the spare word line selection circuits 620 to 623 are changed as shown in FIG. Here, XL [k] and an address signal for selecting a memory mat
By taking the logical product of A _X [n _W -1] and A _Y [n _B -1] (or its complement), only the spare word line of the selected memory mat is driven. . The features of this embodiment are as follows. The first feature is that the number of wires from the defect relief circuit 500 to the spare word line selection circuits 620 to 623 is reduced. The number of wirings is R in the embodiment shown in FIG. 3, and L in this embodiment. As described above, in the present invention, L <R is generally satisfied, so that the number of wirings is smaller in this embodiment. The second feature is that the correspondence between the address comparison circuit and the spare line can be flexibly changed, so that the flexibility of use of the address comparison circuit is large. The correspondence between the address comparison circuit and the spare line is fixed not only in the conventional example but also in the previous embodiments. For example, in the conventional example of FIG. 27, AC [k] is dedicated to SW [k, 0] to SW [k, 3] (k =
0-3). In the conventional example of FIG. 30, AC [k, l] is SW [k, l].
It is dedicated (k = 0,1, l = 0-3). In the embodiment shown in FIG. 3, AC [2k] is dedicated to SW [k, 0] and SW [k, 2].
[2k + 1] is dedicated to SW [k, 1] and SW [k, 3] (k = 0,
1). However, in the present embodiment, there is no such restriction, and one address comparison circuit can correspond to any spare word line by switching the address stored in the address comparison circuit and the switching of the switch circuit 510. Of the addresses stored in the address comparison circuit, A _X [n _W -1]
And two bits of A _Y [n _B -1] determine one memory mat, and switch 510 determines one spare word line in the memory mat. As a result, the probability of successful defect remedy increases. For example, consider a case where each of the memory mats 110 and 112 has two defective word lines. Such a defect cannot be repaired in the embodiment shown in FIG. 3, but can be repaired in the present embodiment. The third feature is that the correspondence between the address comparison circuit and the spare line can be flexibly changed as described above, so that the address comparison circuit is resistant to failure. For example, a spare word line
Address comparison circuit AC to use SW [0,0]

[0]
Suppose that you tried to use it and it was out of order. In this case, for example, AC [1] may be used. In addition to the above three points, the features of the embodiment shown in FIG. 3 described above also apply to this embodiment. FIG. 6 shows an example of the switch circuit 510 used in this embodiment. In the figure, 511 is a fuse cut by a laser, 512,
518 and 520 are N-channel MOS transistors, 517 and 519 are P
Channel MOS transistor, 513 is an inverter, 514, 515
Is a NAND gate. When the fuse is not blown, node 532 is low, 533 is high and terminal x
And z conduct. When the fuse is blown, node 532
Is at a high level, 533 is at a low level, and the terminals y and z conduct. This embodiment is an improvement of the embodiment of FIG. 3, but the same improvement is possible with respect to the embodiment of FIG. Embodiment 4 FIG. 7 shows a fourth embodiment of the present invention. In this embodiment, the outputs XR of four (generally R) address comparison circuits are used.

[0] to XR [3] are not wired as they are, and two (usually R / L) are ORed together (generally L
Pcs) signal XL

[0] and XL [1] are wired. However, the spare word line selection circuits 620 to 623 are
Change as shown in FIG. Here, XL [k] and address signals A _X [n _W −1] and A _Y [n _B
-1] (or its complement) so that only the spare word line of the selected memory mat is driven. The features of this embodiment are as follows. First, the features of the embodiment of FIG. 5 described above apply to this embodiment as it is. That is, first, the number of wires from the defect relief circuit to the spare word line selection circuit is small. Second, since the correspondence between the address comparison circuit and the spare line can be flexibly changed, the flexibility of use of the address comparison circuit is large.
Third, it is resistant to failure of the address comparison circuit. In addition, this embodiment has the following features. First, the circuit configuration is simpler than that of the embodiment shown in FIG. Next, the correspondence between the address comparison circuit and the spare line can be changed simply by changing the address stored in the address comparison circuit without cutting the fuse of the switch circuit. Of the addresses stored in the address comparison circuit, A _X
One memory mat is determined by two bits [n _W -1] and A _Y [n _B -1]. In the present embodiment, as is apparent from the above description, R is L
It is desirable to be a multiple of. This embodiment is an improvement of the embodiment of FIG. 3, but the same improvement is possible with respect to the embodiment of FIG. Note that the methods shown in FIGS. 3, 5, and 7 are better than the method (m = 2) in FIG. 1 in that m = 1 as described above. This method cannot be directly applied to word line defect repair of a normal address multiplex DRAM. The first reason is that the number of simultaneously selected word lines cannot be arbitrarily set because the DRAM needs to refresh the memory cells. The number of memory cells to be refreshed at the same time, a is whereas N _B Coil case of FIG. 1, FIG. 3, FIG. 5, in the case of Figure 7 is N _B / 2 pieces. So DR these methods
To apply to AM, the specification of the number of refresh cycles needs to be changed. The second reason is that at the time of word line selection, the column address signal has not been input yet and cannot be used because of the address multiplex system. However, if there is no such problem, for example, SR
In the case of AM or when there is no restriction on the number of refresh cycles in a DRAM which is not an address multiplex method, these methods can be applied. These methods can be applied to a bit line defect relief even in a normal DRAM. This is because the number of bit lines selected simultaneously does not affect the number of refresh cycles, and the row address signal has already been input at the time of bit line selection. [Embodiment 5] For the above-described reason, in the case of relieving a defect of a word line of a DRAM, it is desirable to simultaneously replace memory cells that are simultaneously refreshed, as in the embodiment of FIG. However, even in the case of a DRAM word line defect remedy, m = 1 can be set in the case as shown in FIG. In this method, the memory array is divided into four parts, but the word lines are not divided but the bit lines are divided into four parts. The method of relieving defects is the same as in the embodiment of FIG. In this case, the number of memory cells to is also N _B number and Figure 1 to be refreshed simultaneously,
This is because both address signals that determine the selected memory mat are row address signals. In this embodiment, only one Y decoder 40 is provided at the end, and the output YS [j] is supplied to each memory mat by a wiring indicated by a chain line in the figure. This is a technique called a multi-divided bit line, which aims to reduce the area by sharing the Y decoder with a plurality of memory mats. Further, the sense amplifier and the input / output line are shared by two memory mats. I.e. 240 to 130 and 131
The 241 is shared by 132 and 133 respectively. This is a technique called shared sense, which is effective in reducing the area of the sense amplifier. For multi-divided bit lines and shared sense, for example,
C.C., Digest of Technical Papers, pp. 282-283, February 1984 (ISSCC Digest
of Techninal Papers, pp. 282-283, Feb. 1984) or JP-A-57-198592. The first to fifth embodiments are examples in which the present invention is applied to word line defect relief. However, the present invention is also applicable to bit line defect relief. [First Embodiment of Address Comparison Circuit] An address comparison circuit used in the present invention will be described. FIG. 10 is an example of an address comparison circuit used in the semiconductor memory of FIG. In the figure, 801 is an N-channel MOS transistor, 802 and 803 are P-channel MOS transistors, and 804 is an inverter. 810 is one of the bad addresses
A bit comparison circuit for storing bits and comparing the bits with one bit of an address signal, 811 is a fuse cut by a laser, 812 and 821 to 824 are N-channel MOS transistors, 817 to 820 are P-channel MOS transistors, 813 is an inverter, and 814 and 815 are NAND gates. Hereinafter, the operation of this circuit will be described. First, the transistor 802 is turned on by setting the precharge signal XDP to low level, and the node 805 is set to high level. At this time, the output XR is at a low level. Next, an address signal A _X [i] (i = 0 to n _W −1) is applied. Each bit comparison circuit 810 compares one bit of the defective address stored in the circuit with A _X [i], and if they match, outputs Cx [i].
[I] is set to a high level, and if they do not match, set to a low level. When the comparison results of all the bit comparison circuits match, all the transistors 801 are turned on. At this time, node 805
Is discharged to a low level, and the output XR goes to a high level. That is, it is determined that the applied address matches the defective address. If at least one bit of the address does not match, node 805 is not discharged, and therefore output XR
Remains at a low level. Note that the transistor 803 is
A transistor having a relatively small transconductance for latching the potential of the node 805.
When node 805 is not discharged, transistor 803 is conductive because output XR is low. Thus, the potential of the node 805 is kept at a high level. Next, the bit comparison circuit 810 will be described in detail. This circuit stores one bit of a defective address depending on whether the fuse 811 has been blown or not. Here, the state where the fuse is not blown corresponds to “0”, and the state where the fuse is blown corresponds to “1”. When the fuse is not blown, node 830 is high, 8
31 goes low. Two cross-coupled NAND gates
The output of the latch consisting of 814 and 815 is low at node 832 and high at 833. Therefore, the address signal A
_{When X} [i] = “0”, that is, when the true signal A _X [i] is low and the complementary signal / A _X [i] is high, the output C
[I] becomes high level. When the fuse is blown, the potential of each node is opposite to the above, and the address signal
When A _X [i] = “1”, the output C [i] goes high. Note that one of the bit comparison circuits includes an address signal A
_X [i], / instead of A _X [i], respectively the power supply Vcc, a timing signal / phi _A A (signal that changes at the same timing as the address signal from the high level to the low level) is input. This is a so-called enable circuit for determining whether or not to use this address comparison circuit for defect relief. If used, blow the fuse. When the fuse is not blown, the output E of the enable circuit is always at a low level, so that the output XR of the address comparison circuit is always at a low level. As described above, in the embodiments of FIGS. 3, 5, and 7, the column address A _Y [n _B -1] is also compared. This can be realized by adding one bit comparison circuit 810 and one MOS transistor 801. The device for storing the defective address is not limited to the fuse cut by the laser shown here. An electrically cut fuse or a nonvolatile memory such as an EPROM may be used. [Embodiment 2 of Address Comparison Circuit] FIG. 11 shows another embodiment of the address comparison circuit. This embodiment is suitable for application to the semiconductor memory shown in FIG. 7 or FIG. The difference from the previous embodiment is that two sets (850 and 851) of circuits combining the bit comparison circuit 810 and the N-channel MOS transistor 801 are provided. Defective addresses are stored in the circuits 850 and 851, respectively. Hereinafter, the operation of the present embodiment will be described. First, the precharge signal XDP is set to low level, and the node 805 is set to high level. Next, the address signal A _X
[I] (i = 0 to n _W −1) is applied. At this time, the circuit
At 850 and 851, a comparison is made with the defective address, respectively. When the applied address matches one of the bad addresses stored in circuits 850, 851, node 805 is discharged and output XL goes high. As is clear from the above description, the circuit of this embodiment is equivalent to the circuit in which the OR gate (502 or 503) is added to the two address comparison circuits in the defect relief circuit of FIG. 7 or FIG. . Therefore, if this circuit is used, the OR gate shown in FIG. 7 or FIG. 9 is not required. And node 80
Since the discharge time of No. 5 is the same as the previous embodiment, the delay due to the addition of the OR gate can be eliminated. [Effect of Don't Care] In the case of relieving a bit line of a memory having a configuration as shown in FIG. 9, a defect may occur over a plurality of memory mats. This is because the Y decoder and the sense amplifier are shared by a plurality of memory mats. However, this problem can be solved by storing not only "0" and "1" but also a don't care value "X" in the address comparison circuit as described below. Hereinafter, an embodiment using a don't care value will be described. Embodiment 6 FIG. 12 shows a sixth embodiment of the present invention. In the figure, 10 is a memory array, 20 is a sense amplifier and input / output lines, and 30 is X
A decoder, 40 is a Y decoder, 500 is a defect relief circuit, 630 is a spare bit line selection circuit (the configuration is the same as in FIG. 33), 701 is a data input buffer, and 702 is a data output buffer. The memory array 10 includes an area 14 where regular memory cells are arranged and an area 15 where spare memory cells are arranged.
Consists of The regions 14, N _W of word lines W [i] (i =
0 to N _W -1) and N _B bit lines B [j] (j = 0 to N _B -
The intersection of the 1), N _W × N memory cells M [i, j] of _B is arranged. The regions 15, N _W (in this case L = 2) of word lines and L the spare bit line SB [k] of the (k = 0~L-
_NW × L spare memory cells are arranged at the intersection with 1). Although the array system of this embodiment is a folded bit line system, the present invention can be similarly applied to an open bit line system memory. For details of the folded bit line method and the open bit line method, see, for example, IEE, Proceeding, Vol. 130, Part 1, Part 3
No. 127-135, June 1983 (IEE PROC., Vol.
130, Pt. I, No. 3, pp. 127-135, June 1983). Hereinafter, the feature of the defect relief in the present embodiment will be described. The feature of the defect relief circuit of this embodiment is that each address comparison circuit AC [k] outputs not only a column address signal but also a row address signal _AX.

[0] to A _X [n _W -1] are input, and the don't care value “X” can be stored in the address comparison circuit. This makes it possible to compare or not compare the row addresses in the address comparison circuit. In the case of the conventional example shown in FIG. 32, only the column address is compared in the address comparison circuit. This is because replacement of normal memory cells with spare memory cells is performed in bit line units. Also in the present embodiment, if the row addresses are not compared, the replacement in units of bit lines as in the related art can be realized. On the other hand, if row addresses are compared, normal memory cells and spare memory cells can be replaced in 1-bit units. This will be described with reference to FIG. FIG. 14 is a table showing an example of a method of replacing a regular memory cell with a spare memory cell, which is possible in the defect relief circuit of the present embodiment. In the drawing, the mark "○" indicates that the address is compared ("0" or "1" is stored), and the mark "x" indicates that the address is not compared ("X" is stored). If both the row address and the column address are compared as in the first example of the table, the normal memory cell and the spare memory cell are replaced in units of 1 bit. If row addresses are not compared as in the third column, replacement is performed in bit line units as in the related art. Also, if only the least significant bit of the row address is not compared as in the second column,
Replacement is performed in units of two bits. As described above, another feature of the present embodiment is that the row address is used for bit line defect relief. In the conventional defect relief technique, only a row address is used for word line defect relief, and only a column address is used for dot line defect relief. However, by using a row address for bit line defect relief as in the present embodiment, or conversely, using a column address for word line defect relief, the above various replacement methods can be realized. . An advantage of the present invention is that various defects of a semiconductor memory can be finely dealt with by the various replacement methods as described above. In general, semiconductor memory failures include 1-bit failures (for example, caused by pinholes in memory cell capacitors), bit-to-bit failures (for example, due to contact failures), and bit line failures (for example, due to bit line disconnections). is there. In the conventional example shown in FIG. 32, even if one bit is defective, the entire bit line including the defective memory cell is replaced with a spare bit line. On the other hand, in the present embodiment, only one defective memory cell can be replaced with a spare memory cell in the case of 1-bit failure, and only two defective memory cells can be replaced in the case of a bit failure. Of course, in the case of a bit line failure, replacement in bit line units is possible as before. By replacing only the minimum necessary memory cells with spare memory cells in this manner, the probability that a spare memory cell in which a regular memory cell has been replaced has a defect is smaller than in the conventional case, and the yield is improved. This is because the probability that all the spare memory cells are not defective is inversely proportional to the exponential function of the number of memory cells. Further, since the minimum necessary spare memory cells are used for repairing a defect, the utilization efficiency of the spare memory cells is improved. For example, regular memory cells M [i ₁ , j ₁ ] and M [i ₂ , j ₂ ] (i ₁ ≠
Consider a case where i ₂ , j ₁ ≠ j ₂ ) is bad. In such a case, the conventional method requires two spare bit lines for restoration. However, in the case of the present embodiment, for example, the address comparison circuit AC

Replace [0] with the defective address [i ₁ , j ₁ ]
By storing [i ₂ , j ₂ ] in [1], one spare bit line SB

The restoration can be performed only by [0]. Therefore, the spare bit line SB [1] can be used for repairing other defects, and an improvement in yield can be expected. Next, details of the defect relief circuit 500 will be described. The defect relief circuit of the present embodiment has R (here, R = 4) address comparison circuits AC [k] (k = 0 to R−1) and R / L (here, R / L = 2) address comparison circuits. OR gates 502, 503, and NOR gate
Consists of 504. Output YR of R address comparison circuits

[0]
L signals YL obtained by ORing .about.YR [3] R / L each

[0] and YL [1] are wired to the spare bit line selection circuit 630, and are used to select a spare bit line. NOR gate 5
04 is YR

This is for disabling the Y decoder 40 when any one of [0] to YR [3] becomes high level. A feature of the present invention is that the number of spare bit lines L and the number of address comparison circuits R can be freely selected. In the conventional method, since replacement is performed in units of bit lines, L = R
Must. For example, in FIG. 32, L = R = 4. On the other hand, in the method according to the present invention, since L and R can be selected relatively freely, it is possible to produce an efficient defect relief circuit with a small area. Next, the relationship between L and R will be described. In general, assuming that the number of normal memory cells to be replaced with spare memory cells at a time is b, the following holds: L ≦ R ≦ LN _W / b (3) The inequality sign on the left indicates that it is meaningless to provide more spare lines than the number of address comparison circuits. The inequality sign on the right has the following meaning: Although the spare memory cell is LN _W pieces, since it is replaced Among b or by simultaneously, the degree of freedom of substitutions are LN _W / b. Therefore, it is meaningless to increase the number of address comparison circuits. In the conventional method (replacement per bit line), b = N _W
Therefore, L = R must be satisfied. In the manner of this embodiment contrast, b is from can be chosen freely in a range of _{1 ≦ b ≦ N W, L} , the degree of freedom of selection of the R becomes large. From the viewpoint of the chip area, it is desirable to increase R rather than L. This is because the area increase due to the provision of one address comparison circuit is usually smaller than the area increase due to the provision of one spare line for all memory mats. In the conventional method, it is impossible to increase only R due to the relation of L = R, but according to the present invention, it is possible. Therefore, by setting L to be relatively small and R to be relatively large, a small-area and efficient defect relief circuit can be produced. That is, the feature of the present invention is that L <R ≦ LN _W / b (4) can be obtained by removing the left-hand equal sign from the equation (3). For example, in the embodiment of FIG.
L = 2 and R = 4. As is apparent from this example, it is desirable that R be a multiple of L. Embodiment 7 FIG. 15 shows a seventh embodiment of the present invention. The difference from the previous embodiment lies in the wiring method of the output of the address comparison circuit.
In this embodiment, YR

The signal YL, which is the logical sum of [0] to YR [3], is routed to the spare bit line selection circuit 640. Accordingly, the configuration of the spare bit line selection signal 640 is changed as shown in FIG.
Or, change as shown in (b). This is to prevent multiple selection of spare bit lines. In (a), YL and an address signal A _Y for selecting a bit line are used.

By taking the logical product with [0] (or its complementary signal), in (b), the bit line selection signal φ _{Y is changed} to A _Y

By generating the signals φ _Y0 and φ _Y1 predecoded by [0], only one spare bit line is selected. The feature of this embodiment is that replacement is required for two bit lines. This will be described with reference to FIG. The first, second, and fifth columns of the table are for a bit failure, a bit failure, and a bit line failure, respectively, as in FIG. The third column is a defective bit, but two adjacent bits on the same word line are defective (the second column is two adjacent bits on the same bit line). Such a defect is caused by, for example, a short circuit between the memory cell capacitors. The fourth column shows a case where 2 × 2 bits are defective. Such a defect is caused by a contact defect in the case of an SRAM, for example. The sixth column shows a case where two adjacent bit lines are defective. Such a defect is caused by, for example, a short circuit between bit lines. By using this embodiment, it is possible to easily repair the above-described various defects. Another feature of this embodiment is that the number of wirings between the defect relief circuit 500 and the spare bit line selection circuit 640 can be reduced. Embodiment 8 FIG. 18 shows an eighth embodiment of the present invention. The difference from the previous two embodiments is that the memory array is divided into a plurality (here, four) of memory mats 130 to 133 in the bit line direction. Each memory mat includes regions 140 to 143 where normal memory cells are arranged and regions 150 to 153 where spare memory cells are arranged. Each of the regions 140-143, N _W / 4 word lines W [i, n] _{(i = 0~N W / 4-1,} n =
0-3) and N _B bit lines B [j, n] (j = 0~N _B -1, n
_{= 0~3) N W × N B} / 4 pieces of memory cells at intersections of the are arranged. Each of the regions 150~153, N _W / 4 word lines [i, n] of the _{(i = 0~N W / 4-1,} n = 0~3) and L the (in this case L = 2) Spare bit line B [k, n] (k = 0 to L-
1, n = 0~3) and N _W × L / 4 pieces of spare memory cells at the intersection is arranged. Sense amplifier and input / output lines 230 to 233
Are provided corresponding to the respective memory mats. However, only one Y decoder 40 is provided at the end. The output YS [j] of the Y decoder is supplied to each memory mat by wiring shown by a dashed line in the figure. The same applies to the output SYS [k] of the spare bit line selection circuit 630.
This is a method called bit line division, in which the area is reduced by sharing the Y decoder with a plurality of memory mats. Bit line division is described in, for example, ISCC, Digest of Technical Papers, pp. 282 to 283, February 1984 (ISSCC, Digest of Techninal papers, pp. 282-283, Fe
b.1984) or JP-A-57-198592. The present invention is particularly effective when a plurality of memory mats share a circuit (in this case, a Y decoder and its output wiring) as in the present embodiment. This is because, if the shared circuit has a defect, a defect over a plurality of memory mats occurs. However, such a defect can be easily repaired by using the present invention. This will be described with reference to FIG. The first and second columns of the table are for bit failure and bit failure, respectively, as in FIG.
The third column is for a bit line failure. However, in this case, since the memory array is divided into four, the address signal for selecting the memory mat (here, the upper two bits of the row address, A _X [n _W -1] and A _X [n _W -2]) Is also compared. Thereby, only the bit line of one memory mat is replaced with the spare bit line. The fourth column of the table shows the case where the Y decoder is defective. In this case, _Ax [ _nW- 1] and _Ax [ _nW- 2] are not compared. Thereby, the bit lines at the corresponding positions of the four memory mats are simultaneously replaced with the spare bit lines. Embodiment 9 FIG. 20 shows a ninth embodiment of the present invention. The difference from the embodiment of FIG. 18 is that the sense amplifier and the input / output line are shared by two memory mats. That is, 24
0 is shared by 130 and 131, and 241 is shared by 132 and 133, respectively. This is a technique called shared sense, which is effective in reducing the area of the sense amplifier. The above-mentioned documents and published patent publications also describe shared sense. In the case of the present embodiment, if there is a defect in the sense amplifier, the corresponding bit lines on the left and right mats are simultaneously defective. However, with the present invention, such a defect can be easily repaired. This will be described with reference to FIG. The first column, the second column, the third column, and the fifth column of the table are for a bit defect, a bit defect, a bit line defect, and a Y decoder defect, respectively, as in FIG. The fourth column is for a sense amplifier failure. In this case, among the row addresses, the memory mat 13
Only the address signal (here, A _X [n _W -1]) that determines whether to select 0, 131 or 132, 133 is compared.
Thereby, the bit lines at the corresponding positions of the left and right memory mats of the sense amplifier are simultaneously replaced with the spare bit lines. The above-described embodiments 6 to 9 are all examples in which the present invention is applied to bit line defect relief. However, the defect relief using the don't care value can also be applied to word line defect relief. Third Embodiment of Address Comparator Next, an address comparator used in the sixth to ninth embodiments will be described. The address comparison circuit used here is
As described above, a feature is that three values of "0", "1", and "X" can be stored as defective addresses. FIG. 22 shows a third embodiment of the address comparison circuit. In the figure, reference numeral 800 denotes an AND gate. A bit comparison circuit 810 stores one bit of a defective address and compares it with one bit of an address signal. Reference numerals 861 to 863 denote laser cut fuses, 864 and 867 denote inverters, and 865 and 866 denote NAND gates. Reference numeral 809 denotes an enable circuit for determining whether to use the address comparison circuit for the defect rescue circuit. Reference numeral 811 denotes a fuse cut by a laser, 812 denotes an N-channel MOS transistor, 813 and 816 denote inverters, and 814 and 815 denote NAND gates. Hereinafter, the operation of this circuit will be described. First, the enable circuit will be described. When using the address comparison circuit for defect relief, first, the fuse 811 in the enable circuit is cut. This sets node 830 to low level, 831 to high level, 832 to high level, 8
33 goes low. Therefore, the enable signal E becomes high level. When the fuse 811 is not blown, the potential of each node is opposite to the above, and the enable signal E becomes low level. Next, the bit comparison circuit will be described. The bit comparison circuit 810 compares the value stored according to the blow state of the fuse with the address A _X [i] (or A _Y [j]),
If they match, the output C _X [i] (or C _Y [j]) is set to a high level, and if they do not match, the output is set to a low level. The method of cutting the fuse is as follows. To store “0”, the fuses 861 and 862 are cut. Thus, when the address is “0”, that is, when the true signal A _X [i] (or A
_Y [j]) is low level and the complement signal / A _X [i] (also / A
_{When Y} [j]) is at a high level, the output C _X [i] (or C _Y
[J]) goes high. To store “1”, the fuses 861 and 863 are cut. Thus, when the address is “1”, that is, when the true signal A _X [i] (or A
_Y [j]) is at a high level and the complementary signal / A _X [i] (also / A
_{When Y} [j]) is low, the output C _X [i] (also / C
_Y [j]) goes high. To store “X”, fuses 862 and 863 are blown. At this time, regardless of the address, the output C _X [i] (and / C _Y [j])
Is at a high level. When the comparison results of all the bit comparison circuits match, the output YR of the AND gate 800 goes high. That is, it is determined that the applied address matches the defective address. If even one bit of the address does not match, YR goes low. The above is the case where the enable signal E is at a high level. When the enable signal E is low, the outputs C of all the bit comparison circuits
_X [i] (also / C _Y [j]) is low, and therefore YR is also low. The feature of this embodiment is that the circuit scale is small, and therefore the occupied area can be reduced. The device for storing the defective address is not limited to the fuse cut by the laser shown here.
An electrically cut fuse or a nonvolatile memory such as an EPROM may be used. [Embodiment 4 of Address Comparison Circuit] FIG. 23 shows a fourth embodiment of the address comparison circuit. The difference from the previous embodiment lies in the configuration of the bit comparison circuit 810. 871, 881, 882 are laser cut fuses, 872
Is an N-channel MOS transistor, 873 and 887 are inverters, 874, 875, 885 and 886 are NAND gates, and 883 and 884 are OR gates. Hereinafter, the operation of this circuit will be described. To store “X” in the bit comparison circuit 810, the fuse 871 is blown. This causes node 890 to be low, 891 to be high, 892 to be high, and 893 to be low. Therefore, since the don't care signal D becomes high level, the output C _X [i] (or
/ C _Y [j]) goes high. When storing “0” or “1”, the fuse 871 is not blown. At this time,
D is low level. To store “0”, the fuse 881 is blown. Thus, when the address is "0", that is, the true signal A _X [i] (or A _Y [j]) is at a low level, and the complementary signal / A _X [i] (or / A _Y [j]) is high. The output C _X [i] (or C _Y [j]) goes high when the level is high. To store “1”, the fuse 882 is cut. Thus, when the address is "1", that is, the true signal A _X [i] (or A _Y [j]) is at a high level, and the complementary signal / A _X
Output C _X when [i] (or / A _Y [j]) is low level
[I] (or C _Y [j]) goes high. A feature of the circuit of this embodiment is that the number of fuses to be cut may be one (two in the previous embodiment) when any of "0", "1", and "X" is stored. As a result, the time required for defect relief during inspection can be reduced. Another feature is that although not shown, the don't care signal D can be shared by a plurality of bit comparison circuits. For example
To realize the five replacement methods shown in Fig. 21, A _X
Don't care signals of [1] to A _X [n _W -3] may be common.
In such a case, only one set of circuits consisting of 871 to 875 is required, so that the occupied area can be reduced. [Fifth Embodiment of Address Comparison Circuit] FIG. 24 shows a fifth embodiment of the address comparison circuit. The difference from the previous embodiment lies in the configuration of the bit comparison circuit 810. 901 and 911 are fuses cut by laser, 902 and 912
Is an N-channel MOS transistor, 903, 913 are inverters, 904, 905, 914, 915 are NAND gates, 917, 918, 91
9, 920 are P-channel MOS transistors 921, 922, 923, 92
4 is an N-channel MOS transistor. Hereinafter, this operation will be described. When neither fuse 901, 911 is blown, nodes 932 and 942 are low. Therefore, regardless of the address, the bit comparison circuit 810
Output C _X [i] (or C _Y [j]) is high.
This is a state where “X” is stored. To store “0”, the fuse 901 is blown. This causes node 932 to go high and node 942 to go low. Therefore, when the address is "0", that is, the true signal A _X [i]
(Or A _Y [j]) is low and the complement signal / A _X [i] (or / A _Y [j]) is high, the output C _X [i] (or C _Y [j]) is high. Become a high level. To store “1”, the fuse 911 is blown. This causes node 932 to go low and node 942 to go high. Therefore,
When the address is "1", that is, the true signal A _X [i] (or A _Y [j]) is at a high level, and the complementary signal / A _X [i] (or / A _Y
[J]) is low, the output C _X [i] (or C
_Y [j]) goes high. The feature of this embodiment is that the number of fuses is smaller than that of the previous two embodiments, so that the occupied area can be reduced. Moreover, the fuse does not need to be blown when "X" is stored, so that the time required for defect remedy can be further reduced as compared with the previous embodiment. Another feature is that the address comparison circuit can be invalidated by cutting both the fuses 901 and 911. At this time, since C _X [i] (or C _Y [j]) is always low, YR is also always low. This function can be used when a spare memory cell replacing a normal memory cell is defective. For example, twelfth
In the semiconductor memory shown in the figure, a defective bit line is replaced with a spare bit line SB.

[0], the address comparison circuit AC

Using [0], SB

[0] is assumed to be defective. In this case, AC

[0] is invalidated by the above-described method, and the spare bit line SB [1] is replaced by using, for example, AC [2].
Can be replaced by In the third to fifth embodiments of the address comparison circuit introduced above,
The don't care value “X” can be stored in all the bit comparison circuits. However, it may not be necessary to store "X" in some bit comparison circuits. For example, the 21st
To implement the five replacement methods shown in the figure, A
_Y

It is not necessary to store “X” in the bit comparison circuits for [0] to A _Y [n _W −1]. In such a case, A _Y

[0] to A _Y
By using a circuit that cannot store “X” as the bit comparison circuit for [n _B −1], for example, the circuit shown in FIG. 10, the occupied area can be reduced. Further, for example, when only the three replacement methods of the third to fifth columns in FIG. 21 are realized (that is, the replacement is not performed in bit units or bit units), the following may be performed. A _X [ _nW- 2], A
Only 2 bit _X [n _W -1], using a bit comparator circuit capable of storing a "X", A _Y

A bit comparison circuit that cannot store “X” is used for [0] to A _Y [n _B −1]. A _X

[0] to A
_No bit comparison circuit for _X [n _W -3] is required.

【The invention's effect】

According to the present invention, the number of memory cells that are simultaneously replaced by defect relief is reduced, the probability that the spare memory cell itself has a defect is reduced, and the utilization efficiency of the spare memory cell is increased. Further, the degree of freedom in setting the number of spare lines and the number of address comparison circuits of each memory mat increases. This makes it possible to produce a defect relief circuit having a small area and a large yield improvement effect.

[Brief description of the drawings]

FIG. 1, FIG. 3, FIG. 5, FIG. 7, FIG. 9, FIG.
FIGS. 15, 18, and 20 are block diagrams showing the configuration of a semiconductor memory according to an embodiment of the present invention. FIGS. 2 and 4 are diagrams showing the relationship between a normal word line and a spare word line in a semiconductor memory according to the present invention. FIG. 6 is a circuit diagram of a switch circuit used in the present invention, FIG. 8 is a circuit diagram of a spare word line selecting circuit used in the present invention, FIG. 10, FIG. 11, FIG. Figure 23,
FIG. 24 is a circuit diagram of an address comparison circuit used in the present invention,
Fig. 13 is a table for explaining don't care values, Figs. 14 and 17
FIG. 19, FIG. 19, and FIG. 21 are tables for explaining defect repair according to the present invention, FIG. 16 is a circuit diagram of a spare bit line selection circuit used in the present invention, FIG. 25, FIG. 27, and FIG. , FIG. 32 is a block diagram showing the configuration of a conventional semiconductor memory, FIGS. 26 and 28 are circuit diagrams of a spare word line selection circuit used in a conventional semiconductor memory, and FIGS. 29 and 31 are conventional semiconductor memories. FIG. 7 is a diagram showing a method of replacing a regular word line and a spare word line in a memory,
FIG. 33 is a circuit diagram of a spare bit line selection circuit used in a conventional semiconductor memory. Description of the code 10: memory array, 100 to 103, 130 to 133 ... memory mat, 20, 200 to 203, 230 to 233, 240, 241 ... sense amplifier and input / output line, 30, 300, 301, 310 to 313, 330 to 333 ... X decoder, 40, 400, 410, 411 ... Y decoder, 500 …… Defect relief circuit, 600,610 to 613,620 to 627 …… Spare word line selection circuit, 630,640 …… Spare bit line selection circuit, 700 …… Mux, 701 …… Data input buffer, 702 …… Data output buffer, W [i ], W [i, 0]-W [i, 3] ... regular word line, SW
[K, 0]-SW [k, 3] .... Reserved word line, B [j], B [j,
0] to B [j, 3]… regular bit lines, SB [k], SB [k,
0] to SB [k, 3]... Spare bit line, YS [j]... Y decoder output line, AC [k].

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kiyoo Ito 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (56) References JP-A-59-135700 (JP, A) (58) Surveyed field (Int.Cl. ⁶ , DB name) G11C 29/00 G11C 11/401 G11C 11/413

Claims (31)

(57) [Claims] A memory array including a plurality of memory cells provided at predetermined intersections between a plurality of normal word lines and spare word lines and a plurality of bit lines, and a defective address for a defective word line including a defect. A plurality of address comparing means for comparing with an address requested for access, and means for replacing the defective word line or the normal word line including the defective word line with the spare word line according to a comparison result of the address comparing means. The memory array is divided into M (M ≧ 2) memory mats, and among the M memory mats, the defective word line or the normal word line including the defective word line and the spare The number m of memory mats in which word lines are simultaneously replaced is M
A number L of spare word lines included in each of the M memory mats, a number R of the plurality of address comparing means,
A semiconductor device, wherein the relationship of L <R <LM / m is established between M and m. 2. The semiconductor device according to claim 1, wherein said spare word line is selected by one output of said plurality of comparing means determined by comparing said address with said defective address. 3. The R address comparing means is divided into the L address comparing means groups, and the L address comparing means formed by the logical sum of outputs of a plurality of address comparing means of each address comparing means group. 3. The semiconductor device according to claim 1, wherein a signal is used for selecting said spare word line of each memory mat. 4. A memory array including a plurality of memory cells provided at predetermined intersections between a plurality of word lines and a plurality of normal bit lines and spare bit lines, and a defective address corresponding to a defective bit line including a defect. A plurality of address comparing means for storing and comparing with an access requested address; and replacing the defective bit line or the normal bit line including the defective bit line with the spare bit line according to a comparison result of the address comparing means. Means, wherein the memory array is divided into M (M ≧ 2) memory mats, and among the M memory mats, the defective bit line or the normal bit line including the defective bit line and The number m of memory mats in which the spare bit lines are simultaneously replaced is M
A number L of spare bit lines included in each of the M memory mats, a number R of the plurality of address comparing means,
A semiconductor device, wherein the relationship of L <R <LM / m is established between M and m. 5. The semiconductor device according to claim 4, wherein said spare bit line is selected by one output of said plurality of comparing means determined by comparing said address with said defective address. 6. The R address comparing means is divided into the L address comparing means groups, and the L address comparing means formed by the logical sum of outputs of a plurality of address comparing means of each address comparing means group. 6. The semiconductor device according to claim 4, wherein a signal is used for selecting said spare bit line of each memory mat. 7. The semiconductor device according to claim 3, wherein said logical sum is formed by a logical OR circuit. 8. The semiconductor device according to claim 1, wherein said semiconductor device is a dynamic random access memory having a storage capacity of 16 Mbits or more. 9. First and second memory mats each having a plurality of memory cells provided at intersections of a plurality of word lines, a plurality of bit lines, and spare bit lines, and the first and second memory mats. A plurality of bit line selection lines provided corresponding to each of the plurality of bit lines; a spare bit line selection line for selecting the spare bit line of the first and second memory mats; A defect rescue circuit provided to control selection of a line selection line, and to which access information for specifying one of the first and second memory mats and one of the plurality of bit line selection lines is input; And a signal for selecting the spare bit line selection line when the access information and the information stored in the first storage circuit match with each other. To A first comparison circuit to be formed, wherein the first storage circuit stores first information for designating a memory mat related to a first defect among the first and second memory mats. And a second area for storing second information for designating a bit line selection line associated with the first defect among the plurality of bit line selection lines. A semiconductor device, wherein one of the second memory mats is selected, and one of the plurality of word lines of the selected memory mat is selected. 10. The semiconductor device according to claim 9, wherein said defect rescue circuit compares the access information with the information stored in the second storage circuit when the access information matches the information stored in the second storage circuit. A second comparison circuit that forms a signal for selecting a spare bit line selection line, wherein the second storage circuit specifies a memory mat related to a second defect among the first and second memory mats And a fourth area for storing fourth information for designating a bit line selection line associated with the second defect among the plurality of bit line selection lines. A semiconductor device characterized by the above-mentioned. 11. The semiconductor device according to claim 9, wherein: an output node coupled to said plurality of bit line selection lines;
A Y decoder having an input node supplied with a column address, an output node coupled to the plurality of word lines included in the first and second memory mats, and an X having an input node supplied with a row address; A semiconductor device further comprising a decoder, wherein the access information input to the defect relieving circuit is related to a part of the column address and the row address. 12. The semiconductor device according to claim 9, further comprising: a plurality of first sense amplifiers and first input / output lines provided corresponding to said first memory mat; A semiconductor device comprising a plurality of second sense amplifiers and second input / output lines provided corresponding to a memory mat. 13. The semiconductor device according to claim 9, further comprising a plurality of sense amplifiers and input / output lines shared by said first memory mat and said second memory mat. Semiconductor device. 14. The semiconductor device according to claim 9, wherein said first and second regions of said first storage circuit each include a fuse for storing defect information. Semiconductor device. 15. The semiconductor device according to claim 10, wherein each of the first and second areas of the first storage circuit includes a fuse for storing defect information, and the second storage circuit includes a fuse for storing defect information. The semiconductor device according to claim 1, wherein the third and fourth regions of the circuit each include a fuse for storing defect information. 16. The semiconductor device according to claim 10, wherein said defect relieving circuit further includes a logical sum circuit, wherein an output of said first comparing circuit and an output of said second comparing circuit both pass through said logical sum circuit. A semiconductor device coupled to the spare bit line selection line via the semiconductor device. 17. A first, second, and second memory cells each having a plurality of memory cells provided at intersections of a plurality of word lines and a plurality of bit lines, a first spare bit line, and a second spare bit line.
Third and fourth memory mats, and a plurality of bit lines provided over the first to fourth memory mats and provided corresponding to each of the plurality of bit lines of the first to fourth memory mats A selection line, a first spare bit line selection line provided across the first to fourth memory mats for selecting the first spare bit line of the first to fourth memory mats, A second spare bit line selection line for selecting the second spare bit line of the first to fourth memory mats, and selecting the first and second spare bit line. A defect relief circuit provided for controlling selection of a line, to which access information for specifying one of the first to fourth memory mats and one of the plurality of bit line selection lines is input; The defect relief A path for forming a signal for selecting the first spare bit line selection line when the access information and the information stored in the first storage circuit match by comparing the first storage circuit; A comparison circuit; a second storage circuit; and forming a signal for selecting the first spare bit line selection line when the access information and the information stored in the second storage circuit match and match. A second comparison circuit, a third storage circuit, and a signal for selecting the second spare bit line selection line when the access information is compared with the information stored in the third storage circuit and they match. A third comparison circuit, a fourth storage circuit, and a comparison circuit for comparing the access information with the information stored in the fourth storage circuit to select the second spare bit line selection line when they match. A fourth comparison circuit for forming a signal of A, and wherein each of the first to fourth storage circuits, a first area for storing first information for specifying a memory mat associated from the first to the given defect in the fourth memory mat,
A semiconductor device having a second area for storing second information for designating a bit line selection line related to the predetermined defect among the plurality of bit line selection lines. 18. The semiconductor device according to claim 17, further comprising: an output node coupled to said plurality of bit line selection lines;
A Y decoder having an input node supplied with a column address, an output node coupled to the plurality of word lines included in the first to fourth memory mats, and an X having an input node supplied with a row address; A semiconductor device comprising: a decoder; and the access information input to the defect repair circuit is related to a part of the column address and the row address. 19. The semiconductor device according to claim 17, further comprising: a plurality of first sense amplifiers and first input / output lines provided corresponding to said first memory mat; A plurality of second sense amplifiers and second input / output lines provided correspondingly; a plurality of third sense amplifiers and third input / output lines provided corresponding to the third memory mat; A semiconductor device comprising a plurality of fourth sense amplifiers and fourth input / output lines provided corresponding to a mat. 20. The semiconductor device according to claim 17, further comprising: a plurality of first sense amplifiers and first input / output lines shared by said first memory mat and said second memory mat; A semiconductor device comprising: a plurality of second sense amplifiers and second input / output lines shared by a memory mat and the fourth memory mat. 21. The semiconductor device according to claim 17, wherein the first and second regions in each of the first to fourth storage circuits include a fuse for storing defect information. A semiconductor device characterized by including: 22. The semiconductor device according to claim 17, wherein said first to fourth memory cells are accessed when a memory is accessed.
A semiconductor device, wherein one of the memory mats is selected and one of the plurality of word lines of the selected memory mat is activated. 23. A plurality of memory mats each having a plurality of memory cells provided at predetermined intersections between a plurality of word lines, a plurality of bit lines, and a first spare bit line; A plurality of bit line selection lines provided corresponding to each of the plurality of bit lines of the plurality of memory mats; a plurality of bit line selection lines provided over the plurality of memory mats; A first spare bit line selection line for selecting one spare bit line, and one of the plurality of memory mats and the plurality of bit lines provided for controlling selection of the first spare bit line selection line A defect relief circuit to which access information for designating one of the selection lines is input, wherein the defect relief circuit stores a first storage circuit, the access information, and the first storage circuit. A first comparison circuit that forms a signal for selecting the first spare bit line selection line when the information matches the information stored in the plurality of memory mats. And a first area for storing first information for designating a memory mat associated with a first defect, and a bit line select line associated with the first defect among the plurality of bit line select lines. One of the plurality of memory mats is selected at the time of memory access, and one of the plurality of word lines of the selected memory mat is selected. A semiconductor device characterized by being performed. 24. The semiconductor device according to claim 23, wherein the defect relieving circuit compares the access information with the information stored in the second storage circuit and matches the access information with the information stored in the second storage circuit. A second comparing circuit for forming a signal for selecting the first spare bit line selecting line, wherein the second memory circuit is a memory mat associated with a second defect among the plurality of memory mats. And a fourth area for storing fourth information for designating a bit line selection line associated with the second defect among the plurality of bit line selection lines. A semiconductor device comprising: 25. The semiconductor device according to claim 24, wherein said defect relieving circuit further includes a logical sum circuit, wherein an output of said first comparing circuit and an output of said second comparing circuit both pass through said logical sum circuit. A semiconductor device coupled to the first spare bit line select line via the first spare bit line select line. 26. The semiconductor device according to claim 23, wherein each of the plurality of memory mats includes a second spare bit line and a plurality of memory mats provided at intersections of the plurality of word lines and the second spare bit line. The semiconductor device further includes a second spare bit line selection line provided over the plurality of memory mats and for selecting the second spare bit line of the plurality of memory mats. The defect relieving circuit is configured to select the second spare bit line selection line when the access information and the information stored in the second storage circuit match with each other by comparing the second storage circuit. And a second comparing circuit for forming a signal of the second type. The second storage circuit stores third information for designating a memory mat related to a second defect among the plurality of memory mats. Territory and the front Wherein a has a fourth area for storing the fourth information for specifying a bit line selecting lines associated with the second defect among the plurality of bit line selecting line. 27. The semiconductor device according to claim 23, further comprising: an output node coupled to said plurality of bit line selection lines;
A Y decoder having an input node to which a column address is supplied; an output node coupled to the plurality of word lines included in the plurality of memory mats; and an X decoder having an input node to which a row address is supplied. A semiconductor device, wherein the access information input to the defect relief circuit is related to a part of the column address and the row address. 28. The semiconductor device according to claim 23,
The semiconductor device according to claim 1, wherein the first and second regions of the first storage circuit each include a fuse for storing defect information. 29. The semiconductor device according to claim 24, wherein the first and second regions of the first storage circuit each include a fuse for storing defect information, and the second storage circuit includes a fuse for storing defect information. The semiconductor device according to claim 1, wherein the third and fourth regions of the circuit each include a fuse for storing defect information. 30. The semiconductor device according to claim 9, wherein each of said plurality of memory cells is a dynamic memory cell. 31. The semiconductor device according to claim 9, wherein said semiconductor device is a DRAM to which a row address and a column address are inputted in an address multiplex system at the time of memory access. Semiconductor device.