KR20000055740A - Semiconductor device - Google Patents

Abstract

PURPOSE: A semiconductor device is provided to reduce accessing time by making each of address counters count read/write signals in half periods, to increase counting speeds. CONSTITUTION: A semiconductor device comprises an even address counter(21), an odd address counter(22), a counter enable bit(23), an even memory cell(24), and an odd memory cell(25). The even address counter is composed of an address latch and a decoder. The odd address counter is composed of an address latch and a decoder. The counter enable bit composed of a toggle Flip-Flop outputs control signals to the even/the odd address counters. The even/the odd memory cells are composed of many banks. If a least significant bit(LSB) of an inputted address is '0', addresses except the LSB are latched in the even/the odd address counters, and decoded. If the LSB is '1', the odd address counter latches addresses except the LSB, and the even address counter latches addresses except the LSB by adding '1' to an address.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to semiconductor devices suitable for improving memory access speed.

Hereinafter, a conventional semiconductor device will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a conventional semiconductor device.

As shown in FIG. 1, an address counter 11 outputting a desired address, an address output from the address counter 11, external data Data, and a control signal Control are received. It consists of a memory cell 12 that reads or writes.

The address counter 11 includes an address latch, a counter, and a decoder, and the memory cell 12 includes a plurality of banks having a predetermined size.

In the conventional semiconductor device configured as described above, when the bank of the memory cells 12 is selected by the address output from the address counter 11, the address counter 11 is incremented by one to generate and decode the address to designate a desired address. do.

Therefore, to increase 1 to designate the next address, wait for the time required to increase the address counter 11 and then decode after a stable signal is output.

In other words, it takes a certain time to specify the next address.

In the conventional semiconductor device as described above, there are the following problems.

That is, since it takes a certain time to increment and decode the address counter by one to designate the next address, there is a limit in reducing the access time.

An object of the present invention is to provide a semiconductor device which reduces the access time by reducing the time required to generate an address.

1 is a block diagram showing a conventional semiconductor device

2 is a block diagram illustrating a semiconductor device according to the present invention.

Explanation of symbols for the main parts of the drawings

21: Even Address Counter 22: Odd Address Counter

23: Counter Enable Bit 24: Even Memory Cell

25: odd memory cells

According to an aspect of the present invention, a semiconductor device includes a counter enable bit for outputting a counter enable signal, a first address counter for receiving an even address and receiving a counter enable signal of the counter enable bit; A second address counter that receives the counter enable signal of the counter enable bit and outputs an odd address, and a first memory that receives or writes data from an even address and data of the first address counter and an external control signal to write or read data; And a second memory cell which writes or reads data in response to an odd address and data of the second address counter and an external control signal.

Hereinafter, a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a semiconductor device according to the present invention.

As shown in FIG. 2, an even address counter 21, an odd address counter 22, a counter enable bit (CT_EN) 23, an even memory cell 24, It is composed of odd memory cells 25.

The even address counter 21 is composed of an address latch, an even address counter, and a decoder, and the odd address counter 22 is composed of an address latch, an odd address counter, and a decoder.

The counter enable bit (CT_EN) 23 is composed of a toggle flip-flop (Toggle F / F) to control and output a control signal (Control Signal) to the even address counter 21 and the odd address counter 22. The even memory cells 24 and the odd memory cells 25 are each composed of a plurality of banks.

The semiconductor device of the present invention configured as described above has an even address counter 21 and an odd address counter 22, and if the LSB of the address input is "0", the address excluding the LSB is changed to the even address counter 21 and the odd number. The address counter 22 is latched as it is, decoded, and output.

If the LSB is "1", the odd address counter 22 latches the address except the LSB as it is, and the even address counter 21 latches the address except the LSB.

Each time the read enable bit 23 is "0", the even address counter 21 is incremented by one. When the counter enable bit 23 is "1", the odd address counter 22 is increased. Increase 1).

On the other hand, the LSB of the input address is latched in the counter enable bit 23, and the counter enable bit 23 toggles whenever it is read or written.

At this time, when the counter enable bit 23 is "0", the control signal of the even memory cell 24 is enabled and the control signal of the odd memory cell 25 is disabled.

When the counter enable bit 23 is "1", the control signal of the even memory cell 24 is disabled and the control signal of the odd memory cell 25 is enabled.

As described above, the semiconductor device according to the present invention has the following effects.

That is, since each address counter counts at 1/2 cycles of the read / write signal, the count speed can be increased, thereby reducing the access time, thereby increasing the access speed.

Claims (3)

A counter enable bit for outputting a counter enable signal, A first address counter which receives the counter enable signal of the counter enable bit and outputs an even address; A second address counter configured to receive the counter enable signal of the counter enable bit and output an odd address; A first memory cell configured to receive or write even data and external control signals of the first address counter to write or read data; And a second memory cell configured to receive or write the odd address and data of the second address counter and an external control signal to write or read data. The semiconductor device of claim 1, wherein each of the first and second address counters comprises an address latch, an address counter, and a decoder. The semiconductor device of claim 1, wherein the counter enable bit comprises a toggle flip-flop.