JP2000029784A - High-speed response circuit for device and high-speed response circuit for memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To handle data at a high speed without using a high-speed device. SOLUTION: In this high-speed response circuit, when data D0, D1,..., Dn are successively inputted to a distribution circuit 20 as input signals, they are distributed to an element 0, the element 1,..., an element (n) at a timing indicated by a reference clock by the distribution circuit 20, the respective data respectively outputted from the element 0, the element 1,..., the element (n) are selected and combined at the timing indicated by the reference clock by a combined circuit 30 and thus, the data D0, D1,..., Dn are reproduced and outputted as output signals.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION

The present invention relates to a high-speed response circuit of a device for increasing the input / output response of the device and a high-speed response circuit of a memory for shortening the read / write time of the memory.

[0002]

2. Description of the Related Art A read cycle / write cycle of a memory is determined by its characteristics, and data cannot be read / written in a cycle shorter than the cycle time. For this reason, in order to handle data faster than the cycle time of the memory, it is necessary to change to a faster memory.

[0003]

However, such a high-speed memory is very expensive and poses a serious problem in reducing the cost of the entire hardware. However, even for devices such as gate elements, high-speed devices are generally expensive, so this is not a problem unique to memories alone.

The present invention has been made in view of the above background, and has as its object to provide a high-speed response circuit of a device capable of handling data at high speed without using a high-speed device. Is to do.

[0005]

According to the high-speed response circuit of the device of the present invention, the input / output response of the device is set to the same n (n ≧ n).
2) A high-speed response circuit of a device for speeding up using devices D _1, D _2, ..., D _n and generating a reference clock having a time width much shorter than the input / output response time of the device criteria and generating circuit, a distribution circuit for distributing the device D _1, D ₂ ··· D _n at timing indicated by the reference clock input signal, each output signal from the device D _1, D ₂ ··· D _n And a combining circuit that selects and combines at the timing indicated by the clock and outputs the combined signal as an output signal.

In such a configuration, data D ₁ , D
When ₂ · · D _n are successively input as the input signal, the device D ₁ at the timing indicated by the reference clock by the distribution _circuit,
D ₂ ... D _n and distributed to devices D _1, D _2.
n each output data D _1, D ₂ ·· D _n are combined is selected in the timing indicated by the reference clock by synthesizing circuit from which the data D _1, D ₂ ·· D _n is reproduced, the output signal Is output as

When the device is a memory, the read circuit may have the following configuration. That is, a circuit for shortening the read time of the memory by using the same n (n ≧ 2) memories M _1, M _2, ... M _n at a time interval much shorter than the read time of the memory. enable signal sequentially become active EN _1, EN ₂ ···
A decoding circuit for each output EN _n, in n registers R _1, R ₂ ··· R _n enable signal and the read address signal has a EN _1, EN ₂ ··· EN _n shows the timing an address distribution circuit which respectively output to the memory M _1, M ₂ ··· M _n latches, memory M _1, M ₂ · · ·
Each signal read from _{Mn is} converted to an enable signal EN1 _, E
N ₂ ··· EN _n is better to to the configuration and a combining circuit for outputting a combined output signal selected by the timing shown.

[0008] The writing circuit may be configured as follows. That is, the write time of the memory the same n (n ≧ 2) a fast response circuit of the memory to be fast with the number of memory _{M 1, M 2 ··· M n} , much higher than the write time of the memory crab successively a decoding circuit for each output enable signal EN _1, EN ₂ ··· EN _n which becomes active in a short time interval, n number of registers R _1, R ₂ ··
· R enable signal and the read address signal has a _{n EN 1, EN 2 ··· EN} n memory M ₁ latches at the timing _indicated, M ₂ ··· M _n address distributing circuit for each output And n registers R _1, R ₂ ... R _n
Enable signal and the data has a EN _1, EN ₂
... memory M ₁ latches at the timing indicated by the EN _n,
M ₂ to · · · M _n may be a configuration provided with the data distribution circuit for each output.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a circuit diagram of a high-speed response circuit of a device, FIG. 2 is a timing chart of main signals of the circuit, FIG. 3 is a circuit diagram of a high-speed response circuit of a memory, and FIG. 4 is a timing chart of main signals of the circuit.

In this circuit, the input and output responses of the elements are the same (n
A reference clock generating circuit 10 for generating a reference clock having a time width much shorter than the input / output response time t of the element, which is a circuit for speeding up using +1) elements 0, 1 and. , The input signal is distributed to the devices D _1, D _2, ... D _n at the timing indicated by the reference clock.
And a combining circuit 30 that selects and combines signals output from the devices D _1, D _2, ... D _{n at the} timing indicated by the reference clock, and outputs the selected signals as output signals.

Element 0, Element 1,... Element n are the same, and the types thereof are a photocoupler, a gate element,
A memory, a CPU (not only the internal configuration, but also the installed program) are listed.

The operation of the circuit thus configured will be described with reference to FIG. Data A, D, X, B, E,
When Y, C, F, Z,... Are sequentially input to the distribution circuit 20 as input signals, each data is transmitted to the element 0, element 1,.
Distributed to Thereafter, when the input / output response time t of the element elapses, each data output from the element 0, the element 1,..., The element n is selected and synthesized by the synthesizing circuit 30 at the timing indicated by the reference clock, and synthesized. Data is output as an output signal. As a result, an output signal having the same waveform as the input signal is reproduced.

The specific configuration of such a circuit differs depending on the type of device, but when the device is a memory, the circuit configuration is as shown in FIG.

The high-speed response circuit of this memory is provided as a peripheral circuit of the CPU, and the read time t (read cycle time) of the memory is the same as the (n + 1) memories 0, 1,. It is provided for speeding up using. In the memory 0, the memory 1,..., The memory n, data of the same content is recorded at the same address.

The same circuit, a decoding circuit 40 which respectively outputs the enable signal EN _1, EN ₂ ··· EN _n sequentially become active at short time intervals much from the memory read time t, (n + 1) number of Register 0, Register 1 ...
An enable signal EN _0, EN _1, ... E having a register n and derived from an unillustrated CPU;
Latched at the timing indicated by N _n , memory 0, memory 1
And ... distributing circuit 50 which respectively output to the memory n, memory 0, and selected at a timing memory 1 ... enabling each data read from the memory n signal EN _0, EN ₁ ... EN _n is And a synthesizing circuit 60 for synthesizing and outputting an output signal.

The decoding circuit 40 corresponds to the reference clock generation circuit in the circuit shown in FIG. 1, and includes a (n + 1) -bit counter 41 for counting the counter operation clock CTLK, and a count output of the counter 41 as an enable signal EN _0, It is composed of a decoder 42 for converting the data into EN ₁ ... EN _n . The counter operation clock CTLK is generated by dividing the frequency of the synchronous clock CLTK, and is set to a clock frequency of a period of t / (n + 1) here.

The register 0, register 1,..., Register n are used in the distribution circuit 50 for the read cycle time mainly due to the address holding time and the output data determination time when reading data from the memory. This is because only the address signal needs to be held.
It should be noted that mainly for synchronization between the CPU and the memory,
Register adr is provided at a stage preceding register 0, register 1,...

The synthesizing circuit 60 includes AND gates 0, 1,.
n, an (n + 1) input and one output OR gate 1, and a register 61. AND gates 0, 1,... N
Are connected to enable signals EN _0, EN _1.
Each of the data read from EN _n , memory 0, memory 1... Memory n is introduced. Also, the / OE signal output from the CPU is commonly introduced. A
The outputs of the ND gates 0, 1,... N are introduced to the input terminals of the OR gate 1. The output of the OR gate 1 is latched by the register 61 each time the synchronous clock CLTK becomes active, and is output from the output terminal of the register 61 as an output signal.

The operation of the high-speed response circuit of the memory configured as described above is basically the same as that of the circuit shown in FIG. 1 as shown in FIG. 4, and the read addresses are ADR0 and ADR0.
R1, ADR2,.
The data of DR0, the data of ADR1 of the memory 1, the data of ADR2 of the memory 2,... Are output as output signals. However, as long as the / OE signal output from the CPU does not become active (L level), memory 0, memory 1.
.. Each data read from the memory n does not pass through the AND gates 0, 1... N, and no output signal is output.

In such a high-speed response circuit of a memory, an output response is performed in a cycle of t / (n + 1) despite the use of a memory having a read cycle time of t. Can be handled.

The high-speed response circuit of the memory shown in FIG.
The same circuit is used for writing.
be able to. In this case, n registers R_1,R_Two・ ・
・ R _nAnd enable data EN_1,
EN_Two... EN_nLatch at the timing indicated by
Re M_1,M_Two... M_nData distribution to output to each
It requires additional circuitry. This is what to distribute
Address is data, not an address.
This is the same circuit as the dress distribution circuit 50.

[0022] Note that the decoder circuit to be used in this case, rather than the read time of the memory Naturally, the enable signal EN 1 in consideration of the programming _time, EN ₂ · · · E
N _n will be generated.

Even with such a writing circuit,
T / faster than the write cycle time t for a single memory
Data can be handled in the cycle of (n + 1).

When a circuit is constructed with a fixed data table, it is sufficient to simply increase the response speed of the read cycle. However, there are many cases where dynamic data processing is required. Therefore, it is preferable to adopt a mode in which read / write of the memory is controlled simultaneously. In this case, a read / write enable arbitration circuit or a dual-port RAM
And the like, a high-speed response is realized in the same manner as described above.

[0025]

Effect of the Invention above, in the case of high-speed response circuit device according to claim 1 of the present invention, when the data D _1, D ₂ ·· D _n are successively input as the input signal, the device D ₁ by the distribution _circuit, D ₂ ... D _n , and devices D _1, D ₂
... Each data output D ₁ from the D _n, D ₂ ·· D _n
Are selected and synthesized by a synthesizing circuit, whereby data D ₁ , D _2, ... D _n are reproduced and output as output signals, so that data can be processed at high speed without using a high-speed device. Can handle. Since the overall configuration is very simple, there is a great advantage in reducing the cost of the entire hardware.

According to the high-speed response circuit of the memory according to the second aspect of the present invention, the data can be read in a time shorter than the read cycle time of the memory alone. can get.

According to the high-speed response circuit of the memory according to the third aspect of the present invention, the data can be read in a time shorter than the write cycle time of the memory alone. can get.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining an embodiment of the present invention, and is a circuit diagram of a high-speed response circuit of a device.

FIG. 2 is a timing chart of main signals of the circuit.

FIG. 3 is a circuit diagram of a high-speed response circuit of a memory.

FIG. 4 is a timing chart of main signals of the circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Reference clock generation circuit 20 Distribution circuit 30 Synthesis circuit

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[Procedure amendment]

[Submission date] October 1, 1999 (1999.10.
1)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction contents]

In such a configuration, the input signal data
When chromatography data is input are sequentially distributed to the device D _1, D ₂ ··· D _n at the timing indicated by the reference clock by the distribution circuit, being respectively outputted from the device D _1, D ₂ ··· D _n
The data is selected and synthesized by the synthesis circuit at the timing indicated by the reference clock, whereby the input signal is reproduced and output as an output signal.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction contents]

[0008] The writing circuit may be configured as follows. That is, the write time of the memory to a fast response circuit of the memory to be fast with the same n (n ≧ 2) pieces of memory _{M 1, M 2 ··· M n} , much shorter than the write time of the memory a decoding circuit for each output enable signal EN _1, EN ₂ ··· EN _n sequentially becomes active at time intervals, n number of registers R _1, R ₂ ·
· · R _n enable signal and a write address signal has a EN _1, EN ₂ ··· EN _n memory M ₁ latches at the timing indicated, M ₂ ··· M _n address distribution for each output a circuit, n number of registers R _1, R ₂ ··· R
_n and the data is enabled by the enable signals EN1 _, EN
₂ ... M is latched at the timing indicated by EN _n
1, M ₂ ... M _n .

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0025

[Correction method] Change

[Correction contents]

[0025]

Effect of the Invention above, in the case of high-speed response circuit device according to claim 1 of the present invention, when the data input signal is inputted, the device D ₁ at the timing indicated by the reference clock by the distribution _circuit, D ₂ · · - sequentially distributed to D _n, each data output from the device D _1, D ₂ ··· D _n are combined is selected in the timing indicated by the reference clock by the synthesis circuit, the input signal is reproduced by this, the output Since the signal is output as a signal, data can be handled at high speed without using a high-speed device. Since the overall configuration is very simple, there is a great advantage in reducing the cost of the entire hardware.

Claims (3)

[Claims] An input / output response of a device is set to the same n (n ≧ n)
2) A high-speed response circuit of a device for speeding up using devices D _1, D _2, ..., D _n and generating a reference clock having a time width much shorter than the input / output response time of the device criteria and generating circuit, a distribution circuit for distributing the device D _1, D ₂ ··· D _n at timing indicated by the reference clock input signal, each output signal from the device D _1, D ₂ ··· D _n A high-speed response circuit for a device, comprising: a synthesis circuit for selecting and synthesizing at a timing indicated by a clock and outputting the selected signal as an output signal. 2. The read time of a memory is set to the same n (n ≧ n)
2) a fast response circuit of the memory to be fast with the number of memory _{M 1, M 2 ··· M n} , the enable signal EN 1 sequentially becomes active at short time intervals much than the read time of the _memory, EN ₂ · · · EN and decoding circuit each outputting a _n, n number of registers R _1, R ₂ ··· has a R _n and the read address signal to the enable signal EN
An address distribution circuit which respectively output to _1, EN ₂ ··· EN _n memory M ₁ latches at the timing indicated, M ₂ ··· M _n, read out from the memory M _1, M ₂ ··· M _n fast response circuit of the memory, characterized by comprising a combining circuit for outputting a respective signal as an enable signal EN _1, EN ₂ ··· EN _n is synthesized by selected at a timing output signal. 3. The memory writing time is set to the same n (n ≧ n)
2) A high-speed response circuit of a memory for speeding up the use of the memories M _1, M ₂ ... M _n , wherein enable signals EN _1, which become active sequentially at a time interval much shorter than the write time of the memory _. EN ₂ · · · EN and decoding circuit each outputting a _n, n number of registers R _1, R ₂ ··· has a R _n and the read address signal to the enable signal EN
_1, EN ₂ ··· EN _n and the address distribution circuit respectively output the latched in memory M _1, M ₂ ··· M _n at the timing indicated by the, n number of registers R _1, R ₂ ··· R _n the enable signal EN ₁ a and data has, EN ₂ ··· EN _n
Memory M _1, M ₂ ··· M latches at the timing indicated by the
Fast response circuit of the memory, characterized by comprising a data distribution circuit which respectively output to _n.