KR20000055217A - Method for manufacturing self-aligned buried bit line in semiconductor device - Google Patents

Abstract

PURPOSE: A manufacturing method is to provide a self-aligned buried bit line without a further lithographic process. CONSTITUTION: A manufacturing method comprises the steps of: providing a semiconductor substrate(100); etching the substrate using a mask for forming an active region such that a width of a first isolation region in which a bit line(116) is to be buried, is different from that of a second isolation region in which the bit line is not to be buried; forming a first insulation layer(114) on the former to fill the second region with the first insulation layer; forming a first conductive layer on the former and etching the first conductive layer so as to form a bit line in the first isolation region; and forming a second insulation layer(118) on the former, and flattening the second insulation layer.

Description

Method for manufacturing self-aligned buried bit line in semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of forming a buried bit line without further photographic processes.

A dynamic random access memory (DRAM) device includes a cell array area in which a plurality of memory cells are regularly arranged in the X and Y directions, and a peripheral circuit area for controlling memory cells by being formed around the cell array area. Each memory cell can be selected by selecting both a row signal line called a word line and a column signal line called a bit line. As the DRAM devices are highly integrated, the area of the unit memory cells is inevitably reduced, and thus securing the capacity of the capacitor becomes a very important problem.

In order to secure the capacity of the capacitor, there are various methods such as reducing the thickness of the dielectric layer, using a material having a high dielectric constant as the dielectric film, or increasing the area of the storage electrode. In particular, in order to increase the capacity of the capacitor, from the initial planar cell capacitor structure to the stack (stack) or trench (trench) capacitor structure, and also in the stack capacitor structure, like a cylindrical capacitor or a fin capacitor, storage electrodes Technological changes have been made to increase the effective area of the structure.

In view of the process order, the change from the CUB (Capacitor Under Bitline) structure in which the capacitor is formed before the bit line formation is changed from the Capacitor Over Bitline (COB) structure in which the capacitor is formed after the bit line formation.

Since the COB structure forms the capacitor after the bit line is formed in comparison with the CUB structure, it is possible to form the capacitor irrespective of the margin of the bit line process, thereby having an excellent advantage in increasing the capacity of the capacitor in a limited area. In other words, since the capacitor is formed on the bit line, the COB structure can maximize the size of the storage electrode up to the limit of the lithography process, thereby ensuring a large capacitance.

However, in the COB structure, since the transistor, the bit line, and the interlayer insulating layer are stacked under the storage electrode, the aspect ratio of the buried contact hole for electrically connecting the storage electrode and the source region of the transistor is high. The problem may occur that the contact does not open due to a large size. Accordingly, in order to easily form a buried contact hole and a bit line contact hole for electrically connecting the drain region of the transistor and the bit line, a self-aligned contact hole is formed by using a step of a peripheral structure or a source of the transistor is formed. And a method of reducing the aspect ratio of the contact holes by forming a conductive layer serving as a landing pad on each upper portion of the drain region.

However, since these methods complicate the process, a method of forming a buried bit line below the drain region or the isolation region of the silicon substrate has been proposed.

1 and 2 are cross-sectional views illustrating a method of manufacturing a buried bit line in a semiconductor device by a conventional method.

Referring to FIG. 1, after forming a mask layer (not shown) on the silicon substrate 10, the trench 11 is formed by dry etching the substrate 10 to a predetermined depth using the mask layer. Subsequently, an oxide film is deposited to a thickness sufficient to completely fill the trench 11 on the entire surface of the resultant and then etched by chemical mechanical polishing (CMP). As a result, a shallow trench isolation region 12 filled with a planarized oxide film is formed.

Subsequently, after the photoresist is applied on the resultant, the photoresist is exposed and developed to form a photoresist pattern 13 which opens the region where the bit line is to be buried in the isolation region 12. Using the photoresist pattern 13 as an etching mask, the exposed isolation region 12 is dry etched to a predetermined depth to form the buried region 14 of the bit line.

Referring to FIG. 2, after removing the photoresist pattern 13, a polycrystalline silicon layer is deposited on the resultant and etched back to form a bit line 15. Subsequently, an oxide is deposited on top of the resultant to form the insulating layer 16, and then the insulating layer 16 is etched back to bury the bit line 15.

According to the conventional method described above, an additional photographic process is required to form the buried bit line. In addition, since the bit line of the peripheral circuit region except the cell array region is formed under the isolation region, it is difficult to apply to the actual process.

Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device capable of forming an buried bit line without an additional photographic process.

1 and 2 are cross-sectional views illustrating a method of manufacturing a buried bit line in a semiconductor device by a conventional method.

3 is a plan view of a semiconductor device according to the present invention.

4A to 12B are cross-sectional views illustrating a method of manufacturing the device shown in FIG. 3.

<Description of the code | symbol about the principal part of drawing>

100 silicon substrate 110a, 110b separation region

114: first insulating layer 116: bit line

118: second insulating layer 120: third insulating layer

122: gate 124: sidewall spacer

126 source / drain region 128 first interlayer insulating film

132a, 132b: contact hole 134: third conductive layer

136: second interlayer insulating film 138: buried contact hole

140: storage electrode

In order to achieve the above object, the present invention provides a semiconductor device manufacturing method comprising a cell array region in which a plurality of memory cells are formed, and a peripheral circuit region for driving the cell; Etching the semiconductor substrate using a mask for forming the active region so that the width of the first isolation region where the bit line is to be buried is different from the width of the second isolation region where the bit line is not to be buried; Depositing a first insulating layer on top of the resultant to completely fill the second insulating region with the first insulating layer where the bit line will not be buried; Depositing a first conductive layer on top of the resultant, and etching back the first conductive layer to form a bit line in the first isolation region; And depositing a second insulating layer on top of the resultant and planarizing the second insulating layer.

Preferably, the mask for forming the active region is laid out such that the width of the first isolation region where the bit line is to be buried is greater than the sum of the line widths of the bit line and the width of the second isolation region where the bit line will not be buried.

Preferably, after the planarizing of the second insulating layer, forming a gate and a source / drain region of the second conductive layer on top of the active region; Forming an interlayer insulating layer on the resultant, and etching the interlayer insulating layer and the second insulating layer to form a first contact hole exposing the bit line and a second contact hole exposing the drain region; And depositing a third conductive layer on top of the resultant, and patterning the third conductive layer to connect the first contact hole and the second contact hole. Preferably, the third conductive layer is patterned to be provided as bit lines in the peripheral circuit area.

According to the present invention, the mask for forming the active region is manufactured such that the width of the separation region in the X-axis direction is smaller than the width of the separation region in the Y-axis direction, so that the narrow separation region is completely filled with the insulating layer and the wide width is obtained. Buried the bit line only in the separation region Thus, the buried bitline can be formed in a self-aligned manner without further photographic processing.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view of a semiconductor device according to the present invention.

Referring to FIG. 3, the width of the separation region 110b in the X-axis direction is smaller than the width of the separation region 110a in the Y-axis direction. Accordingly, the isolation region 110b in the X-axis direction is completely filled with the insulating layer, and the bit line 116 made of the first conductive layer is self-aligned and buried only in the isolation region 110a in the Y-axis direction. Preferably, the width of the isolation region 110a in the Y-axis direction should be larger than the sum of the width of the isolation region 110b in the X-axis direction and the line width of the bit line 116 in consideration of the bit line resistance.

In the active region of the silicon substrate where the buried bit line 116 is formed, a transistor including a gate 122 formed of a second conductive layer and a source / drain region 126 is formed. A first interlayer insulating film (not shown) is formed on the substrate including the transistor. A first contact hole 132a exposing the buried bit line 116 and a second contact hole 132b exposing the drain region 126 of the transistor are formed through the first interlayer insulating layer.

The third conductive layer 134 is formed on the first interlayer insulating layer. The third conductive layer 134 is patterned to connect the first contact hole 132a and the second contact hole 132b. That is, the buried bit line 116 and the drain region 126 of the transistor are electrically connected by the third conductive layer 134. In addition, the third conductive layer 134 is patterned to be provided as a bit line in the peripheral circuit region except for the cell array region.

4A to 12B are cross-sectional views illustrating a method of manufacturing the device shown in FIG. 3. Here, each a degree is sectional drawing along the Y-axis direction of FIG. 3, and each b degree is sectional drawing along the X-axis direction of FIG.

4A and 4B illustrate the step of defining the isolation regions 108a and 108b. After the first oxide film 102 is formed thin on the silicon substrate 100 by a thermal oxidation method, the nitride film 104 is formed on the upper portion of the silicon oxide film 100 by low pressure chemical vapor deposition. It is deposited to a thickness of about 1000 to 2000 kPa by the LPCVD method. Next, as shown in FIG. 3, the photolithography process is performed using an active region forming mask in which the width of the separation region 110a in the X-axis direction is 0.3 μm and the width of the separation region 110b in the Y-axis direction is 0.6 μm. By forming the photoresist pattern 106 on the nitride film 104 through, the isolation regions 108a and 108b are defined.

5A and 5B illustrate forming isolation regions 110a and 110b. The nitride film 104 and the first oxide film 102 are sequentially dry-etched using the photoresist pattern 106 as an etching mask. Subsequently, after the photoresist pattern 106 is removed by an ashing and stripping method, the silicon substrate 100 is dry-etched to a predetermined depth, for example, a depth of about 4000 to 5000 mm 3 using the nitride film 104 as an etching mask. 110a, 110b). At this time, the width of the separation region 110a in the X-axis direction is smaller than the width of the separation region 110b in the Y-axis direction.

Subsequently, a thermal oxidation process is performed to recover the lattice damage of the silicon substrate 100 due to the etching process to form the second oxide film 112 on the sidewalls of the isolation regions 110a and 110b to a thickness of about 50 to about 200 Å. .

6A and 6B illustrate forming the first insulating layer 114 and the first conductive layer 116 ′. The first insulation is deposited by depositing an insulating material, such as USG (undoped silicate glass), on top of the resultant to a thickness sufficient to completely fill the narrow separation region 110b by chemical vapor deposition, for example about 1700 kPa. Form layer 114. Subsequently, a polycrystalline silicon layer is deposited on the upper portion of the first insulating layer 114 as a first conductive layer 116 to a thickness of about 3000 to 4000 kPa, for example, by a low pressure chemical vapor deposition method.

7A and 7B illustrate etching the first conductive layer 116 ′ to form a buried bit line 116 having a thickness of about 1500 GPa in the isolation region 110a having a wide width in the Y-axis direction. Illustrated. At this time, all of the first conductive layer 116 ′ on the isolation region 110b in the narrow X-axis direction are etched.

8A and 8B show the step of flattening the result. An insulating material, such as USG, is deposited on the top of the resultant buried bitline 116 to a thickness of about 5000 mm by chemical vapor deposition to form a second insulating layer 118. Subsequently, a chemical physical polishing process may be performed to etch a portion of the nitride film 104 to planarize the resultant product. As a result, all of the second insulating layers 118 on the isolation region 110b in the X-axis direction having a narrow width are etched.

9A and 9B illustrate forming gate 122 and source / drain regions 126. After the nitride film 104 and the first oxide film 102 are removed by a wet etching method, a third insulating layer 120 is formed on the resultant to a thickness of about 50 to 150 kPa by a low pressure chemical vapor deposition method. The third insulating layer 120 serves as a gate insulating layer of the transistor. Subsequently, a second conductive layer, for example, a polycrystalline silicon layer was deposited to a thickness of about 1000 to 3000 kPa by a low pressure chemical vapor deposition method on top of the resultant, and then the second conductive layer was patterned through a photolithography and etching process. The gate 122 is formed.

Subsequently, the oxide is deposited on the top of the resultant to a thickness of about 500 to 1000 mm by chemical vapor deposition and etched back to form sidewall spacers 124 at both edges of the gate 122. The source / drain regions 126 of the transistor are formed by implanting impurities into the surface of the substrate 100 using the sidewall spacers 124 and the gate 122 as ion implantation masks.

10A and 10B illustrate forming a first contact hole 132a and a second contact hole 132b. An insulating material, such as USG, is deposited to a thickness of about 3000 to 8000 kPa by a chemical vapor deposition method on top of the resultant in which the transistor is formed to form a first interlayer insulating film 128.

Next, a photoresist pattern 130 for forming a contact hole is formed on the first interlayer insulating layer 128 through a photolithography process. The first contact hole 132a and the transistor exposing the buried bit line 116 by dry etching the first interlayer insulating layer 128 and the second insulating layer 118 using the photoresist pattern 130 as an etching mask. A second contact hole 132b is formed to expose the drain region 126 of the.

11A and 11B illustrate forming a third conductive layer 134. After removing the photoresist pattern 130 by ashing and stripping, polycrystalline silicon is deposited on top of the first interlayer insulating layer 128 including the first contact hole 132a and the second contact hole 132b. Is deposited to a thickness of about 1000 to 3000 mm 3 to form the third conductive layer 134. Subsequently, the third conductive layer 134 is patterned to connect the first contact hole 132a and the second contact hole 132b to each other through a photolithography and an etching process. As a result, the buried bit line 116 and the drain region 126 of the transistor are electrically connected by the third conductive layer 134. Preferably, the third conductive layer 134 is patterned to be provided as a bit line in the peripheral circuit region except for the cell array region. Therefore, in the step of connecting the buried bit line 116 and the drain region 126 of the transistor in the cell array region, the bit lines of the peripheral circuit region are formed together.

12A and 12B illustrate forming storage electrode 140. An insulating material, such as USG, is deposited on the resultant to a thickness of about 2000 to 8000 kPa by chemical vapor deposition to form a second interlayer insulating film 136.

Subsequently, a photoresist pattern (not shown) for forming a contact hole is formed on the second interlayer insulating layer 136 through a photolithography process. The second interlayer insulating layer 136 and the first interlayer insulating layer 128 are dry etched using the photoresist pattern as an etch mask to form a buried contact hole 138 that exposes the source region 126 of the transistor.

After removing the photoresist pattern by ashing and stripping, a polycrystalline silicon layer was deposited on the upper portion of the second interlayer insulating film 136 including the buried contact hole 138 to a thickness of about 6000 kPa by a low pressure chemical vapor deposition method and photographed. And the storage electrode 140 of the capacitor is patterned by an etching process. The storage electrode 140 is electrically connected to the source region 126 of the transistor through the buried contact hole 138.

Subsequently, although not shown, a capacitor is formed by sequentially stacking a dielectric layer and a plate electrode on the storage electrode 140.

As described above, according to the present invention, the mask for forming the active region is manufactured such that the width of the separation region in the X-axis direction is smaller than the width of the separation region in the Y-axis direction, thereby completely narrowing the narrow separation region to the insulating layer. Fill and bury bitlines only in wide separation areas. Thus, the buried bitline can be formed in a self-aligned manner without further photographic processing.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (4)

A method of manufacturing a semiconductor device having a cell array region in which a plurality of memory cells are formed and a peripheral circuit region for driving the cells, Providing a semiconductor substrate; Etching the semiconductor substrate using a mask for forming an active region so that a width of the first isolation region where the bit line is to be buried and a width of the second isolation region where the bit line is not to be buried are different from each other; Depositing a first insulating layer on top of the resultant to completely fill the second insulating region with the first insulating layer where the bit line will not be buried; Depositing a first conductive layer on top of the resultant, and etching back the first conductive layer to form a bit line in the first isolation region; And Depositing a second insulating layer on top of the resultant and planarizing the second insulating layer. The mask of claim 1, wherein the width of the first isolation region where the bit line is to be buried is greater than the width of the second isolation region where the bit line is not to be buried and the line width of the bit line. A method for manufacturing a semiconductor device, which is laid out to be large. The method of claim 1, further comprising: after the planarization of the second insulating layer, forming a gate and a source / drain region including a second conductive layer on the active region; Forming an interlayer insulating layer on the resultant, etching the interlayer insulating layer and the second insulating layer to form a first contact hole exposing the bit line and a second contact hole exposing the drain region; And patterning the third conductive layer to deposit a third conductive layer on top of the resultant and to connect the first contact hole and the second contact hole. The method of claim 3, wherein in the patterning of the third conductive layer, the third conductive layer is patterned to be provided as a bit line in the peripheral circuit region.