KR20000051692A - Method for manufacturing shallow trench isolation of semiconductor devices - Google Patents

Method for manufacturing shallow trench isolation of semiconductor devices Download PDF

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Publication number
KR20000051692A
KR20000051692A KR1019990002267A KR19990002267A KR20000051692A KR 20000051692 A KR20000051692 A KR 20000051692A KR 1019990002267 A KR1019990002267 A KR 1019990002267A KR 19990002267 A KR19990002267 A KR 19990002267A KR 20000051692 A KR20000051692 A KR 20000051692A
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South Korea
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trench
film
silicon wafer
insulating film
semiconductor device
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KR1019990002267A
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Korean (ko)
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송호영
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김규현
아남반도체 주식회사
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Priority to KR1019990002267A priority Critical patent/KR20000051692A/en
Publication of KR20000051692A publication Critical patent/KR20000051692A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE: A method for fabricating a shallow trench is provided for a non-defective semiconductor device isolation and for preventing the loss of an oxide film when planarizing a trench filling insulation material by a CMP(chemical mechanical polishing) process. CONSTITUTION: A method for fabricating a shallow trench is to remove an insulation film taken out at an interface between an active region and a field region, when planarizing a trench filling insulation material by a chemical mechanical polishing process. According to the method, after forming a pad oxide(12) and a nitride film(13) on a silicon wafer(11), a trench to define a semiconductor device isolation region is formed by patterning the pad oxide and the nitride film and by etching the revealed silicon wafer. In addition, an insulation film is deposited thickly on the whole surface of the silicon wafer where the trench is formed. And, after forming an insulation film pattern in order for the insulation film to be remained only on the trench region and planarizing by a CMP process, the density of the insulation film pattern is increased or the lattice structure is stabilized through a densification process. Finally, a shallow trench for semiconductor device isolation is completed by removing the nitride film by cleaning the silicon wafer.

Description

반도체 소자 분리를 위한 얕은 트렌치 제조 방법{METHOD FOR MANUFACTURING SHALLOW TRENCH ISOLATION OF SEMICONDUCTOR DEVICES}TECHNICAL FIELD METHOD FOR MANUFACTURING SHALLOW TRENCH ISOLATION OF SEMICONDUCTOR DEVICES

본 발명은 반도체 소자 분리를 위한 얕은 트렌치를 제조하는 방법에 관한 것으로, 더욱 상세하게는 반도체 집적회로 등의 반도체 소자를 제조하는 공정 중 실리콘웨이퍼에 각 반도체 소자를 전기적으로 격리하여 분리하기 위한 얕은 트렌치를 제조하는 방법에 관한 것이다.The present invention relates to a method of manufacturing a shallow trench for semiconductor device isolation, and more particularly, to a shallow trench for electrically insulating and separating each semiconductor device from a silicon wafer during a process of manufacturing a semiconductor device such as a semiconductor integrated circuit. It relates to a method of manufacturing.

일반적으로 반도체 소자를 분리하는 방법으로는 선택적 산화법으로 질화막을 이용하는 LOCOS(local oxidation of silicon) 소자 분리 방법이 이용되어 왔다.In general, a method of separating a semiconductor device has been used a local oxidation of silicon (LOCOS) device separation method using a nitride film as a selective oxidation method.

LOCOS 소자 분리 방법은 질화막을 마스크로 해서 실리콘웨이퍼 자체를 열 산화시키기 때문에 공정이 간소해서 산화막의 소자 응력 문제가 적고, 생성되는 산화막질이 좋다는 큰 이점이 있다.Since the LOCOS device isolation method thermally oxidizes the silicon wafer itself using a nitride film as a mask, the process is simple and there is a great advantage that the device stress problem of the oxide film is small, and the oxide film produced is good.

그러나, LOCOS 소자 분리 방법을 이용하면 소자 분리 영역이 차지하는 면적이 크기 때문에 미세화에 한계가 있을 뿐만 아니라 버즈 비크(bird's beak)가 발생하게 된다.However, when the LOCOS device isolation method is used, the area occupied by the device isolation region is not only limited in miniaturization but also causes a bird's beak.

이러한 것을 극복하기 위해 LOCOS 소자 분리 방법을 대체하는 기술로서 트렌치 소자 분리(STI ; shallow trench isolation)가 있다. 트렌치 소자 분리에서는 실리콘웨이퍼에 트렌치를 만들어 절연물을 집어넣기 때문에 소자 분리 영역이 차지하는 면적이 작아서 미세화에 유리하다.In order to overcome this, a trench trench isolation (STI) technique is an alternative to the LOCOS isolation scheme. In trench device isolation, a trench is formed in a silicon wafer to insulate the insulating material, so the area occupied by the device isolation region is small, which is advantageous for miniaturization.

그러면, 이러한 반도체 소자 분리를 위한 얕은 트렌치를 제조하는 종래의 방법을 첨부된 도 1a 내지 도 1d를 참조하여 설명한다.Then, a conventional method of manufacturing such a shallow trench for semiconductor device isolation will be described with reference to FIGS. 1A-1D.

먼저, 도 1a에 도시한 바와 같이, 실리콘웨이퍼(1)에 패드 산화막(2)과 질화막(3)을 차례로 형성한 후, 포토리소그래피(photolithography) 공정에 의해 패드 산화막(3)과 질화막(3)을 패터닝하고 드러난 실리콘웨이퍼(1)를 식각하여 반도체 소자 분리 영역을 정의하기 위한 트렌치를 형성한다. 그리고, 트렌치를 절연물로 매입하기 위하여 열 산화 공정을 실시하여 트렌치의 실리콘웨이퍼(1) 표면에 열 산화막(4)을 형성하고, 상압 화학 기상 증착(APCVD)을 이용하여 절연막(5)을 두껍게 적층한다. 이후, 실리콘웨이퍼(1)에 증착된 절연막(5)은 그 자체로 초집적 소자에 적합한 밀도를 갖고 있지 못하거나 격자 구조가 안정화되어 있지 않으므로, 해당 소자에서 원하는 막의 밀도를 가지도록 하기 위하여 고온 공정을 이용한 치밀화 공정을 실시한다.First, as shown in FIG. 1A, the pad oxide film 2 and the nitride film 3 are sequentially formed on the silicon wafer 1, and then the pad oxide film 3 and the nitride film 3 are formed by a photolithography process. The semiconductor wafer 1 is patterned and the exposed silicon wafer 1 is etched to form trenches for defining semiconductor device isolation regions. In order to embed the trench as an insulator, a thermal oxidation process is performed to form a thermal oxide film 4 on the surface of the silicon wafer 1 of the trench, and the insulating film 5 is thickly laminated using atmospheric chemical vapor deposition (APCVD). do. After that, since the insulating film 5 deposited on the silicon wafer 1 does not have a density suitable for a super integrated device itself or the lattice structure is not stabilized, a high temperature process is performed to have a desired film density in the device. The densification process is performed.

그 다음 도 1b에 도시한 바와 같이, 절연막(5) 상부에 감광막을 도포하고, 사진 현상하여 트렌치 영역만을 가리는 감광막 패턴(6)을 형성한다. 그 다음 감광막 패턴(6)을 마스크로 질화막(3) 상부의 드러난 절연막(5)을 식각하여 제거함으로써, 트렌치 영역에만 절연막(5)이 남도록 형성한다.Then, as shown in Fig. 1B, a photoresist film is applied on the insulating film 5 and photographed to form a photoresist pattern 6 covering only the trench region. Next, the exposed insulating film 5 on the nitride film 3 is etched and removed using the photosensitive film pattern 6 as a mask so that the insulating film 5 remains only in the trench region.

그 다음 도 1c에 도시한 바와 같이, 화학 기계적 연마(CMP ; chemical mechanical polishing) 공정을 통하여 질화막(3)의 표면과 절연막(5)의 표면이 동일한 높이를 가지도록 절연막(5)을 연마하여 평탄화한다.Then, as illustrated in FIG. 1C, the insulating film 5 is polished and planarized so that the surface of the nitride film 3 and the surface of the insulating film 5 have the same height through a chemical mechanical polishing (CMP) process. do.

이어, 도 1d에 도시한 바와 같이, 실리콘웨이퍼(1) 세정 공정을 통해 반도체 소자가 형성될 액티브 영역에 남아 있는 질화막(3)을 제거하여 반도체 소자 분리를 위한 얕은 트렌치를 완성한다.Subsequently, as shown in FIG. 1D, the nitride film 3 remaining in the active region where the semiconductor device is to be formed is removed through the silicon wafer 1 cleaning process, thereby completing a shallow trench for semiconductor device isolation.

그러나, 이와 같은 종래의 반도체 소자 분리를 위한 얕은 트렌치 제조 방법에서는 화학 기계적 연마 공정에서 치밀화 공정에서 경화된 절연막(5)을 연마하기 때문에 절연막(5)의 모서리 부분이 떨어져 나가는 문제점이 발생하며, 이로 인하여 액티브 및 필드 영역에 미세한 결함이 발생한다.However, in the conventional method of manufacturing a shallow trench for semiconductor element isolation, a problem arises in that the edge portion of the insulating film 5 falls off because the insulating insulating film 5 is polished in the densification process in the chemical mechanical polishing process. This results in fine defects in the active and field regions.

본 발명은 이와 같은 문제점을 해결하기 위하여 안출한 것으로, 그 목적은 화학 기계적 연마 공정에 의해 트렌치 매입 절연물을 평탄화할 때 산화막이 유실되는 것을 방지하여, 결함이 없는 반도체 소자 분리를 위한 얕은 트렌치를 제조하는 방법을 제공하는 데 있다.The present invention has been made to solve the above problems, and its object is to prevent the loss of oxide film when planarizing the trench embedding insulator by chemical mechanical polishing process, to manufacture a shallow trench for separation of semiconductor devices without defects To provide a way.

도 1a 내지 도 1d는 반도체 소자 분리를 위한 얕은 트렌치를 제조하는 종래의 방법을 도시한 공정도이고,1A-1D are process diagrams illustrating a conventional method for making shallow trenches for semiconductor device isolation,

도 2a 내지 도 2e는 본 발명에 따라 반도체 소자 분리를 위한 얕은 트렌치를 제조하는 방법을 도시한 공정도이다.2A-2E are process diagrams illustrating a method of manufacturing a shallow trench for semiconductor device isolation in accordance with the present invention.

상기와 같은 목적을 달성하기 위하여, 본 발명은 트렌치 매입을 위하여 절연막을 증착하고 패터닝하고 화학 기계적 연마 공정을 진행하여 평탄화한 다음, 치밀화 공정을 실시하는 것을 특징으로 한다.In order to achieve the above object, the present invention is characterized in that the insulating film is deposited, patterned, and chemically polished to planarize, and then densified to fill the trench.

이러한 본 발명에 따른 제조 방법에서는 경화되지 않은 상태에서 화학 기계적 연마 공정이 진행되므로 유실되는 절연막을 최소화할 수 있다.In the manufacturing method according to the present invention, the chemical mechanical polishing process proceeds in an uncured state, thereby minimizing an insulating film that is lost.

이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

도 2a 내지 도 2e는 본 발명의 일 실시예에 따라 반도체 소자 분리를 위한 얕은 트렌치를 제조하는 방법을 도시한 공정도이다.2A-2E are process diagrams illustrating a method of manufacturing a shallow trench for semiconductor device isolation in accordance with one embodiment of the present invention.

먼저, 도 2a에 도시한 바와 같이, 실리콘웨이퍼(11)에 패드 산화막(12)과 질화막(13)을 형성한 후, 포토리소그래피 공정에 의해 패드 산화막(12)과 질화막(13)을 패터닝하고 드러난 실리콘웨이퍼(11)를 식각하여 반도체 소자 분리 영역을 정의하기 위한 트렌치를 형성한다. 이어, 열 산화 공정을 통하여 노출된 트렌치의 실리콘웨이퍼(11) 표면에 열 산화(14)를 형성한다.First, as shown in FIG. 2A, the pad oxide film 12 and the nitride film 13 are formed on the silicon wafer 11, and then the pad oxide film 12 and the nitride film 13 are patterned and exposed by a photolithography process. The silicon wafer 11 is etched to form trenches for defining semiconductor device isolation regions. Subsequently, thermal oxidation 14 is formed on the surface of the silicon wafer 11 of the trench exposed through the thermal oxidation process.

이어, 도 2b에서 보는 봐와 같이, 트렌치를 매입하기 위하여 절연막, 바람직하게는 NSG(non-doped silicate glass)막(15)을 상압 화학 기상 증착 방법을 통하여 두껍게 증착한다.Subsequently, as shown in FIG. 2B, an insulating film, preferably a non-doped silicate glass (NSG) film 15, is thickly deposited through an atmospheric pressure chemical vapor deposition method to fill the trench.

그 다음 도 2c에 도시한 바와 같이, NSG막(15) 상부에 감광막을 도포하고, 사진 현상하여 트렌치 영역만을 덮는 감광막 패턴(16)을 형성한다. 이어, 감광막 패턴(16)을 마스크로 질화막(13) 상부에 감광막 패턴(16)으로 가리지 않는 NSG막(15)을 식각하여 제거함으로써, 트렌치 영역에만 NSG막(15)이 남도록 형성한다.Then, as shown in FIG. 2C, a photoresist film is applied on the NSG film 15 and photographed to form a photoresist pattern 16 covering only the trench region. Subsequently, the NSG film 15 which is not covered by the photoresist pattern 16 is removed by etching the photoresist pattern 16 on the nitride film 13, so that the NSG film 15 remains only in the trench region.

이어, 도 2d에서 보는 바와 같이, 감광막 패턴(16)을 제거한 후, 화학 기계적 연마 공정을 실시하여 NSG막(15)을 평탄화시킨다. 이어, 실리콘웨이퍼(11)에 증착된 NSG막(15)은 그 자체로는 초집적 소자에 적합한 성질을 가지지 못하므로 밀도를 증가시키고, 격자 구조를 안정화시켜, 해당 소자에서 원하는 막의 성질을 갖도록 하기 위하여 고온 공정을 이용한 치밀화 공정을 실시한다.Subsequently, as shown in FIG. 2D, after the photosensitive film pattern 16 is removed, a chemical mechanical polishing process is performed to planarize the NSG film 15. Subsequently, since the NSG film 15 deposited on the silicon wafer 11 does not have a property suitable for a super-integrated device, the NSG film 15 increases the density and stabilizes the lattice structure so as to have the desired film property in the device. In order to achieve the densification process using a high temperature process.

이러한 본 발명의 제조 방법에서는 종래의 기술과 다르게 치밀화 공정을 실시하지 않은 상태에서 화학 기계적 연마 공정을 실시하므로 NSG막(15)이 유실되지 않는다.In the manufacturing method of the present invention, unlike the conventional technology, the NSG film 15 is not lost because the chemical mechanical polishing process is performed without performing the densification process.

만약, 산화막의 일부가 유실되어 모서리 부분이 유실된 NSG막(15)이 발생하더라도 본 발명의 제조 방법에서는 이후에 고온의 치밀화 공정을 실시하기 때문에 NSG막(15)이 리플로우되어 유실된 부분을 채울 수 있다.If a portion of the oxide film is lost and the NSG film 15 having the corner portion is lost, the manufacturing method of the present invention performs a high-temperature densification process later, so that the NSG film 15 is reflowed and lost. I can fill it.

그 다음 도 2e에 도시한 바와 같이, 실리콘웨이퍼(11) 세정 공정을 통해 반도체 소자가 형성될 액티브 영역에 남아 있는 질화막(13)을 제거하여 반도체 소자 분리를 위한 얕은 트렌치를 완성한다.Next, as shown in FIG. 2E, the nitride film 13 remaining in the active region in which the semiconductor device is to be formed is removed through the silicon wafer 11 cleaning process to complete the shallow trench for semiconductor device isolation.

이와 같이 본 발명은 화학 기계적 연마 공정을 이용한 트렌치 매입 절연막의 평탄화를 이루면서 야기되는 절연막의 모서리 부분이 뜯겨져 나가는 결함을 효과적으로 제거할 수 있을 뿐만 아니라 이로 인하여 반도체 소자의 제조 수율을 향상시킬 수 있다. 또한, 화학 기계적 연막 공정을 실시함으로써 절연막의 일부가 뜯겨져 나가더라도 이후에 실시되는 고온의 치밀화 공정을 통하여 절연막을 리플로우시킴으로써 뜯겨진 절연막을 형성할 수 있다.As described above, the present invention can not only effectively eliminate defects caused by tearing edge portions of the insulating film caused by planarization of the trench-filled insulating film using a chemical mechanical polishing process, but also improve the manufacturing yield of the semiconductor device. In addition, even if a part of the insulating film is torn off by performing a chemical mechanical smoke screening process, the broken insulating film can be formed by reflowing the insulating film through a high-temperature densification step which will be performed later.

Claims (1)

실리콘웨이퍼에 패드 산화막과 질화막을 형성한 후, 패드 산화막과 질화막을 패터닝하고 드러난 실리콘웨이퍼를 식각하여 반도체 소자 분리 영역을 정의하기 위한 트렌치를 형성하는 단계와;Forming a pad oxide film and a nitride film on the silicon wafer, patterning the pad oxide film and the nitride film and etching the exposed silicon wafer to form a trench for defining a semiconductor device isolation region; 상기 트렌치가 형성된 실리콘웨이퍼 전면에 절연막을 두껍게 증착하는 단계와;Depositing a thick insulating film on the entire surface of the silicon wafer on which the trench is formed; 상기 증착된 절연막을 패터닝하여 상기 절연막이 상기 트렌치 영역에만 남도록 절연막 패턴을 형성하는 단계와;Patterning the deposited insulating film to form an insulating film pattern such that the insulating film remains only in the trench region; 상기 절연막 패턴을 화학 기계적 연마 공정을 통하여 평탄화하는 단계;Planarizing the insulating film pattern through a chemical mechanical polishing process; 상기 평탄화 공정 단계이후, 고온의 치밀화 공정을 통하여 상기 절연막 패턴의 밀도를 증가시키는 동시에 격자 구조를 안정화시키는 단계;After the planarization process step, increasing the density of the insulating film pattern through a high temperature densification process and stabilizing a lattice structure; 상기 실리콘웨이퍼를 세정하여 상기 질화막을 제거하는 단계를 포함하는 반도체 소자 분리를 위한 얕은 트렌치 제조 방법.And removing the nitride film by cleaning the silicon wafer.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111987006A (en) * 2020-10-16 2020-11-24 晶芯成(北京)科技有限公司 Semiconductor structure and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111987006A (en) * 2020-10-16 2020-11-24 晶芯成(北京)科技有限公司 Semiconductor structure and manufacturing method thereof
CN111987006B (en) * 2020-10-16 2021-08-10 晶芯成(北京)科技有限公司 Semiconductor structure and manufacturing method thereof

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