KR20000051480A - Driving circuit of Plasma Display Panel - Google Patents

Abstract

PURPOSE: A PDP(plasma display panel) driving circuit is provided to eliminate an abnormal scrolling of screen by maintaining a vertical synchronization signal at regularity regardless of reproduction speed of video image. CONSTITUTION: A PDP driving circuit comprises a signal processing unit(400) for receiving a normal video signal which has a regular cycle and processing an image, an abnormal signal detecting unit(100) for detecting an abnormal vertical synchronization signal with an irregular cycle which is inputted or not, a memory(300) for storing video data inputted during one cycle of vertical synchronization signal, and a normal signal generating unit(200) for receiving the abnormal video signal detected by the abnormal signal detecting unit(100) and controlling the cycle of the vertical synchronization signal of the abnormal video signal to be synchronized with the cycle of the vertical synchronization signal of the normal video signal.

Description

Driving circuit of plasma display panel {Driving circuit of Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel (hereinafter referred to as a plasma display panel), and more particularly, to a driving circuit for displaying an image on a PD screen and a method of controlling a signal of the driving circuit.

PD and LCD are spotlighted as next generation display devices with the highest practicality among flat panel displays. In particular, PDP has higher luminance and wider viewing angle than LCD, and thus has wide applicability as a thin, large display such as an outdoor advertising tower, a wall-mounted TV, or a theater display. Unlike the CRT CRT, the PD displays the screen by the discharge of each discharge cell.

1 illustrates a cross-sectional structure of a general PD, in which a Y electrode and a Z electrode are formed on the same surface of the front glass substrate 1, a dielectric layer is formed on the Y electrode and the Z electrode by a printing method, and the dielectric layer 2 Cross-talk with the superstructure on which the protective layer is formed by vapor deposition, and the X electrode 12 on the rear glass substrate 11 of the superstructure, and adjacent cells between the X electrodes 12. The barrier rib 6 is formed to prevent the phenomenon, and the lower structure is formed by forming the phosphors 8, 9, and 10 around the barrier rib 6 and the X electrode 12 to form a space between the upper structure and the lower structure. The inert gas is enclosed in the structure so as to have a discharge region 5.

In such a structure, first, when a driving voltage is applied between the X electrode and the Y electrode, a counter discharge occurs between the X electrode and the Y electrode, and wall charges are generated on the surface of the protective layer of the upper structure. When the discharge voltages having opposite polarities are continuously applied to the Y electrode and the Z electrode and the driving voltage applied to the X electrode is interrupted, a predetermined potential difference between the Y electrode and the Z electrode is maintained by the wall charge, thereby maintaining the dielectric layer ( 2) and the surface discharge occurs in the discharge region on the surface of the protective layer 3. As a result, ultraviolet rays 7 are generated from the inert gas in the discharge region. The ultraviolet rays 7 excite the phosphors 8, 9, and 10, and color display is performed by the emitted phosphors 8, 9, and 10.

That is, while the electrons inside the discharge cell accelerate to the cathode (-) by the applied driving voltage, helium (He) is filled with the inert mixed gas filled with the pressure of about 400 to 500 torr in the discharge cell. As the main component, it collides with a Penning mixed gas to which xenon (Xe), neon (Ne) gas, etc. are added, and the inert gas is excited to generate ultraviolet rays having a wavelength of 147 nm. The ultraviolet light 7 collides with the phosphors 8, 9, and 10 surrounding the lower electrode 12 and the partition wall 6 to emit light in the visible light region.

The PD discharges the cells constituting the pixel by controlling the application of voltages to the X electrode, the Y electrode, and the Z electrode, and the amount of light emitted by the discharge changes the discharge time of the cell. Adjust In other words, the gray scale required for image display is realized by varying the length of time each cell is discharged within the time required to display the entire image (1/30 second in the case of NTSC TV signal). . At this time, the brightness of the screen is determined by the brightness when each cell is discharged to the maximum. In addition, in order to maximize the luminance of the PD screen, it is necessary to keep the discharge time of the cell as long as possible within the time necessary for constructing one screen.

FIG. 2 is a block diagram showing a schematic structure of a PDP including a driving circuit unit, and shows a panel, an X electrode driver, a Y electrode driver, and a Z electrode driver. The X electrode formed in each cell of the PD shown in FIG. 1 is connected to the X electrode driver to receive an address voltage, and the Y electrode is connected to the Y electrode driver to receive a scan voltage. The electrode is connected to the Z electrode driver to receive a sustain voltage.

The controller of the PD drive circuit unit configured as shown in FIG. 2 receives various control signals such as clock signal, RGB data, vertical synchronization signal, and horizontal synchronization signal from the outside, generates scan data, and applies them to the Y electrode driver. The address data is generated and applied to the X electrode driver. Accordingly, the X electrode, the Y electrode, and the Z electrode are driven in accordance with the signals applied to the respective drivers to display an image on the PD. As described above, there are various methods of displaying the screen by discharging each cell of the PD, and generally used methods include a sub-field method and a line erase scanning method.

The subfield method is a method of implementing one screen by setting a screen displayed by discharge of a cell to one sub-screen, and controlling the Y electrode driver and the Z electrode driver to overlap several sub-screens. In such a subfield method, a plurality of subpictures are sequentially gathered to form a single image. In this case, the number of subpictures is equal to the number of gradation bits of the image. That is, if the gray level of the image implemented on the screen is 8 bits, the number of subscreens implemented by the subfield method is 8 sheets. FIG. 3A illustrates a waveform applied to each electrode of the PDP, and FIG. 3B illustrates a subfield type PDP driving method showing a scanning sequence of each PD cell according to the waveform of FIG. 3A.

First, the subfield method applies a voltage of a digital video signal of one bit to all cells of a PD to generate a first sub-picture of all cells having the same luminance. Then, the voltage of the next bit of the digital video signal is applied to generate another second sub-screen in which all cells have the same brightness. At this time, the luminance of the discharge cells constituting the first sub-screen is the same and the luminance of all the discharge cells constituting the second sub-screen is the same, and the luminance of the first sub-screen and the second sub-screen are different.

Each sub-picture generated by one bit of video signal has the highest sub-picture with the highest luminance bit, the lowest sub-picture with the lowest luminance bit, and between the highest sub-picture and the lowest sub-picture. It consists of several sub-pictures by the middle bit. For example, an image having an 8-bit gradation may include a first sub-picture based on the most significant bit, an eighth sub-picture based on the least significant bit, and a second sub-picture that has been differentially divided by six intermediate bits. A total of eight subscreens, including the 4th, 5th, 6th subscreens, are displayed. The subfield method is to superimpose these eight sub-screens and to realize one complete screen by the afterimage effect of the human eye.

However, such a general PD and its driving circuit have the following problems.

Since the CRT CRT is determined by the intensity of each electron gun, the data signal applied to the CRT CRT is an analog signal. In addition to the CRT CRT, an analog display device receiving an analog data signal and displaying an image displays the image in synchronization with a vertical synchronous signal. On the other hand, the grayscale of the PD is determined by the number of discharges of the discharge cells driven in accordance with an externally applied data signal. Thus, the data signal applied to the PD is a digital signal. In particular, since a digital display device such as a PD is divided by a vertical synchronization signal by a predetermined reference value, the screen is configured. As shown in FIG. 4, when the vertical synchronization signal is larger than the predetermined reference value, the screen is abnormally scrolled. Phenomenon occurs. The reason is that despite the change of the vertical synchronous signal applied to the PD, the PD circuit driving circuit is driven according to the normal vertical synchronous signal.

For example, a user may connect video player, such as a video tape recorder (Video Tape Recorder) or video cassette recorder (Video Cassette Recorder), to PDPD. When fast forwarding (FF) or rewinding is performed while the tape or cassette is played, the playback speed of the tape is increased. At this time, the frequency of the vertical synchronization signal generated by a video media playback apparatus such as VRT or VRL increases, so that the screen appearing on PDPD is abnormally scrolled so that the VRD user can hardly watch the image displayed on the screen.

Disclosure of Invention The present invention has been made to solve such a problem, and an object thereof is to provide a PD drive circuit capable of realizing a normal screen regardless of a change in a signal type input to the PD drive circuit.

1 is a cross-sectional view schematically showing the structure of a conventional surface discharge type three-electrode plasma display panel

2 is a block diagram schematically illustrating a structure of a plasma display panel including a driving block.

3A is a diagram illustrating waveforms applied to respective electrodes of a PDP.

FIG. 3B is a diagram illustrating a subfield type PDP driving method showing a scanning order of PD cells according to the waveform of FIG. 3A; FIG.

4 is a diagram illustrating a vertical synchronization signal and a horizontal synchronization signal included in a normal video signal, and a vertical synchronization signal and a horizontal synchronization signal included in an irregular video signal.

5 is a block diagram showing an essential part of a driving circuit of the plasma display panel of the present invention;

Explanation of symbols for main parts of the drawings

100: irregular signal detection unit 200: regular signal generation unit

300: memory 400: signal processor

The present invention is characterized by the addition of a non-normal circuit for performing a separate data processing algorithm so that the drive circuit of the PD P for the change of the vertical synchronization signal.

5 is a signal processing unit 400 for receiving a normal video signal to implement an image, a non-normal signal detection unit 100 for detecting whether an irregular video signal is input, and a vertical synchronization signal for one period. And a normal signal generator 200 for adjusting the vertical synchronization signal of the non-normal video signal so that the non-normal video signal is synchronized with the vertical synchronization signal of the normal video signal.

The signal processor 400 receives a regular video signal having a constant vertical synchronization signal and implements an image. The signal processor 400 is a video signal processing circuit of a TV employing PD. The normal video signal is a playback signal input from a video media playback apparatus such as VTIAL or VCD, and is a signal implemented as an image on PDTV. The period of the vertical synchronization signal included in the normal video signal is approximately 60 hertz.

The irregular signal detection unit 100 detects whether an irregular video signal is inputted in which the period of the vertical synchronization signal varies. The irregular video signal is a signal input from an image medium reproducing apparatus, and is a signal that is implemented as a screen that is faster or slower than the normal speed. One example of such an irregular video signal is a signal that implements a double-speed screen of video or a signal that implements a slow video screen.

The memory 300 stores image data of a normal image signal input during one period of the vertical synchronization signal. The memory 300 is a video memory and stores image data mapped to each pixel.

The normal signal generator 200 receives the irregular video signal detected by the irregular signal detection unit 100 and adjusts the vertical synchronization signal included in the irregular video signal to be synchronized with the period of the vertical synchronization signal included in the normal video signal. .

Hereinafter, the operation principle of the present invention will be described with reference to FIGS. 4 and 5.

The signal input through the external input terminal is input to the irregular signal detection unit 100, the signal processing unit 400, and the memory 300. The irregular signal detection unit 100 detects an irregular video signal including an abnormal vertical synchronization signal. The normal video signal including the normal vertical synchronization signal is implemented as an image on the PD screen by the signal processor 400.

When the non-normal video signal is detected by the non-normal signal detection unit 100, the non-normal video signal is input to the normal signal generator 200, and the image data input during one period of the vertical synchronization signal included in the non-normal video signal is stored in the memory. It is stored in the unit 300.

The irregular video signal is adjusted by the regular signal generator 200 so that the abnormal vertical sync signal is synchronized with the period of the normal vertical sync signal. In addition, the image data stored in the memory unit 300 is applied to the signal processing unit 400 in synchronization with the vertical synchronization signal of the irregular video signal adjusted by the regular signal generator 200.

Accordingly, since the image data is processed so that the irregular video signal including the abnormal vertical sync signal is synchronized with the normal vertical sync signal, the video signal of the video medium reproducing apparatus is implemented as a normal video.

The present invention is output as a normal screen regardless of the shape of the video signal compared to the conventional PD drive circuit, there is an effect that the abnormal scroll phenomenon of the image does not occur. That is, according to the present invention, since the vertical synchronization signal is kept constant regardless of whether the video image is played at a normal speed or at an abnormal speed, an abnormal scroll phenomenon does not occur.

Claims (6)

A signal processor configured to receive a normal video signal having a constant vertical synchronization signal and to implement an image; A non-normal signal detection unit for detecting whether or not the non-normal video signal whose period of the vertical synchronization signal is varied is inputted; A memory for storing image data input during one period of the vertical synchronization signal; And a regular signal generator configured to receive the irregular video signal detected by the irregular signal detector and to adjust a vertical synchronization signal of the irregular video signal to be synchronized with a period of the vertical synchronization signal of the normal video signal. in. The driving circuit of claim 1, wherein the normal image signal is a reproduction signal of an image output from an image medium reproducing apparatus. The driving circuit of claim 1, wherein the atypical video signal is a fast forward signal during playback of an image output from an image carrier. The driving circuit of claim 1, wherein the irregular video signal is a rewind signal during playback of an image output from an image medium reproducing apparatus. 5. The driving circuit of a plasma display panel according to any one of claims 2, 3 and 4, wherein the video medium reproducing apparatus is any one selected from a video tape recorder and a video cassette recorder. The driving circuit of claim 1, wherein a period of the vertical synchronization signal of the normal video signal is about 60 hertz.