KR20000050272A - Liquid crystal display device - Google Patents

Abstract

PURPOSE: A step of manufacturing TFT panel is provided to solve a problems of changing in quality and illuminating a gate pole in a process of formatting a TFT panel used a bipolar (+:al ,-:cr) by using the first and second wring covering the exposure area of insulating filems. CONSTITUTION: An area of a,b,c are oxidized by permeating anodizing liquid into PDA and charge DC voltage, and then a-Si is remained at a TFT part , a wiring crossing part with patterning a-Si, and SIN on the gate is removed by patterning a-Si and as a process shown in FIG.9(e), using a step that a transparent pole is patterned and remained on the gate pole and the transparent pole covers the part of an uncovered area on the gate pole, and a connection part prevents the TFT panel from being changed in a quality.

Description

LCD Display

An example of a liquid crystal display TFT substrate using Al ₂ O ₃ obtained by using an amorphous silicon TFT (hereinafter referred to as a-Si) TFT and making the gate electrode Al (aluminum) and anodizing it is shown. Mark on 2. 2 (a), 2 (b) and 2 (c) show an equivalent circuit diagram, a plan view and a sectional view of a TFT substrate, respectively. (G ₁ ), (G ₂ ) is the gate terminal, (G ₁ '), (G ₂ ') is the gate wiring, (D ₁ ), (D ₂ ) is the drain terminal, (T ₁₁ ), (T ₁₂ ) (T ₂₁ ) and (T ₂₂ ) denote TFTs, (LC) denote liquid crystals, and (Vcom) denote common terminals provided on the color filter substrate side. (10) is a substrate, (12 ') is Al, (13) is Al ₂ O ₃ , (14) is SiN, (17) is a transparent electrode (pixel electrode), and (15) is undoped a-Si (i) and (16) are hydrogenated amorphous silicon doped with phosphorus (hereinafter referred to as a-Si (n ⁺ )), (18) is signal wiring, and (18 ') is a-Si (n ⁺ ) as a source electrode. The TFT and the pixel electrode are connected. 2 of ₍₁₁₎ serves for indicating the boundary of the otherwise and performing the anodic oxidation as the anode oxide boundary zone area, an area for performing the right area is the anodic oxidation from a boundary line _(11), the left side is not carried out areas .

In addition, near the gate electrode of the conventional TFT substrate, a structure as shown in Figs. 32A and 32B has been used. FIG. 32A is a plan view near the gate electrode, and FIG. 32B is a sectional view taken along the line AA ′. In the same figure, reference numeral 10 denotes a substrate, 11 denotes Cr, 12 denotes Al, 14 denotes SiN, 15 denotes a-Si, 55 denotes a source electrode, and 18 denotes a source electrode. Signal wiring, which also serves as a drain electrode, denotes a transparent electrode serving as a pixel electrode.

As shown in the figure, conventionally, Cr is used for the gate electrode and SiN is used for the gate insulating film. On the other hand, a two-layer metal of Cr and Al is used for the gate wiring. Thus, the reason why the gate electrode and the gate wiring are formed of different materials will be described below.

First, the metal of the gate electrode has a condition that the adhesion to the substrate is good, there are no irregularities on the surface, and that the metal of the gate electrode does not deteriorate in the process of forming SiN as the gate insulating film. Cr is suitable as this condition. On the other hand, since the gate wiring is required to have a low resistance, Cr has a high resistivity of at least one digit compared to Al, which is not suitable for the gate wiring. On the contrary, Al tends to generate hillocks and tends to cause needle-shaped convex defects on its surface. In addition, there is a problem that this hill grows in the process of forming SiN (usually deposited at a substrate temperature of 200 to 350 DEG C by a plasma CVD method), which is a gate insulating film, and thus cannot be used as a gate electrode. Therefore, conventionally, a two-layered metal of Cr and Al is used for the gate electrode and Cr for the gate wiring.

On the other hand, as a final technique, there is an anodization technique of Ta or Al (for example, Japanese Electrochemical Manual (Maruzen) issued in December 1964, see pages 874 to 892), which electrochemically oxidizes the surface of a metal. This technique is conventionally used for capacitors and surface coatings.

An advantage of the oxide film (insulation film) by this technique is that defects due to dust are hard to occur. For this reason, there exists a conventional technique which used this technique for TFT (Japanese Patent Laid-Open No. 58-147069, Japanese Patent Laid-Open No. 61-133662).

Further, the prior arts related to the present invention include Japanese Patent Laid-Open Nos. 63-164 and Japanese Patent Laid-Open Nos. 58-90770 and 58-93092 as related to the anodic oxidation.

However, the prior art has the following problems because Al is used for the gate terminal or the gate electrode, and only a portion thereof is anodized.

In the conventional TFT substrate as shown in Fig. 2, Al is also used for the gate terminal. Usually, the gate terminal of a TFT substrate is used in the state exposed to air | atmosphere. Al is susceptible to deterioration such as electrical corrosion, and the use of Al for the gate terminal impairs the reliability of the TFT panel.

② Al is not preferable because heat stress causes rod-shaped crystals or heels called whiskers, which cause irregularities on the surface. In particular, whiskers are beard defects of several tens of micrometers, which causes short circuits between electrodes.

As described above, the related art has a problem in terms of yield at the time of manufacture due to the reliability or defect occurrence of the gate terminal.

(3) The gate wiring must be electrically connected to an external circuit at its end. Therefore, research is needed to prevent anodization of this part. It is contemplated to cover this part with a resist so that it does not come in direct contact with the anodizing solution. However, at this time, there is a problem that Al breaks along the resist end due to a phenomenon caused by electrostatic breakdown of the resist.

(4) When a positive photoresist is used as the mask for anodization, there is a problem in which defects such as Al melt at the intersection between the Al pattern and the mask pattern for anodic oxidation occur.

(5) The film thickness of Al ₂ O ₃ is desired to be as thin as possible from the viewpoint of gm mutual conductivity. On the other hand, a thick one is desirable in terms of electrostatic breakdown voltage. There was a problem that this film thickness was not optimized.

However, in the prior art, the gate electrode of the portion not covered by the anodization film is liable to cause electrical breakdown or alteration, and there is a possibility that a poor connection between the gate wiring and the external circuit may occur.

The present invention relates to a liquid crystal display device using a thin film transistor substrate.

1 is an equivalent circuit diagram, a plan view, a partially enlarged plan view, and a sectional view of a TFT substrate of one embodiment of the present invention;

2 is an equivalent circuit diagram, a plan view, and a sectional view of a conventional TFT substrate.

3 is an equivalent circuit diagram and a plan view of a TFT substrate of another embodiment of the present invention.

4 and 5 are plan views showing intersections of gate wirings and photoresist ends.

6 and 7 are overall plan views of one embodiment of a TFT substrate of the present invention.

8 is a plan view and a cross-sectional view of a TFT substrate of another embodiment of the present invention.

9 is a sectional view showing the manufacturing process

10 shows the relationship between the leakage current and the heat treatment temperature.

11 is a sectional view, plan view and partially enlarged plan view of a TFT substrate of another embodiment of the present invention;

12 is a cross-sectional view showing the manufacturing process thereof.

13 is a partial equivalent circuit diagram of a TFT substrate of an embodiment of the present invention.

FIG. 14 is a diagram showing the relationship between the mutual conductivity and the thickness of the insulating film, and the leak characteristic of the anodized film.

15 is a sectional view, plan view and partially enlarged plan view of a TFT substrate of another embodiment of the present invention;

16 and 17 are plan views showing intersections of gate wirings and photoresist ends.

18, 19 and 20 are cross-sectional views and plan views near the TFT portion of the TFT substrate of another embodiment of the present invention.

Fig. 21 is a plan view showing an intersection state between an Al pattern and a photoresist end;

22 and 23 show the effect of the angle of the intersection thereof.

Fig. 24 shows the effect of the film thickness of resists;

25 is an equivalent circuit diagram of a TFT substrate

Fig. 26 is an overall plan view showing an outline of a TFT substrate.

27, 29 and 30 are plan views showing intersections of Al patterns and photoresist ends.

Fig. 28 is a partial sectional view of a TFT substrate of another embodiment of the present invention.

31 is a cross-sectional view of an LCD panel according to an embodiment of the present invention.

32 is a plan view and a partial cross-sectional view of a conventional TFT substrate.

33 is a schematic diagram of a liquid crystal display device according to an embodiment of the present invention.

(Initiation of invention)

An object of the present invention is to provide a liquid crystal display device using a liquid crystal display panel using a thin film transistor substrate having high reliability and improved yield in manufacturing.

The above object is a terminal comprising a first wiring made of an insulating substrate and a metal mainly composed of aluminum or aluminum formed on the insulating substrate, and a conductive film of a material different from the first wiring, and the first wiring and the terminal. A second wiring electrically connected, wherein the first wiring is partially covered by an insulating film made of an oxide of aluminum, and the first wiring is exposed from the insulating film at least in a portion where the first wiring is connected to the terminal. And the second wiring is achieved by the liquid crystal display device, characterized in that, in the connection portion, the first wiring covers a region exposed from the insulating film.

It is preferable that the terminal of the liquid crystal display device has a layer made of at least chromium or tantalum.

In addition, the second wiring is preferably made of a transparent electrode.

In addition, the second wiring preferably has a layer made of chromium.

In addition, it is preferable that the second wiring has a layer made of aluminum.

The second wiring is preferably made of a transparent electrode, and the terminal is preferably covered by the second wiring.

In this case, the terminal preferably has a layer made of at least chromium or tantalum.

In the present invention, Cr or Ta is used as the gate terminal, and Al or Al, which is the gate wiring at the tip end of the gate terminal, is connected with a metal having a main component. Since Al tends to deteriorate due to thermal stress, it is preferable to use a metal in which Pd or Si of 1% or less (at% or less) is added to Al in order to provide resistance to thermal stress. Hereinafter, such Al is recorded as Al (Pd) and Al (Si). Al (Pd) and Al (Si) can be anodized similarly to Al, and can form Al ₂ O ₃ similar to that of pure Al. It is not preferable to add Si or Pd in an amount exceeding 1% because the internal pressure of Al ₂ O ₃ obtained deteriorates. The preferable addition amount of Si and Pd is 0.01% or more, and especially the range of 0.1%-0.3% is more preferable. In the comparison between Al (Pd) and Al (Si), the anodization film formed is more preferably about 30% higher in electrons, and more preferably Al (Pd). In addition, when using the Al ₂ O ₃ as a gate insulating film of the TFT, the film thickness of the Al ₂ 0 ₃ is in the point of mutual conductivity, and it is preferably as thin as possible, it is desired that the thick points of the electrostatic breakdown voltage. Therefore, the preferable film thickness is in the range of 1100 kPa to 2200 kPa, and the more preferable film thickness is in the range of 1100 kPa to 2100 kPa.

Al (Pd) and Al (Si) were improved in heel resistance but could not prevent whiskers. As a result of the examination, it was found that the whiskers can be prevented by making the wiring width finer than 20 µm as shown in Table 1. Usually, the Al wiring width is about 100 μm, but the end of the line of the connection point between Cr or Ta and Al, Al (Pd), and Al (Si) described above has a stripe shape having a line width of 20 μm or less. desirable. Thereby, the occurrence of whiskers could be completely prevented. In addition, the line width of the stripe is preferably 5 µm or more.

Al wire width (μm) Whisker density (pieces / μm) 70 5 × 10 ^-6 30 3 × 10 ^-6 20 ○ 10 ○

In the case of anodizing the present invention, if there are two kinds of metals with Cr and Al or Al as the main component, the part in which the metal containing Cr, Al or Al as the main component is in contact with the anodic oxidation solution In this case, Cr in this part is eluted by the battery reaction, and this part disappears and the gate is disconnected. When Ta is used instead of Cr, the boundary between Ta ₂ O ₅ and Al ₂ O ₃ is different because the volume expansion rate when changing from Al to Al ₂ O ₃ and the volume expansion rate when changing from Ta to Ta ₂ O ₅ are different. Peeling arises from the vicinity, and there exists a possibility that a gate may be disconnected. Therefore, it is necessary to perform anodization after completely covering such a portion with the photoresist.

Further, in the TFT substrate manufacturing method of the present invention, a more preferable manufacturing method is a method of performing post-heat treatment (photosbaking) of photoresist before development when forming a photoresist pattern to be subjected to anodization. That is, the pattern formation of the photoresist is usually

① Application of photoresist

② Heat treatment (prebaking)

③ exposure

④ phenomenon

⑤ Post heat treatment (post baking)

The procedure is as follows. In this case, when the photoresist remains in development, this residue is fixed by baking in the post heat treatment. If foreign matter in the furnace or foreign matter around the substrate moves and adheres to the surface to be oxidized, the anodic oxidation solution cannot penetrate, and an anodized film cannot be formed in this part. Therefore, this part is exposed to metal and causes short circuit. Therefore, it is preferable to carry out in the following order.

① Application of photoresist

② Heat treatment (prebaking)

③ exposure

④ Post Heat Treatment (Post Baking)

⑤ Status

Next, the operation of the present invention will be described.

① Cr or Ta is strong against electrical corrosion even in the air, improving reliability.

(2) When using Al containing 1% or less of Pd or Si instead of Al, hillock and migration are improved, and reliability is further improved.

(3) The whisker does not occur when the Al portion is made into a thin line having a line width of 20 µm or less. Thus, the yield is improved.

In addition, the anodizing method of the present invention has the following functions. As a masking material for selectively performing anodization, a positive type resist is frequently used in a conventional semiconductor process. This masks the resist so that it crosses the Al pattern, and then anodizes, and at the intersection between the patterns, oxidation may proceed even under the resist mask, and in the worst case, Al may melt. This is due to the breakdown voltage failure of the masking photoresist. It was found that this breakdown pressure resistance was insufficient only by increasing the thickness of the resist. When the photoresist pattern is selectively coated on the Al or Al-based metal pattern, and the angle of the pattern where the Al and the resist overlap (the part where the surface becomes Al after anodization) is 90 ° or less When irradiated with ultraviolet rays for patterning the resist, it was found that due to the halation at the edge of the Al pattern, the resist in the vicinity reduced the film thickness, resulting in a breakdown voltage failure. In other words, when the pattern of the masking photoresist is made of Al or Al as a main component, the pattern of the resist portion of the metal is formed when the angle between Al and the resist, which is formed outside the pattern, is 90 ° or less. When irradiated with ultraviolet rays, it was found that the resist near it caused a decrease in film thickness due to the halation at the edge of the Al pattern, resulting in a breakdown voltage failure. Therefore, when the photoresist is exposed to light, the masking photoresist pattern is made to have a large angle between the Al and the resist to be formed on the outer side of the pattern with respect to the pattern of the Al to Al or Al metal as the main component. It was found that the effect of the halation light on the pattern edge was eliminated, and the film thickness reduction phenomenon of the photoresist did not occur, and in this case, it had sufficient internal pressure. As a result, defects during anodization (unnecessary oxidation and dissolution of Al under photoresist) could be eliminated.

This embodiment is explained using FIG. 21, FIG. On the insulating substrate 10, Al (12 ') was deposited by a vacuum deposition method of 0.2 mu m in thickness, for example, and patterned by ordinary photoetching. Then, a positive photoresist (PR) was applied at a film thickness of 2 µm, and ultraviolet rays were selectively irradiated and exposed using a desired photomask. This was developed and set as the shape shown in FIG.

Fig. 22 shows the experimental results when the pattern of the photoresist is changed, and the horizontal axis shows the angles θ1 and θ2 occurring outside the pattern of the masking photoresist and the Al pattern of the portion to be oxidized (Al for Al). And the angle θ of the portion where the resist overlaps, hereinafter simply referred to as outer angle). In terms of the shape after anodization, the angle formed between the contour of the oxidized aluminum pattern and the unoxidized Al pattern on the Al pattern is the angle at which Al is exposed without being oxidized. . In addition, the vertical axis | shaft is the defect occurrence rate at the time of anodization, and the parameter in the figure is the film thickness of the masking photoresist.

As is apparent from this experimental result, the defect is more likely to occur when the thickness of the photoresist is thinner and the outer shell is smaller. If the film thickness of the photoresist is 2.6 mu m, the defect becomes zero at an angle of 60 degrees. If the film thickness of the photoresist is 1 µm, defects may occur even at an angle of 90 degrees. It turns out that 1.5 micrometers or more are needed as a film thickness of a photoresist in order that the possibility of a defect generate | occur | producing at the angle of 90 degrees disappears at all. The results also show that the larger the angle, the safer it is.

Fig. 23 shows the occurrence of defects during anodization due to the influence of halation light in the positive type photoresist in relation to the thickness of the resist film and? In Fig. 21. The horizontal axis in Fig. 23 is the resist film thickness, and the vertical axis is θ. When the thickness of the resist film is T, the upper portion of the line θ = 110-20T in the figure indicates a region where no defect occurs.

The above description is in the case of using a positive type resist as a mask for anodization. In the case of a negative type resist, the photochemical reaction is reversed. In other words, in the positive type, low molecular weight is generated by light, and in the negative type, light is polymerized. Therefore, in the negative type, the influence of halation light is reversed. That is, in the negative type, the photoresist which should not be inherent around the Al pattern remains slightly due to the halation light. Since the resist is particularly thin, the dielectric breakdown voltage is low, resulting in defects during anodization. In the negative type, the mechanism of generating residues of the thin resist with low dielectric breakdown voltage is different from that in the negative type, but the cause of the defect is both caused by the influence of halation light. In the negative type, the masking photoresist pattern is formed at an angle of 90 ° or less by the Al and the resist pattern generated outside of the Al pattern with respect to the pattern of the Al- or Al-oxidized metal-oxidized part pattern. It was confirmed that the influence of the halation light on the Al pattern edge at the time of exposure to light can be eliminated, and the extra film residual phenomenon of the photoresist does not occur.

In other words, the negative angle of the negative type should be 90 ° or less. In this case, it was found that it had sufficient internal pressure.

An example of experiments on the post-baking treatment of the positive photoresist before anodization is shown in FIG. 24.

24 is the post-baking temperature. The vertical axis is the defect occurrence rate. The film thickness of the resist is 2.8 mu m.

The parameter is the pattern of the masking photoresist described above and the angle (outer angle) generated outside the Al pattern. From this experiment result, it turns out that a defect increases when the phosphbing temperature is low. Unlike this experiment, if the postbaking strength is too strong, a defect occurs that causes cracks in the photoresist. The limit of postbaking strength is ① temperature is 160 ℃ and ② time is 40 minutes.

Moreover, when post-baking intensity | strength was too small, defects increased and it was confirmed that the minimum is ① temperature of 120 degreeC, and ② time is 5 minutes. The effect of the postbaking strength was not different in the negative type positive type.

From the findings of the above experiment, when the outer angle θ of the defect generation limit is obtained as a function of the film thickness T of the positive type resist, the outer angle is as shown in FIG.

θ = 110-20T

(Obtained from the data in FIG. 22).

In this equation, the limit that a resist produces photochemical reaction is calculated | required by the influence of the halation light in Al-pattern edge.

That is, in a positive type resist, the area | region of an angle larger than the angle obtained by this formula is a area | region which does not generate a defect.

In a typical photoprocess, the maximum coating film thickness of the photoresist is about 5 mu m. The withstand voltage of the resist in this film thickness was 250V. Therefore, there is an upper limit in raising the anodic oxidation voltage, and 200 V or less is preferable. The film thickness of Al ₂ O ₃ formed at 200 V as this upper limit was about 280 nm.

The above description has been made of the case where pure Al is used for the Al pattern, but Al (Si) or Al (Pd) material in which Al or a small amount of Si or Pd is mixed in a few% or less is similarly anodized without defects by the above method. It can be seen that Al ₂ O ₃ can be obtained. That is, the present invention is a technique that can be generally applied to Al alloy materials as well as pure Al.

According to the present invention, as shown in Fig. 9 (e), the transparent electrode 17 is patterned and left in the gate terminal portion, and the Al ₂ O ₃ (13) of the gate wiring is formed at the coarse portion with the gate terminal of the gate wiring. By covering the portion not covered by the transparent electrode 17 with the transparent electrode 17, the Al film 12 of the gate wiring exposed from the Al ₂ O ₃ (13) is protected by the transparent electrode 17, and thus, It does not cause deterioration.

According to the present invention, as shown in Fig. 9E, the Cr / Al (18) for the signal line source electrode is patterned and left in the gate terminal portion, and the gate wiring portion is connected to the gate terminal of the gate wiring. Since the portion not covered by Al ₂ O ₃ (13) is covered with Cr / Al (18), the Al film 12 of the gate wiring exposed from Al ₂ O ₃ (13) is protected by the Cr film. It does not cause eating and deterioration.

Therefore, according to the present invention shown in Fig. 9E, the reliability of the connection portion between the gate terminal and the gate wiring is improved.

(The best form to carry out invention)

EMBODIMENT OF THE INVENTION Hereinafter, this invention is demonstrated in detail using an Example.

Example 1

Fig. 1 (a) is an equivalent circuit diagram of a TFT substrate according to one embodiment of the present invention, Fig. 1 (b) is a plan view thereof, Fig. 1 (c) is an enlarged plan view of region A of Fig. 1 (b), and Fig. 1 (d). Is its cross section. (Cad) denotes an additional capacitance, (PAD) denotes an anodization pad, (1) a cutting line, (L) an anodization bus line, and (20) a SiN protective film. The other symbols are the same as described in FIG.

First, the manufacturing method of this TFT substrate is demonstrated. Cr 11 is deposited on the substrate 10 at a thickness of about 1000 mW by sputtering, and gate terminals G ₁ and G ₂ are formed by photoetching (etching using photoresist as a mask). . On it, Al (Pd) (addition amount 0.1% of Pd) 12 was deposited by sputtering to a thickness of 2800 kPa, and the gate wirings G ₁ ′, G ₂ ′, and addition of Al (Pd) by photoetching were added. A pattern of the capacitor Cad and the gate electrode is formed.

Gate wirings G ₁ ′, G ₂ ′, and gate terminals G ₁ , G ₂ are connected in hatched region A. FIG. At this time, the pattern of the area A has a stripe shape in which the line width d of Al (Pd) is 20 µm or less, as shown in Fig. 1C. This works because it prevents whiskers. Thereafter, the film is coated with a photoresist except for the anodizing portion (right side of the boundary line 11 in the drawing) and the anodizing pad PAD. In Fig. 1C, (d ') indicates the distance between the photoresist end and the Cr 11 of the gate terminal.

As described above, Cr is eluted by the battery reaction when it comes into contact with the anodic oxidation solution, and therefore it should not be in contact with the anodic oxidation solution. On the other hand, even when coated with a photoresist, the anodic oxidation solution permeates from the interface between the photoresist and Al (Pd). This permeation distance is about 100 μm. Therefore, as (d '), you may be 100 micrometers or more.

Gate wirings G ₁ ', (G ₂ '), (G ₃ '), ..., (G _N ') and the photoresist end of Al (Pd) are orthogonal as shown in FIG. As shown in FIG. 5, when (G ₁ ′) and (l ₁ ) are crossed at an acute angle (θ), when anodized, Al (Pd) in the portion indicated by R elutes in the figure. The gate wiring is broken. This is because the film thickness of the cross section of the positive photoresist becomes thin due to the halation of the sidewall of Al (Pd), and the breakdown voltage disappears. The gate terminals G ₁ , G ₂ , G ₃ , G ₃ , G _N are commonly connected to the anodization bus line L, and the anodic oxidation bus line L is provided. Anodization pad (PAD) for supplying a voltage for anodization is installed at the tip of the). This anodic oxidation bus line L is formed of Al (Pd) 12. In this state, anodization is performed.

6 and 7 show the entire TFT substrate. FIG. 6 shows an example in which a gate terminal is commonly connected in the anodic oxidation bus line L on the left side, and supplies a voltage for anodizing therefrom. Anodization pad PAD or anodization bus line L is simultaneously formed using Al (Pd) of the gate wiring. The inside of the boundary line ₁₁ is an area | region which anodizes. Outside the boundary line 1 ₁ are all covered with resist except for the pad for anodization (PAD).

7 shows an example in which the gate wirings are drawn out to the left and right. In this case, two anodization bus lines L are required. In the case of using the edge portion of the anodization pad PAD for applying a voltage as in this example, the space can be effectively utilized. In this case, the liquid level AL indicates the liquid level of the anodic oxidation liquid. The substrate is obliquely penetrated into the liquid flow, and a portion of the pad for anodization (PAD) is taken out to the liquid surface, and a voltage is applied by fitting it with a clip or the like. If the anodizing pad PAD is wet with anodizing solution, an insulating film is formed on the surface thereof and cannot be oxidized. Thus, the liquid level adjustment becomes extremely easy by immersing it in the liquid at an angle.

The anodic oxidation method is performed by allowing the anodization pad PAD to come out of the liquid level to penetrate the anodic oxidation liquid, and apply a DC voltage of 72 V to 144 V at maximum to the anodization pad PAD. The application method is gradually boosted from OV so as to have a constant current of 0.5 to 5 mA / cm 2. When a high voltage is applied from the beginning, since a large current flows, the Al (Pd) line melts and the gate line is disconnected. As the anodic oxidation solution, a solution obtained by diluting a solution obtained by adjusting 3% tin acid to PH7.0 ± 0.5 with ammonia at 1: 9 in an ethylene glycol solution is used. If the current is 0.5 mA / cm 2, the anodic oxidation voltage becomes 144 V in about 10 minutes. At this time, the thickness of the formed Al ₂ O ₃ ((13) in FIG. 1 (d)) is 2000 kPa.

This Al ₂ O ₃ is used as a dielectric for the gate insulating film and the additional capacitance portion. Moreover, after it becomes 114V and it becomes constant voltage oxidation, it is preferable to hold | maintain in that state for several minutes to several minutes. This is important for obtaining a uniform Al ₂ O ₃ film.

It returns to FIG. 1 again and demonstrates. After removing the photoresist, the TFT is formed by the following method. 2000 ns of SiNs 14 are formed on the entire surface by plasma CVD. As the material gas, a gas containing SiH ₄ and NH ₃ as main components is used. A-Si (i) (15) was deposited thereon at 2000 kPa, and a-Si (n ⁺ ) (16) doped with 2.5% phosphorus was deposited at 3000 kPa. At this time, the substrate temperature is 300 deg. As the material gas, a-Si is a gas containing SiH ₄ as a main component, and a mixed gas of SiH ₄ and PH ₃ is used for a-Si (n ⁺ ). Thereafter, a-Si rolls are patterned to form an array. The dry etching method by SF ₆ gas is used for the etching liquid of a plasma film. As the transparent electrode for the pixel electrode, indium oxide (1000 kS) was deposited and processed to form a transparent electrode (17).

The signal wiring 1 serving as the drain electrode of the TFT and Cr / Al for the source electrode are formed by sputtering at a thickness of 1000 mW and 3500 mW respectively and patterned. Dry etching of a-Si (n ⁺ ) 16 using the drain electrode as a mask.

Finally, as the protective film 20, SiN is formed to 1 mu m, and the SiN on the terminal portion is removed, and the TFT substrate is mechanically cut between the anodized bus line L and the gate terminals G ₁ and G ₂ . This is complete.

Here, a two-layer film of Al ₂ O ₃ and SiN is used for the gate insulating film, but the SiN film is not necessarily required. In addition, SiO ₂ may be used instead of the SiN film.

In the TFT substrate, a maximum voltage of about 25 V is applied between the gate electrode and another electrode. Therefore, the minimum thickness of the Al ₂ O ₃ film is 500 kPa or more. In addition, although FIG. 1 has shown the case where each pixel arrange | positioned in a column, the arrangement which shifted by half pitch may be sufficient. In addition, of course, even if there is no additional capacity (Cad) can be produced completely similarly.

Also, using Al and Al (Si) in addition to Al (Pd), a TFT substrate could be similarly produced. Also, using Ta instead of Cr as a gate terminal could produce a TFT substrate.

In this embodiment, a portion which does not want to be anodized is covered with a photoresist, but a method may be conceived so that the portion which does not want to be anodized does not come into contact with the anodizing liquid.

However, this method is not preferable because Al has a drawback in that the wiring is broken because a large current flows to the newly contacted part when the liquid level is slightly shaken.

Next, the transmissive substrate having the opposite electrode and the color filter array of blue, red, and green and the TFT substrate prepared as described above are bonded together using a spacer having a thickness of 7.3 μm, and the liquid crystal is sealed in between to prevent the liquid crystal display panel. Completed. The structure will be described below.

31 shows the entire cross-sectional structure of the color liquid crystal display panel. A TFT substrate having TFTs and the like formed on the transparent glass substrate 10 is disposed below the liquid crystal LC, and a transparent glass substrate having a color filter FIL and a black matrix BM is formed thereon. 10b) is arranged. The lower transparent glass substrate 10 has a thickness of about 1.1 mm.

31 shows the cross section of one pixel portion, the left side shows the cross section of the portion where the outer lead line exists as the left edge portion of the transparent glass substrates 10 and 10b, and the right side the transparent glass substrate 10. ) And (b) the cross sections of the right edge portion where no external lead line exists.

The sealing material SL shown on each of the left and right sides of FIG. 31 is configured to seal and prevent the liquid crystal LC, and the transparent glass substrates 10 and (not shown) except for the liquid crystal encapsulation opening (not shown) are provided. It is formed along the whole periphery of 10b). The sealing material SL is made of epoxy resin, for example.

At least one common transparent pixel electrode 17b on the upper transparent glass substrate 10b side is connected to an external lead line 17 'formed on the lower transparent glass substrate 10 side by a silver paste material SIL. have. The external lead line is formed in the same manufacturing process as each of the gate electrode, the source electrode, and the drain electrode.

The layers of the alignment films ORI1 and ORI2, the transparent electrode 17, the common transparent pixel electrode 17b, the protective films 20 and 20b, and the SiN 14 serving as the insulating film are inside the sealing material SL. Is formed. The polarizing plates POL1 and POL2 are formed on the outer surfaces of the lower transparent glass substrate 10 and the upper transparent glass substrate 10b, respectively.

The liquid crystal LC is enclosed between the lower alignment film ORI1 and the upper alignment film ORI2 for setting the direction of the liquid crystal molecules and sealed by the sealing material SL.

The lower alignment layer ORI1 is formed on the passivation layer 20 toward the lower transparent glass substrate 10.

On the inner surface of the upper transparent glass substrate 10b (the liquid crystal side), a light shielding film BM, a color filter FIL, a protective film 20b, a common transparent pixel electrode 17b, and an upper alignment film ORI2 are sequentially stacked and formed. It is.

Example 2

Fig. 3A is an equivalent circuit diagram of a TFT substrate of another embodiment of the present invention, and Fig. 3B is a plan view thereof. The difference from Example 1 is that the additional capacitance Ca is changed into the accumulation capacitance Cst. In the additional capacitance of Example 1, the adjacent gate line was the counter electrode, but in the case of the storage capacitor, the counter electrode wirings ST1 and ST2 are required as shown in FIG. As shown in Fig. 3A, the counter electrode wiring is connected in common and connected to the storage capacitor terminal ST. In addition, all the symbols of FIG. 3 are the same as FIG.

The manufacturing method of the TFT substrate of this embodiment is also almost the same as that of the first embodiment. The difference in manufacturing method is that in this case, it is connected to the pads for anodization (PAD 1, PAD 2) different from the gate wiring, the storage capacitance, and the counter electrode wiring, so that different anodic oxidation voltages can be applied. to be. That is, while the gate insulating film is applied with a relatively high voltage (25V) as described above, only about 7V is applied to the storage capacitor (Cst), and only a lower voltage is applied. On the other hand, the storage capacitor Cst impairs the transmittance of the TFT substrate, and the smaller the area of the electrode, the better. In other words, the thinner the Al ₂ O ₃ film thickness of the storage capacitor Cst, the smaller the electrode area may be. Therefore, the voltages applied to (PAD1) and (PAD2) are different. Al ₂ O ₃ for the gate insulating film is thick (2000 kV, voltage 144 V), and Al ₂ O ₃ for the storage capacitance Cst is thin (500 kV). Voltage 36V).

After completing the thin film circuit in the same manner as in Example 1, the anodization line was cut off at the cutting line 1 to remove it from the TFT substrate, thereby completing the TFT substrate.

Subsequently, the TFT substrate and the light transmissive substrate were bonded together using a spacer having a thickness of 7.3 μm, and the liquid crystal was sealed in between to seal the liquid crystal display panel.

Example 3

Fig. 8A is a partial plan view of a TFT substrate of another embodiment of the present invention, Fig. 8B is a sectional view thereof, and Fig. 9 is a sectional view showing the manufacturing process thereof. In this embodiment, only the portions indicated by the regions (a), (b), and (c) (which correspond to the TFT portion, the wiring crossing portion, and the thin film capacitance portion (here, the additional capacitance portion)) are subjected to anodization. Do it.

First, the manufacturing method of a TFT substrate is demonstrated. Cr (11) is deposited on the insulating substrate (10) to a thickness of about 1100 kW by sputtering, and is connected to the gate terminals (G ₁ ), (G ₂ ) and these by photoetching to supply voltage for anodizing A pattern of the anodic oxidation bus line L to be formed is formed (Fig. 9 (a)). On top of that, Al (Pd) (addition amount 0.1% of Pd) (12) is deposited by sputtering at a thickness of 2800 kPa, and the gate wirings of Al (Pd) (G ₁ '), (G ₂ '), addition A pattern of the capacitor, the gate electrode, and the anodization bus line L is formed. Is the same as the gate wiring _{(G 1 '), (G} 2') the gate terminal (G _1), the shape the shape of a (G ₂₎ the area of between the connection A is shown in Example 1 eseo 1 (c) of ( 9 (b)).

The photoresist is applied to a thickness of 3 μm, prebaked at 90 ° C. and then exposed. After that, post-baking at 140 ° C is performed, and development is continued. As a result, the photoresist of the portions (areas a, b and c in FIG. 8) and the anodization pad PAD is removed. 9 (c) shows an example in which only the gate terminal portion leaves the photoresist PR.

In this state, the TFT substrate is made to penetrate the anodic coral solution by letting out the pad for anodization (PAD) out from the liquid surface, and anodic oxidation is performed by applying a DC voltage to the pad for anodic oxidation (PAD). With respect to Al (Pd) to be anodized, the voltage is gradually raised from OV to a current density of 145V so as to have a current density of 0.5 mA / cm 2 (constant current oxidation). When the voltage reaches 145V, the voltage remains as it is (constant voltage oxidation). In about 30 minutes, Al ₂ O ₃ (13) with a thickness of about 2000 mm ₃ can be obtained. At this time, 1300 kV of the 2,800 kPa of Al (Pd) is oxidized. By anodizing only the regions (a), (b), and (c), most of the gate wirings G ₁ ′, G ₂ ′ do not need to be oxidized, so that the wiring resistance can be reduced.

After removing the resist, it is heated at 200 ° C. for 60 minutes in the atmosphere. By this heating, the leak current of Al ₂ O ₃ decreases by one or more digits. 10 shows the relationship between the leakage current of Al ₂ O ₃ and the heat treatment temperature. The heat treatment temperature is preferably in the range of 200 ° C to 350 ° C. When the temperature is higher than 350 ° C, exfoliation of Al ₂ O ₃ occurs. Plasma CVD was performed to form a-Si (n ⁺ ) 16 doped with SiN 14 at a thickness of 2000 GPa, a-Si (i) 15 at a thickness of 2000 GPa, and 2.5% doped with phosphorus. It is deposited to a thickness of 300Å. At this time, the substrate temperature is 300 ℃. Thereafter, a-Si is patterned to leave a-Si in the TFT portion and the wiring intersection portion. Thereafter, the SiN 14 is patterned to remove SiN on the gate terminal (Fig. 9 (d)). As the transparent electrode 17, indium oxide was sputtered to a thickness of 1000 GPa and patterned to form the transparent electrode 1 and the gate terminal.

The signal wiring 18 serving as the drain electrode of the TFT and Cr / Al for the source electrode are respectively deposited by sputtering and patterned to a thickness of 600 mW and 4000 mW. Finally, as the protective film 20, SiN is formed to 1 mu m, the SiN on the terminal portion is removed, and the TFT substrate is completed by mechanically cutting between the anodization bus line L and the gate terminals G1 and G2. (FIG. 9 (e)).

The TFT substrate thus obtained has a low gate wiring resistance, no short circuit between currents in the TFT section and the wiring crossing section, and a dielectric constant of Al ₂ O ₃ is 9.2, which is about 30% higher than 6.7 of SiN. The conductivity gm can be increased by about 1.5 times, and the area of the additional capacitance portion can also be reduced, thereby improving the transmittance. In this way, a high yield, high performance TFT substrate was obtained.

Next, a translucent substrate having a counter electrode and a color filter array of blue, red, and green, and a TFT substrate prepared as described above are pasted together using a spacer having a thickness of 7.3 μm, and a liquid crystal is sealed in between to seal the liquid crystal display panel. Was completed.

In this embodiment, Al (Pd) was used as the gate wiring pattern material. However, Al and Al (Si) could also be used to manufacture the TFT substrate. In addition, even when Ta was used instead of Cr as the gate terminal material, a TFT substrate could be manufactured in the same manner. Examples of additional capacitances are shown as thin film capacitances, but storage capacities could be similarly produced.

In addition, Al ₂ O ₃ is not limited to the process after forming, for example, to form a signal wiring of a Cr / Al first, a transparent electrode may be formed later. Al ₂ O ₃ formed by anodic oxidation, but the display example of 2000Å, it is preferable that the 1100Å~2200Å.

In addition, although the example which a-Si is an active layer of TFT was mentioned, it is a matter of course that other materials, such as poly Si, may be sufficient.

Example 4

It demonstrates using FIG.11 (a), (b), (c), FIG.12 (a), (b), (c), (d), (e).

Fig. 11A shows a cross section of a TFT substrate of another embodiment of the present invention, and Fig. 11B shows its plane. In the figure, 10 is an insulating substrate, (12 ') is Al (11) of the gate wiring pattern is Cr for the gate terminal, 13 is an Al ₂ O _3, (14 anode oxide film of Al ") is Silicon nitride film, (15 ') is a-Si, (19) is silicon nitride film, (16) is hydrogenated amorphous silicon (n ⁺ layer) doped with phosphorus, (11'), (12 '), (17 ) Are Cr, Al, transparent electrode, (20) is a protective film, (L) is an anodization bus line, (G ₁ '), (G ₂ ') is a gate wiring, and (D1) is a drain terminal (thin film transistor (A) denotes an anodization region of the TFT portion, (b) denotes an interconnection region, and (c) denotes an anodization region of the thin film capacitor portion.

12 (a), (b), (c), (d), and (e) show cross-sectional views in the respective steps. 12 (a) after anodization, FIG. 12 (b) after patterning the silicon nitride film, FIG. 12 (c) after patterning the n ⁺ layer, and FIG. 12 (d) after Al (12 ") After patterning, Fig. 12E shows the patterning of the transparent electrode 17 for pixel electrodes.

Cr is deposited on the insulating substrate 10 to a thickness of 1100 에 by sputtering and patterned to form a gate terminal G ₁ ′, G ₂ ′, and an anode serving as a voltage supply line for common connection and anodization thereof. Oxide bus line (L) is formed. Further, Al is formed by sputtering to a thickness of 2600 mA and patterned to form a gate electrode 12 ', a gate wiring G ₁ ′, and G ₂ ′. In this case, each gate wiring G ₁ ′, G ₂ ′ is commonly connected by an anodization bus line L. FIG. Thereafter, the photoresist is applied to 3 mu m, and the resist in the areas (a), (b) and (c) surrounded by the dotted lines in FIG. 11 (b) is removed by the photoetching process.

In this state, the substrate is immersed in the anodizing solution and a voltage is supplied to the anodizing bus line. The voltage is gradually increased from OV to + 120V so as to have a current density of 0.5 to 10 mA / cm 2 with respect to Al for anodizing. When it reaches + 120V, the voltage is maintained as it is (constant voltage oxidation). In about 30 minutes an Al ₂ O ₃ (13) of about 1700 kPa can be obtained. At this time, 1100 kV is oxidized among 2600 kPa of Al thickness. As the anodizing solution, a solution of neutralized 3% tartaric acid solution with ammonia, diluted 1: 9 with ethylene glycol or propylene glycol and adjusted to PH 7.0 ± 0.5 is used. By locally anodizing in this manner, since most of Al in the gate wirings G ₁ ′ and G ₂ ′ do not need to be anodized, the wiring resistance can be kept low.

11C, an enlarged view of the connection region A between Al (12 ') of the gate wiring and Cr (11) of the gate terminal is shown. (D) in the figure shows the line width of the Al pattern. The reason for such a complicated pattern is that a metal mainly composed of Al or Al prevents whiskers from being generated when thermal stress is applied. Whiskers may occur when the line width d of Al is 25 µm or more, but whiskers do not occur when the line width d is 20 µm or less, more preferably 10 µm or less. For this reason, it set as the pattern like FIG.11 (c). Of course, whiskers do not occur in the Al part covered with Al ₂ O ₃ .

After removing the resist, it is heated at 200 to 400 ° C. for 60 minutes in air or in vacuum. This heating reduces the leakage current of Al ₂ O ₃ by one or more digits. This is shown in FIG. 10. As heat processing temperature, the range of 200 degreeC-400 degreeC is preferable. When the temperature becomes higher than this, peeling occurs on the Al film. Plasma CVD allows the first silicon nitride 14 'to have a thickness of 1200 to 2000 GPa, the a-Si (15') to a thickness of 200 to 1000 GPa, and the second silicon nitride 19 to 1000 to 2000 GPa. To the thickness of. At this time, the substrate temperature was set to 150 to 300 ° C. Thereafter, the second silicon nitride 19 was patterned and left only on the channel and the wiring crossing portion of the TFT (Fig. 11 (a)).

Amorphous silicon (n ⁺ layer) 16 doped with 0.6 to 2.5% of phosphorus is deposited to a thickness of 200 to 500 mW, and patterned to remain only in the source / drain portions of the TFT. At this time, a-Si (15 ') is also removed at the same time. Cr (11 ') is deposited to a thickness of 500 to 1000 GPa, and Al (12 ") is deposited and patterned to resist thickness heating or sputtering to a thickness of 3000 to 8000 GPa, and the drain terminal (D1) and drain and source electrodes of the TFT are patterned. Next, a transparent electrode 17 made of indium oxide is deposited and patterned by about 1000 m sputtering to form a pixel electrode, a terminal, etc. Next, silicon nitride is deposited by plasma CVD to about 1 m. The thin film transistor substrate is completed by removing the silicon nitride on the terminal portion by the photo etching process.

The substrate and the opposing substrate are aligned, the liquid crystal is sealed in between, and the gate bus line L is cut along the cutting line 1 in Fig. 11 (b) to separate the gate terminals to complete the display panel. . The gate bus line L also serves to protect the panel from electrostatic breakdown.

The display panel thus obtained has a low gate wiring resistance, no short circuit between the electrodes at the TFT and the wiring intersection, and a dielectric constant of Al ₂ O ₃ of 9.2, which is about 30% higher than that of 6.7 of silicon nitride. The conductivity gm can be increased by about 1.5 times, and the area of the additional capacitance portion can also be reduced, thereby improving the transmittance. Thus, a high yield and high performance panel was obtained. Although Al is shown as an example in the case of using Al as the gate electrode and wiring, Al containing 1% or less of Si or Pd can be used in the same manner. Al is used for the drain terminal, but Al (Si) and Al (Pd) may be used instead of Al.

In addition, the description about the thin film capacitance is added. 13A, 13B, and 13C show circuit diagrams of portions corresponding to two pixels of the TFT substrate.

FIG. 13A shows the additional capacitance between the adjacent gate wirings and FIG. 13C shows the additional capacitance between the gate wirings thereof. In one case, Fig. 13 (d) shows another example in which additional capacitance is formed between adjacent gate wirings.

In the same figure, (G ₁ ′) is a gate wiring, (G ₂ ′) is an adjacent gate wiring, (T11), (T12) is TFT, (LC) is liquid crystal, (G), (S), (D Are the gate, source, and drain of the TFT, respectively. (Vcom) is a common terminal, (b) is a wiring crossing area, (Cad) is an additional capacitance, and (D1) and (D2) are drain terminals. It goes without saying that (G ₂ ′) may be a wiring separate from the gate wiring in Figs. 13 (b) and 13 (d).

Of course, in any case, it can be produced completely the same way. In this example, an example in which the gate electrode G and the wiring crossing area b are separated is shown. However, the gate electrode G may not be separated.

Particularly important is the Al ₂ O ₃ film thickness, which will be described. In terms of the mutual conductivity gm of the TFT, the thinner the gate insulating film, the better. In Fig. 14A, the relationship between the mutual conductivity gm, and the film thicknesses of Al ₂ O ₃ and SiN is shown. Conventionally, as the gate insulating film, SiN having a thickness of about 0.3 mu m is often used. When the mutual conductivity gm is 1 at this time, the value of the mutual conductivity gm when the film thicknesses of Al ₂ O ₃ and SiN are changed is displayed. As apparent from this figure, the advantage of providing a two-layer gate insulating film is that the mutual conductivity gm can be improved in addition to the short circuit between the electrodes. Therefore, the hatched area in Fig. 14A is a preferable area in terms of mutual conductivity gm. On the other hand, when it becomes thin, insulation breakdown voltage falls. In the normal operation state of the liquid crystal panel, a maximum voltage of 25V (gate is negative) is applied between the gate and the drain (signal wiring). In actual products, screening is performed at this three times 75V to compensate for this 25V voltage. Therefore, neither Al ₂ O ₃ nor SiN should be the film thickness that each film can withstand this voltage (assuming that there is a foreign material, if there is no part without Al ₂ O ₃ or part without SiN) Can not be done). Table 2 shows the breakdown voltage of the Al ₂ O ₃ and SiN films and the minimum film thickness withstanding 75V. Al ₂ O ₃ and SiN are required to have thicknesses of 1100 and 1200 GPa or more, respectively. The thickness of 1100 kPa of Al ₂ O ₃ corresponds to anodization voltage of 80V.

Film thickness withstand breakdown voltage 75V Anodic oxidation voltage MV / cm V VAl ₂ O ₃ 6.8 1100 80SiN 6.3 1200-

In addition, the leakage current characteristics of the anodic oxide film Al ₂ O ₃ are shown in Fig. 14B. This leak current is low up to a certain voltage, but rapidly increases above a certain voltage. This current is added to the OFF current of the TFT. Therefore, smaller is preferable. The OFF current of the TFT is about 10 ^-8 A / cm 2, and this leak current needs to be less than or equal to this. As described above, in the liquid crystal panel, a voltage of -25V is applied, but the leakage current becomes 10 ^-8 A / cm 2 or less at this voltage when the anodic oxidation voltage is 80V or more. In this respect, it can be said that the Al ₂ O ₃ film thickness is required to be 1100 GPa or more.

There is a resist breakdown voltage to limit the Al ₂ O ₃ film thickness. As described above, the portion that is not desired to be anodized is covered with photoresist, but when the anodic oxidation voltage exceeds the internal pressure of the photoresist, the resist is destroyed and Al under it is lost. Therefore, it is not suitable to increase the anodizing voltage, 150V are preferred or less (where Al ₂ O ₃ film thickness is about 2100~2200Å). The optimum film thickness regions of Al ₂ O ₃ and SiN described above in FIG. 14A are indicated by a lattice net.

Al ₂ O ₃ is preferably in the range of 1100 to 2200 GPa, particularly in the range of 1100 to 2100 GPa, and of SiN in the range of 1200 to 2000 GPa.

Example 5

In this embodiment, the entire surface is anodized except for the gate terminal portion. Fig. 15A shows a cross section of the TFT substrate according to the present embodiment, and Fig. 15B shows its plane. 15 (c) shows an enlarged view of the gate terminal and the gate wiring connection portion. The symbols of the respective parts are the same as in the above embodiment.

The fabrication process is the same as in Example 4. The only other is the shape of the photoresist during anodization. After Fig. 15 (b) the dotted line ₍₁₁₎ covering the gate terminal side from a line indicated by the resist, the anodic oxidation is carried out. When the Cr gate terminal comes in contact with the anodic oxidation solution, Cr in this part is eluted by the battery reaction, so it is necessary to completely coat the resist. In the drawing of Fig. 15C, the symbol d 'indicates the distance between the resist end portion and Cr, but since the anodic oxidation solution is infiltrated, (d') needs to be 100 µm or more. In this case, the resist end surface is orthogonal to the gate wiring as shown in Fig. 15C. Although the resist breakdown voltage was explained in Example 4, the breakdown voltage of this resist is largely determined by the relative positional relationship between the resist pattern and the Al wiring pattern. Explain this.

As shown in Fig. 16, the gate terminal has an oblique portion near its tip. When such a portion is covered with a photoresist, a photoresist pattern as shown in Fig. 16 (a portion where the diagonal portion is covered with the photoresist) is considered. At this time, the gate wiring and the resist end portion cross each other at angles θ ₁ and θ ₂ as shown in the figure. In this figure, θ ₁ is an obtuse angle and θ ₂ is an acute angle. However, if anodization is performed in such a resist pattern, the gate wiring is eluted at the acute angle θ, and the gate wiring is disconnected. This is because light is scattered by the gate wiring because the distance between the gate wiring and the resist end portion is close during the exposure of the resist pattern, and as a result, the resist film thickness of this portion becomes thin and the breakdown voltage falls.

This can be prevented by making θ ₁ and θ ₂ of the resist pattern at right angles or obtuse angles. 17 shows a case where both θ ₁ and θ ₂ are at right angles.

In Examples 4 and 5, the case where a silicon nitride film is formed on Al ₂ O ₃ has been described. In Examples 4 and 5, SiO ₂ can be used instead of silicon nitride.

SiO ₂ is formed by the following method. The substrate temperature for forming a SiO ₂ film having a film thickness of 1000 to 3000 Pa by the plasma CVD method using a mixed gas containing SiH ₄ and N ₂ O as a main component is 200 to 300 ° C. The structure in the case of using this SiO ₂ film differs only in that the silicon nitride 14 'in FIGS. 11 and 12 becomes SiO ₂ . Other than that is the same as that of Examples 4 and 5.

Example 6

In Examples 4 and 5, the first silicon nitride, amorphous silicon, and second silicon nitride were deposited on Al ₂ O ₃ in the order of plasma CVD, but the present embodiment is an example in which the second silicon nitride is not used. It demonstrates using FIG.18 (a), (b), (c), (d), (e), (f). 18A, 18B, and 18C show portions a corresponding to the TFT portion (region a), the wiring crossing portion (region b), and the additional capacitance portion (region c) shown in the same drawing (f). -a ', b-b', and c-c 'cross-sectional views are shown. Symbols in the drawings are the same as in the above embodiment. The planar arrangement is the same as in Fig. 11 (b).

2800 Al of Al (12 ') is formed on the insulating substrate 10. By patterning, a gate wiring pattern including the gate wiring G1 'and the gate electrode and the additional capacitance electrode is formed, and anodized to form Al ₂ O ₃ (13). At this time, anodizing voltage is set to 144V. As a result, the film thickness of Al ₂ O ₃ (13) is about 2000 kPa, and the film thickness of Al (12 ') which is not anodized is about 1500 kPa. Silicon nitride 14 '(which may be silicon oxide) is formed on the film by a plasma CVD method to a thickness of 1200 to 2000 GPa. Subsequently, 200 to 2000 microseconds of amorphous silicon 15 'is formed. Further, amorphous silicon 16 containing 0.5 to 2.5% of phosphorus is deposited. Thereafter, the amorphous silicon film of the portion other than the TFT portion and the wiring crossing portion is removed in the photoetching process. Thereafter, Cr (11 ') is formed to a thickness of 400 to 1000 GPa, and Al (12') is formed to a thickness of 3000 to 5000 GPa and patterned to form signal wiring, a TFT source and a drain electrode. Subsequently, the amorphous silicon 16 doped with phosphorus is processed using this as a mask. Thereafter, the indium oxide transparent electrode 17 is formed by sputtering to a thickness of 500 to 2000 mW to form a pixel electrode. This transparent electrode may be left over the entire area on Al. This completes the TFT substrate having the structure shown in Figs. 18A to 18C. A protective film silicon nitride (about 1 mu m) is formed thereon, and then the panel is completed in the same manner as in the above embodiment.

Not only this structure but also the wiring crossing portion and the additional capacitance portion can have a structure as shown in Figs. 18 (d) and (e), for example.

18 (d) shows an example in which the interlayer insulating film of the wiring crossing portion is made of Al ₂ O ₃ only, and FIG. 18 (e) shows an example in which the dielectric of the additional capacitance portion is made of Al ₂ O ₃ only. Thus, whether Al ₂ O ₃ , SiN, SiO, or a-Si is inserted can of course be selected by changing the mask.

In this embodiment, the amorphous silicon and the phosphorus-doped amorphous silicon film can be formed continuously, which makes it possible to stabilize the characteristics of the thin film transistor.

In addition, similar effects can be obtained even when Al (1% Si) and Al (0.3% Pd) are used instead of Al. In this case, a two-layer film of Cr and Al is used for the drain terminal, but only Al may be used.

Example 7

An example of an example in which an equivalent circuit is shown in Fig. 13B is shown in Figs. 19A, 19B, 19C, 19D and 19E. (B), (c), (d), and (e) are portions corresponding to lines A-A ', B-B', C-C ', and D-D' shown in the same drawing (a). Each section is shown.

Al (0.1% Pd) 12 was formed on the insulating substrate 10 to a thickness of 2800 GPa, and patterned by photoetching to form the gate electrode 56, the gate wiring G ₁ ′, and the storage capacitor line 51. ), And the accumulation capacity Cst is formed. By the method described in Examples 4 and 5, Al (Pd) was anodized to form Al ₂ O ₃ (13) with a thickness of 2000 GPa. The silicon nitride 14 'is formed to a thickness of 1200-2000 GPa by the plasma CVD method, and the amorphous silicon 15' is formed to a thickness of 200-2000 GPa. Further, amorphous silicon 16 containing phosphorus is formed. After that, the amorphous silicon of the portions other than the TFT portion and the wiring crossing portion is removed in the photoetching process. In addition, the silicon nitride film of the storage capacitor Cst is removed. So only Al ₂ O ₃ remains in the storage capacity. The silicon nitride film is usually removed by a plasma asher using CF ₄ gas, but the Al ₂ O ₃ film is extremely resistant to this CF ₄ gas asher, and thus, only SiN on Al ₂ O ₃ phase can be removed. Thereafter, Cr is formed to a thickness of 400 to 1000 mW and Al is formed to a thickness of 3000 to 5000 mW, and then patterned to form the signal wiring 18, the TFT source electrode 55, and the storage capacitor wiring 57. Next, this is used as a mask to process the amorphous silicon 16 doped with phosphorus. Thereafter, a transparent electrode 17 made of indium oxide is formed by sputtering to a thickness of 500 to 2000 GPa to form a pixel electrode. This transparent electrode may be left over the entire surface on Al. A silicon nitride film is formed as a protective film 20 thereon, and the TFT substrate is completed in the same manner as in the above embodiment.

In this embodiment, only Al ₂ O ₃ is used as the insulating film of the storage capacitor portion. In addition, an Al ₂ O ₃ / SiN 2 layer insulating film can be used, but the capacity of only Al ₂ O ₃ can be increased, and the area occupied by the storage capacitor can be made smaller, thereby improving the transmittance of the substrate. Can be. Table 3 summarizes the insulating film (dielectric film) usable in this example and the places where it is required.

Location Materials Oxide Film Silicon Nitride Film a-Si Film Gate Section ○ ○ ○ Gate Wiring and Signal Wiring Intersection ○ ○ △ Accumulation Capacitive Line and Signal Wiring Intersection ○ ○ △ Accumulation Capacitive ○ ○ ×

○ Necessary × Unnecessary △ Available anywhere

It is sufficient to decide whether or not to use? In the table.

Example 8

In Example 7, the storage capacitor line 51 is formed separately from the gate wiring G ₁ ′, but the present embodiment is shown in FIGS. 20 (a), (b), (c), (d), and (e). As shown, this is an example in which a portion of the adjacent gate wiring G ₂ ′ is used as the storage capacitance. 20 (b), (c), (d), and (e) correspond to the lines A-A ', B-B', C-C ', and D-D' shown in FIG. Sectional drawing of the part to show is shown, respectively.

Example 9

A ninth embodiment of the present invention will be described with reference to FIG.

On the insulating substrate 10, Al (12 ') was deposited to a film thickness of 0.2 mu m by the vacuum deposition method, and this was patterned by a normal photoetching method. Next, a positive photoresist (PR) (trade name OFPR-8OO, manufactured by Tokyo Okako Co., Ltd., trade name OFPR-8OO) was applied at a film thickness of 2 μm, and ultraviolet rays were selectively irradiated and exposed using a desired photomask. The state obtained by developing this is FIG. PAD is an anodization pad (anode oxidation terminal) for applying a voltage during Al anodization. Of particular importance here is the intersection of the pattern edges of the Al pattern and the mask pattern for anodization. That is, as shown in Fig. 21, the angles θ ₁ and θ _{2 are set} to 135 °. After the post-baking by 120 degreeC and heat processing for 20 minutes, it carried out so that the liquid surface of the anodic-oxidizing liquid might be near the A-A 'line in a figure, and anodizing was performed. In the method of applying the voltage in the anodic oxidation, initially, the voltage was gradually increased to a current density of 50 µA / cm 2, and at a time when the voltage became 100 V, a constant voltage of 100 V was applied for 15 minutes to perform anodization. As a result, Al ₂ O ₃ having a thickness of about 140 nm could be grown on Al (12 ') in the liquid in which the photoresist was not placed. At this time, the anodic oxidation mask (photoresist PR) on Al (12 ') exhibited sufficient breakdown voltage and did not cause dielectric breakdown. In particular, defects due to dielectric breakdown of the pattern edge of the positive pole oxidation mask by the outer θ _1, θ _2, such as in, but not easy to cause a breakdown which the patterns forming the anodic oxidation mask, in this example to more than 90 ° (135 °) There was no occurrence of.

Example 10

A tenth embodiment of the present invention will be described with reference to FIGS. 25, 26, 27, and 28.

Here, an example in which the present technology is applied to a liquid crystal display using a TFT is shown.

FIG. 25 is a view schematically showing a part of a panel for driving a liquid crystal display using a thin film transistor.

T _{11 in the} same drawing is provided as a TFT for each pixel, and a video signal is supplied from the drain terminal D _N to be written to each pixel by this transistor. The video signal is supplied to the liquid crystal LC via the TFT of (T ₁₁ ) and represents a desired video for each pixel. Cad is an additional capacitance for holding the video signal longer, and 58, 55, and 56 are drain electrodes, source electrodes, and gate electrodes of the transistors, respectively. Denoted at 18 is a signal wiring for supplying the video signal supplied from the drain terminal D _N to each pixel, and G ' _N is a gate wiring (scanning line) for selecting a row for recording the signal. This gate wiring is connected to the gate terminal G _N.

In order to realize such a liquid crystal display panel, a gate electrode, a gate wiring, and a gate terminal are generally first formed on a glass substrate.

Here, an example in which the gate electrode, the gate wiring, and the gate terminal are formed of Al will be described.

Fig. 26 is a plan view showing an outline of the case where the gate wiring is performed in the display panel. Numeral 10 denotes a glass substrate, and numeral 40 denotes a device portion including a gate electrode and a gate wiring or a transistor or a pixel, and the TFT array portion in FIG. (G _N ) is the gate terminal. 41 connects the device portion 40 and the gate terminal _GN , adjusts the pitch of the row portion of the device portion and the pitch of the terminal portion, and forms a terminal block by arranging the number suitable for external connection by one block. It is a leader line.

An enlarged view of the vicinity of the leader line 41 is shown in FIG. 27. The same figure is shown in the state which rotated 90 degrees so that the said device part 40 of FIG. 26 may become downward. Due to the above reason, the lead-out portion is not equally spaced or equilibrated like the gate wiring and the gate terminal, and is usually diagonal as shown in FIG. 27, and the pattern often takes various directions depending on the place.

Incidentally, process cross-sectional views in this embodiment of the TFT portion, which form a particularly important and complicated structure among the device portions, are shown in Figs. 28 (a), (b), (c), (d) and (e). Fig. 28 (a) shows a gate electrode of TFT made of Al (12 ') having a thickness of 0.3 mu m.

Here, the device portion 40 of FIG. 26 is anodized, and as shown in FIG. 28, Al ₂ O ₃ (13) is grown on Al (12 '), and Al ₂ O ₃ is formed as a part of the gate insulating film. It is used for the insulating film of a wiring crossing part. Therefore, other than the terminal was made to oxidize. The part which bundles the terminal for this anodization is the anodization pad part 44 of FIG. There is also an anodization pad (PAD) for applying a voltage during anodization. In Fig. 27, PR is a positive photoresist of an anodization mask. Here, the film thickness of the photoresist was set to 3.5 µm. Of particular importance is the intersection of the pattern edges of the Al pattern and the mask pattern for the anodization in the portion that penetrates into the anodic oxidation solution. As described above, the lead line portion 41 has the Al pattern facing in various directions, so that the outer angle between the photoresist and the Al pattern in the anodic oxidation solution is in a straight line in the horizontal direction in FIG. 27. Is formed, the outer angle takes various angles, and becomes 40 ° to 140 °, for example. As described above, when the outer angle is various angles, especially when the mask photoresist is a positive type, the defect is likely to occur when the angle is 90 degrees or less. In the present embodiment, as shown in FIG. 27, the outer angles are all 135 degrees.

Next, after 140 degreeC and 30 minutes of postbaking processes, anodization was performed. Anodization was such that the surface of the anodic solution was near A-A 'in FIG. As the anodic oxidation solution, ammonia water was added to a 3% aqueous solution of tartaric acid, and after neutralization, propylene glycol was added 10 times by volume ratio. From the pad for anodization, a constant current of 30 mA / cm 2 was initially flowed, and after reaching 150 V, anodization was performed by applying a voltage for 20 minutes at a constant voltage. As a result, an Al ₂ O ₃ film could be grown 210 nm on Al. In the anodic oxidation here, since the outer angle θ was 135 ° and the postbaking was 140 ° C. for 30 minutes, there were no defects during oxidation. In this case, the structure of the transistor unit is shown in FIG. 28 (b).

Although the main part of this technology is above, the description for producing a liquid crystal display panel is briefly demonstrated using FIG. 28 (b), after sequentially depositing SiN 14, a-Si (i) 15 and a-Si (n) 16 by plasma CVD, as shown in FIG. 28 (c) -Si (n) (16) and a-Si (n) (15) were processed smaller than the gate electrode width. Next, as shown in Fig. 28 (d), Cr (11) serving as an electrode was deposited by vacuum deposition and processed into the shape of the source and drain electrodes.

In addition, in order to perform an electrode and wiring, Al (12kV) was deposited by the vacuum vapor deposition method, and it carried out like FIG. 28 (e). A transparent electrode (e.g., an ITO film), which is a pixel electrode, is formed, but it may be after this process or before the source and drain electrodes are formed (the transparent electrode is not shown in order to avoid complication here). Thus, the liquid crystal display panel TFT was produced. The gate insulating film of this transistor is composed of Al ₂ O ₃ and SiN by anodization described above. Since the gate insulating film is a two-layered gate insulating film, the structure is particularly excellent in insulation.

Example 11

An eleventh embodiment of the present invention will be described with reference to FIG. Also in this embodiment, anodization was performed assuming a liquid crystal display panel. 0.3 micrometer of Al (12 ') was deposited on the board | substrate 10, and Al (12') was processed similarly to Example 10. FIG. Also in this example, as in Example 10, a protective mask for selectively anodizing was formed between the anodized portion and the non-anodized portion. Here, as a mask, OFPR-800 (positive type resist) was set to 4 micrometers in thickness, and the outer shell of Al (12 ') and the resist pattern PR was set to 90 degrees in the intersection of any part. This was followed by postbaking at 130 ° C. for 30 minutes. Next, the surface of the anodic oxidation solution was made near A-A 'in the same plane, and a current was flowed from the anodic oxidation pad PAD at a current density of 80 nA / cm 2. Al ₂ O ₃ grows as the voltage gradually increases. When the voltage reached 140V, it was kept at this voltage for 20 minutes. After anodizing in this manner, the photoresist was removed. As a result, Al ₂ O ₃ with a film thickness of about 200 nm could be formed. In this anodic oxidation, the mask pattern shape of the photoresist was set to 90 ° at the intersection with any Al pattern, and the effect of Al in the anodic oxidation was sufficiently thickened to 4 mu m. There were no defects such as melting.

Example 12

A twelfth example will be described with reference to FIG. Also in this embodiment, anodization was performed assuming a liquid crystal display panel.

0.35 micrometer of Al (12 ') was deposited on the board | substrate 10, and Al (12') was processed like Example 10. FIG. Also in this example, as in Example 10, a photoresist PR was formed as a protective mask for selectively anodizing between the anodized portion and the non-anodized portion. Here, as a mask, OMR (negative-type resist) was made into 3 micrometers in film thickness, and the outer angle of Al and a resist pattern was set to 60 degrees also in the intersection of any part. In the negative type resist, when the pattern is formed by ultraviolet exposure, the resist is overlapped by the halation on the Al pattern edge, and the resist residue is generated. In order to remove this influence, in the present Example, the outer shell was 60 degrees. Then, post-baking was performed for 140 degreeC and 40 minutes.

Thereafter, the anodic oxidation liquid was made near A-A 'in the same drawing to flow a current at a current density of 100 nA / cm 2 from the anodization pad (PAD). Al ₂ O ₃ grows as the voltage gradually increases. When the voltage reached 200V, it was kept at this voltage for 20 minutes. After anodizing in this manner, the photoresist was removed. As a result, Al ₂ O ₃ having a film thickness of about 280 nm could be formed. In this anodization, since the mask pattern shape of the photoresist was set at 60 ° at the intersection with any Al pattern, the effect of halation on the Al pattern edge could be eliminated. There was no defect such as this.

Example 13

33 shows an embodiment of a liquid crystal display of the present invention. The apparatus includes a liquid crystal display panel 81, a video signal driver circuit 83 for providing a video signal to the liquid crystal display panel, a scanning circuit 84 for applying a scan signal to the liquid crystal display panel, And a control circuit 82 for imparting TFT information to the video signal driving circuit and the scanning circuit. The control circuit 82 includes a power supply circuit, a circuit for converting information into TFT information from an upper processing unit, and the like. When the liquid crystal display panels obtained in the above embodiments were incorporated into the apparatus, respectively, images with high reliability were obtained.

As shown in each of the above examples, the present invention significantly improved the reliability of the TFT substrate, improved the mutual conductivity gm by 25% to 50%, and improved the utilization of light by 20% or more. Moreover, the yield was largely improved at the time of its manufacture. In addition, wiring resistance could be lowered by locally anodizing Al. Moreover, the reliability of the liquid crystal display panel using this TFT substrate was remarkably improved. Moreover, the reliability of the liquid crystal display device using this liquid crystal display panel was also remarkably improved.

Claims (7)

Insulation board, A first wiring made of aluminum or a metal mainly composed of aluminum formed on the insulating substrate; A terminal made of a conductive film different from the first wiring, And a second wiring electrically connected to the first wiring and the terminal, The first wiring is partially covered by an insulating film made of aluminum oxide, The first wiring is exposed from the insulating film at least in a portion where the first wiring is connected to the terminal, And said second wiring covers a region exposed by said insulating film from said insulating film in said connection portion. The liquid crystal display device according to claim 1, wherein the terminal has a layer made of at least chromium or tantalum. The liquid crystal display of claim 1, wherein the second wiring is made of a transparent electrode. The liquid crystal display of claim 1, wherein the second wiring has a layer made of chromium. The liquid crystal display device according to claim 4, wherein the second wiring has a layer made of aluminum. The liquid crystal display device according to claim 1, wherein the second wiring is made of a transparent electrode, and the terminal is covered by the second wiring. 7. The liquid crystal display device according to claim 6, wherein the terminal has a layer made of at least chromium or tantalum.