KR20000043910A - Method for forming copper line of semiconductor device - Google Patents
Method for forming copper line of semiconductor device Download PDFInfo
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- KR20000043910A KR20000043910A KR1019980060348A KR19980060348A KR20000043910A KR 20000043910 A KR20000043910 A KR 20000043910A KR 1019980060348 A KR1019980060348 A KR 1019980060348A KR 19980060348 A KR19980060348 A KR 19980060348A KR 20000043910 A KR20000043910 A KR 20000043910A
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- Prior art keywords
- layer
- forming
- tantalum
- copper
- interlayer insulating
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 40
- 229910052802 copper Inorganic materials 0.000 title claims abstract description 40
- 239000010949 copper Substances 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000009792 diffusion process Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 9
- 238000007747 plating Methods 0.000 claims abstract description 6
- 239000000126 substance Substances 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 76
- 229910052715 tantalum Inorganic materials 0.000 claims description 36
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 34
- 239000011229 interlayer Substances 0.000 claims description 23
- 230000004888 barrier function Effects 0.000 claims description 18
- 238000010438 heat treatment Methods 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 4
- 238000005240 physical vapour deposition Methods 0.000 claims description 4
- 229910018557 Si O Inorganic materials 0.000 claims description 3
- 230000009977 dual effect Effects 0.000 claims description 3
- 238000007517 polishing process Methods 0.000 claims description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 3
- 238000009413 insulation Methods 0.000 abstract 4
- 238000005498 polishing Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 14
- 239000012790 adhesive layer Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VQANKOFXSBIWDC-UHFFFAOYSA-N [Si]=O.[Ta] Chemical compound [Si]=O.[Ta] VQANKOFXSBIWDC-UHFFFAOYSA-N 0.000 description 1
- MANYRMJQFFSZKJ-UHFFFAOYSA-N bis($l^{2}-silanylidene)tantalum Chemical compound [Si]=[Ta]=[Si] MANYRMJQFFSZKJ-UHFFFAOYSA-N 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052716 thallium Inorganic materials 0.000 description 1
- -1 thallium nitride Chemical class 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 더욱 상세히는 물리적 기상 증착 방법을 이용하여 탄탈륨(Ta) 박막을 증착하고 후속 열처리 공정중 Ta와 실리콘 옥사이드층 사이에 비정질층을 형성하여 확산 방지막으로 이용할 수 있는 반도체 소자의 구리 배선 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to deposit a tantalum (Ta) thin film by using a physical vapor deposition method and to form an amorphous layer between Ta and silicon oxide layer during the subsequent heat treatment process to be used as a diffusion barrier. It relates to a copper wiring formation method of a semiconductor device which can be.
현재, 반도체 소자의 금속 배선 형성 공정으로 저 저항 특성 및 EM(Electro- Migration) 특성이 우수한 구리 배선 형성 공정이 많이 연구되고 있다.Currently, many studies have been made on the formation of copper wirings having excellent low-resistance characteristics and electro-migration (EM) characteristics as metal wiring formation processes of semiconductor devices.
구리 배선 형성 공정에는 여러 가지 장점을 가지고 있는 반면, 실리콘이나 절연체인 실리콘 옥사이드층을 통한 뛰어난 확산 특성으로 인해 반도체 소자의 특성을 저해시키므로 구리 배선에서 확산 방지막 사용이 필요하며, 구리 확산을 막기 위한 확산 방지막으로 여러 가지 물질이 연구되어 왔다. 그중 Ta나 탈탈륨 나이트라이드(TaN) 박막층을 사용한 구리 확산 방지막에 대해서도 많은 실험 및 연구 결과가 있었고, 우수한 특성 등으로 인해 적용 가능성이 높아지고 있다.The copper wiring formation process has many advantages, but the excellent diffusion characteristics through the silicon or insulator silicon oxide layer impairs the characteristics of the semiconductor device, so it is necessary to use a diffusion barrier in the copper wiring, and to prevent copper diffusion. Various materials have been studied as barriers. Among them, there have been many experiments and research results on the copper diffusion barrier film using Ta or thallium nitride (TaN) thin film layer, and the applicability thereof is increasing due to excellent properties.
Ta나 TaN 층에 의해 구리 확산 방지막을 형성할 경우, Ta나 TaN 층이 비정질이나 비정질 같은 미세한 결정립계를 형성하기 때문에 구리의 확산을 어렵게 한다. 또한, 이러한 구조의 Ta나 TaN 층은 쉽게 다결정화(polycrystalline)되면서 결정립계 등을 통해 구리의 확산이 일어나게 되어, 구리 확산에 의한 반도체 특성이 크게 저하되게 되었다.When the copper diffusion barrier is formed by the Ta or TaN layer, the diffusion of copper is difficult because the Ta or TaN layer forms a fine grain boundary such as amorphous or amorphous. In addition, the Ta or TaN layer having such a structure is easily polycrystalline, and diffusion of copper occurs through grain boundaries, etc., thereby greatly deteriorating semiconductor characteristics due to copper diffusion.
따라서, 본 발명의 목적은 상기한 문제점을 해결하기 위해 탄탈륨층 증착후 열처리를 실시하여 비정질 확산층 및 탄탈륨 접착층을 동시에 형성하여 연속적인 씨앗 구리층의 증착이 가능하게 하므로서 공정의 단순화 및 우수한 확산 방지막을 형성할 수 있는 반도체 소자의 구리 배선 형성 방법을 제공하는데 있다.Accordingly, an object of the present invention is to simplify the process and to provide an excellent diffusion barrier layer by depositing a tantalum layer and heat treatment after deposition to simultaneously form an amorphous diffusion layer and a tantalum adhesive layer to solve the above problems. The present invention provides a method for forming a copper wiring of a semiconductor device that can be formed.
상기한 목적을 달성하기 위한 본 발명에 따른 반도체 구리 배선 형성 방법은 반도체 소자를 이루기 위한 여러 요소가 형성된 반도체 기판상에 금속 배선을 형성한 후, 상기 금속 배선상에 제 1 층간 절연막을 형성하는 단계와; 상기 제 1 층간 절연막에 콘택홀을 형성한 후, 상기 콘택홀의 일부를 포함하여 상기 제 1 층간 절연막에 트랜치를 형성하는 단계와; 상기 콘택홀 및 트랜치를 포함하는 기판상에 탄탈륨층을 형성하는 단계와; 상기 탄탈륨층이 형성된 기판에 열처리를 실시하고, 이로 인하여 상기 제 1 층간 절연막과 탄탈륨층의 접합면에 비정질층이 형성되고, 그 상부에 반응하지 않은 탄탈륨층이 잔류되는 단계와; 상기 반응하지 않은 탄탈륨층상에 씨드층을 형성한 후, 상기 콘택홀 및 트랜치가 충분히 매립되도록 구리 도금을 실시하는 단계와; 상기 콘택홀 및 트랜치에만 구리 도금이 매립되도록 상기 기판에 화학적 기계적 연마 공정을 실시한 후, 그 상부에 확산 방지막을 형성하고 제 2 층간 절연막을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.The method for forming a semiconductor copper wiring according to the present invention for achieving the above object comprises the steps of forming a metal wiring on a semiconductor substrate on which various elements for forming a semiconductor device are formed, and then forming a first interlayer insulating film on the metal wiring. Wow; Forming a contact hole in the first interlayer insulating film after forming a contact hole in the first interlayer insulating film; Forming a tantalum layer on the substrate including the contact hole and the trench; Heat-treating the substrate on which the tantalum layer is formed, whereby an amorphous layer is formed on the bonding surface of the first interlayer insulating film and the tantalum layer, and an unreacted tantalum layer remains on the upper surface; Forming a seed layer on the unreacted tantalum layer and performing copper plating so that the contact holes and trenches are sufficiently filled; And performing a chemical mechanical polishing process on the substrate such that only copper is embedded in the contact hole and the trench, and then forming a diffusion barrier layer and a second interlayer insulating layer thereon.
도 1(a) 내지 도 1(d)는 본 발명에 따른 반도체 소자의 구리 배선 형성 방법을 순차적으로 설명하기 위한 단면도.1 (a) to 1 (d) are cross-sectional views for sequentially explaining a method for forming a copper wiring of a semiconductor device according to the present invention.
〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>
11 : 반도체 기판 12 : 금속 배선11: semiconductor substrate 12: metal wiring
13 : 제 1 층간 절연막 14 : 콘택홀13 first interlayer insulating film 14 contact hole
15 : 트렌치 16 및 17 : 탄탈륨(Ta)층15 trench 16 and 17 tantalum (Ta) layer
18 : 비정질층 19 : 씨드층18: amorphous layer 19: seed layer
20 : 구리 배선 21 : 확산 방지막20: copper wiring 21: diffusion barrier
22 : 제 2 층간 절연막22: second interlayer insulating film
본 발명을 설명하기에 앞서 본 발명의 전반적인 기술적 원리를 설명한다.Before describing the present invention, the overall technical principle of the present invention will be described.
듀얼 다마신 등의 구리 배선 라인 및 콘택에 확산 방지막 형성을 위해 Ta 층을 증착한 후, 고 진공하에서 열처리하여 Ta 층과 절연체인 실리콘 옥사이드를 반응시켜 비정질의 탄탈 실리콘 옥사이드층을 형성하여 비정질 확산 방지막을 형성하고, 반응되지 않은 탄탈륨층은 구리 금속 배선의 공정시 접착층으로 사용한다.After depositing a Ta layer to form a diffusion barrier on copper wiring lines and contacts such as dual damascene, heat treatment under high vacuum to react the Ta layer and silicon oxide as an insulator to form an amorphous tantalum silicon oxide layer to form an amorphous diffusion barrier The unreacted tantalum layer is used as an adhesive layer in the process of copper metal wiring.
증착된 탄탈륨층은 고 진공 열처리하면 배선 라인이나 콘택의 절연 실리콘 옥사이드 등에 있는 산소 및 실리콘 원자들이 탄탈륨층 내로 확산하여 Ta, Si, O 등의 비정질층을 형성시킨다. 이러한 확산은 대략 250 ℃ 정도에서부터 발생되어 탄탈 실리사이드(TaSi2)가 형성되는 임계 온도인 600 ℃ 정도에서는 비정질층이 안정적으로 존재하게 된다.When the deposited tantalum layer is subjected to high vacuum heat treatment, oxygen and silicon atoms in an insulating silicon oxide of a wiring line or a contact diffuse into the tantalum layer to form an amorphous layer such as Ta, Si, O, or the like. Such diffusion occurs from about 250 ° C., and the amorphous layer is stably present at about 600 ° C., which is a critical temperature at which tantalum silicide (TaSi 2) is formed.
Ta, Si, O 등의 혼합된 비정질층 내에는 결정립계가 없으므로 결정립계를 통한 확산을 억제하여 확산 방지막 역할을 하게 된다. 열처리시 열처리 온도 및 시간에 의해 비정질 두께 등이 정해지며, Ta 층과 실리콘 옥사이드층의 계면에 형성되는 Ta-Si-O 층의 임계 두께는 대략 100 내지 150 Å 정도로서, 증착된 Ta 층의 두께를 조절하면 임계 두께의 비정질층과 반응하지 않는 Ta 층은 화학 기상 증착 방법 등에 의해 씨드층(seed layer)으로 구리층을 증착하기 위한 접착층으로 사용하므로서 연속적인 구리 배선 공정을 가능하게 하여 준다.Since there is no grain boundary in the mixed amorphous layer of Ta, Si, O, etc., it acts as a diffusion barrier by suppressing diffusion through the grain boundary. During the heat treatment, the amorphous thickness is determined by the heat treatment temperature and time, and the critical thickness of the Ta-Si-O layer formed at the interface between the Ta layer and the silicon oxide layer is about 100 to 150 GPa, and the thickness of the deposited Ta layer is increased. When controlled, the Ta layer, which does not react with an amorphous layer of critical thickness, is used as an adhesive layer for depositing a copper layer as a seed layer by a chemical vapor deposition method, thereby enabling a continuous copper wiring process.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1(a) 내지 도 1(d)는 본 발명에 따른 반도체 소자의 구리 배선 형성 방법을 순차적으로 설명하기 위한 단면도이다.1 (a) to 1 (d) are cross-sectional views for sequentially explaining a method for forming a copper wiring of a semiconductor device according to the present invention.
도 1(a)를 참조하여 설명하면, 반도체 소자를 이루기 위한 여러 요소가 형성된 반도체 기판(11)상에 금속 배선(12)을 형성한 후, 상기 금속 배선(12)상에 제1 층간 절연막(13)을 형성한다. 상기 금속 배선(12)이 노출되도록 상기 재 1 층간 절연막(13)의 선택된 영역을 식각하여 콘택홀(14)을 형성한 후, 상기 콘택홀(14)의 일부를 포함하는 제 1 층간 절연막(13)의 선택된 영역을 식각하여 트랜치(15)를 형성한다. 이후, 상기 콘택홀(14) 및 트랜치(15)를 포함하는 반도체 기판(11)상에 탄탈륨(Ta)층(16)을 형성한다.Referring to FIG. 1A, after the metal wiring 12 is formed on the semiconductor substrate 11 on which various elements for forming a semiconductor element are formed, a first interlayer insulating film (1) is formed on the metal wiring 12. 13). After etching the selected region of the first interlayer insulating layer 13 to expose the metal wiring 12 to form the contact hole 14, the first interlayer insulating layer 13 including a part of the contact hole 14. The trench 15 is formed by etching the selected region. Thereafter, a tantalum (Ta) layer 16 is formed on the semiconductor substrate 11 including the contact hole 14 and the trench 15.
상기 제 1 층간 절연막(13)은 절연체인 실리콘 옥사이드를 사용한다. 상기 콘택홀(14) 및 트랜치(15)는 듀얼 다마신 또는 싱글 다마신 방식으로 형성되는데, 트랜치(15)는 구리 배선 라인으로 사용된다. 상기 탄탈륨층(16)은 물리적 기상 증착 방법에 의해 200 내지 2000 Å 정도의 두께로 증착되어 형성된다.The first interlayer insulating layer 13 uses silicon oxide as an insulator. The contact hole 14 and the trench 15 are formed in a dual damascene or single damascene manner, and the trench 15 is used as a copper wiring line. The tantalum layer 16 is formed by being deposited to a thickness of about 200 to 2000 kPa by a physical vapor deposition method.
도 1(b)를 참조하여 설명하면, 상기 탄탈륨층(16)이 형성된 기판에 고 진공하에서 열처리를 실시하고, 이로 인하여 콘택홀(14) 및 트랜치(15) 내부의 탄탈륨층(16)이 제 1 층간 절연막(13)과 반응하여 비정질층(18)을 형성하고, 그 상부에 반응하지 않은 탄탈륨층(17)이 잔류된다.Referring to FIG. 1 (b), the substrate on which the tantalum layer 16 is formed is subjected to heat treatment under high vacuum, and thus the tantalum layer 16 inside the contact hole 14 and the trench 15 is removed. Reacts with the interlayer insulating film 13 to form an amorphous layer 18, and an unreacted tantalum layer 17 remains thereon.
상기 비정질층(18)은 제 1 층간 절연막(13)인 실리콘 옥사이드와 탄탈륨이 반응하여 Ta-Si-O 층으로 형성되어 확산 방지막으로 사용되는데, 100 내지 150 Å의 두께로 형성된다. 이때, 비정질층(18)은 탄탈륨(Ta), 실리콘(Si), 산소(O) 및 질소(N) 등으로도 형성할 수 있다. 상기 반응하지 않은 탄탈륨층(17)은 50 내지 500 Å 정도의 두께로 조절되며, 접착층으로 사용된다.The amorphous layer 18 is formed as a Ta-Si-O layer by reacting silicon oxide, which is the first interlayer insulating layer 13, and tantalum, and is used as a diffusion barrier, and has a thickness of 100 to 150 kPa. In this case, the amorphous layer 18 may also be formed of tantalum (Ta), silicon (Si), oxygen (O), nitrogen (N), or the like. The unreacted tantalum layer 17 is adjusted to a thickness of about 50 to 500 kPa, and used as an adhesive layer.
상기에서, 열처리는 300 내지 500 ℃ 정도로 실시되는데, 탄탈륨을 증착하는 중에 히터에 의해 기판을 승온시키므로서 수행할 수 있고, 또한 탄탈륨을 증착한 후 고 진공하에서 램프(lamp) 등에 의한 복사열에 의해 수행되거나, 히터에 의해 열처리를 실시하며, 이때 열전달은 고순도의 불활성 기체에 의해 균일하게 열을 전달되도록 한다.In the above, the heat treatment is carried out about 300 to 500 ℃, can be carried out by heating the substrate by the heater during the deposition of tantalum, and also by radiation heat by lamp or the like under high vacuum after the deposition of tantalum Alternatively, the heat treatment may be performed by a heater, in which heat transfer allows heat to be uniformly transferred by an inert gas of high purity.
도 1(c)를 참조하여 설명하면, 상기 반응하지 않은 탄탈륨층(17) 상에 씨드층(19)을 형성한 후, 상기 콘택홀(14) 및 트랜치(15)가 충분히 매립되도록 상기 씨드층(19)상을 포함하는 전체 구조상에 연속적으로 진공 파괴없이 구리 도금(20)을 실시한다.Referring to FIG. 1C, after forming the seed layer 19 on the unreacted tantalum layer 17, the seed layer is sufficiently filled with the contact hole 14 and the trench 15. Copper plating 20 is continuously performed on the whole structure including phase (19) without vacuum breaking.
상기 씨드층(19)은 100 내지 2000 Å 정도의 구리를 증착하여 형성되는데, 이는 물리적 또는 화학적 기상 증착 방법을 통해 형성 된다.The seed layer 19 is formed by depositing about 100 to 2000 kPa of copper, which is formed by a physical or chemical vapor deposition method.
도 1(d)를 참조하여 설명하면, 상기 콘택홀(14) 및 트랜치(15)에만 구리 도금(20)이 매립되도록 하기 위해, 상기 구리 도금(20)이 증착된 기판에 화학적 기계적 연마 공정을 통해 제 1 층간 절연막(13)상의 씨드층(19), 탄탈륨층(17) 및 비정질층(18)을 제거하여 평탄화를 이루어 구리 배선 공정을 완료한 후, 그 상부에 확산 방지막(21)으로 탄탈륨이나 탄탈륨 나이트라이드를 증착한다. 상기 확산 방지막(21)을 포함하는 제 1 층간 절연막(13)상에 제 2 층간 절연막(22)을 형성한다.Referring to FIG. 1 (d), a chemical mechanical polishing process is performed on a substrate on which the copper plating 20 is deposited so that the copper plating 20 is embedded only in the contact hole 14 and the trench 15. After the seed layer 19, the tantalum layer 17, and the amorphous layer 18 on the first interlayer insulating layer 13 are removed and planarized, the copper wiring process is completed, and then tantalum is used as the diffusion barrier 21 thereon. Or tantalum nitride is deposited. A second interlayer insulating film 22 is formed on the first interlayer insulating film 13 including the diffusion barrier film 21.
상술한 바와 같이, 본 발명에 의하면 다층 박막 및 열 공정 등의 복잡한 공정상의 여러 절차로 형성된 종래의 확산 방지막의 문제점을 해결하기 위해 하나의 층만 증착한 후, 열 공정을 통해 비정질 확산 방지막 및 구리 배선의 접착층 역할을 하게 하므로서 공정의 단순화 및 우수한 확산 방지막 특성을 추구하는데 탁월한효과가 있다.As described above, according to the present invention, in order to solve the problem of the conventional diffusion barrier film formed by various procedures in complex processes such as multilayer thin film and thermal process, only one layer is deposited, and then the amorphous diffusion barrier film and the copper wiring through the thermal process. By acting as an adhesive layer of the has an excellent effect in simplifying the process and pursuing excellent diffusion barrier properties.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020032698A (en) * | 2000-10-26 | 2002-05-04 | 박종섭 | Method of forming a copper wiring in a semiconductor device |
| KR20020092002A (en) * | 2001-06-01 | 2002-12-11 | 주식회사 하이닉스반도체 | Method for Forming Cu lines in Semiconductor Device |
| KR100462762B1 (en) * | 2002-06-18 | 2004-12-20 | 동부전자 주식회사 | Method for forming copper metal line of semiconductor device |
| KR100508422B1 (en) * | 2001-01-22 | 2005-08-18 | 아넬바 가부시기가이샤 | A method for the formation of copper wiring films |
| KR100528530B1 (en) * | 2000-12-20 | 2005-11-15 | 매그나칩 반도체 유한회사 | Method for forming a metal layer of a semiconductor device |
| KR100725710B1 (en) * | 2005-12-29 | 2007-06-07 | 동부일렉트로닉스 주식회사 | Formation method of thin layer |
| KR100727256B1 (en) * | 2005-12-29 | 2007-06-11 | 동부일렉트로닉스 주식회사 | Formation method of thin layer |
| KR100727258B1 (en) * | 2005-12-29 | 2007-06-11 | 동부일렉트로닉스 주식회사 | Fabricating method of thin film and metal line in semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0148325B1 (en) * | 1995-03-04 | 1998-12-01 | 김주용 | Formation method of metal layer in semiconductor device |
| KR970052324A (en) * | 1995-12-22 | 1997-07-29 | 김주용 | Method of reducing contact resistance of semiconductor device |
| JP3353874B2 (en) * | 1996-09-24 | 2002-12-03 | シャープ株式会社 | Semiconductor device and manufacturing method thereof |
| KR100430684B1 (en) * | 1996-12-31 | 2004-07-30 | 주식회사 하이닉스반도체 | Method of forming thermally stable metal line of semiconductor device using doubly or triply deposited amorphous and crystalline tungsten nitride layer |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020032698A (en) * | 2000-10-26 | 2002-05-04 | 박종섭 | Method of forming a copper wiring in a semiconductor device |
| KR100528530B1 (en) * | 2000-12-20 | 2005-11-15 | 매그나칩 반도체 유한회사 | Method for forming a metal layer of a semiconductor device |
| KR100508422B1 (en) * | 2001-01-22 | 2005-08-18 | 아넬바 가부시기가이샤 | A method for the formation of copper wiring films |
| KR20020092002A (en) * | 2001-06-01 | 2002-12-11 | 주식회사 하이닉스반도체 | Method for Forming Cu lines in Semiconductor Device |
| KR100462762B1 (en) * | 2002-06-18 | 2004-12-20 | 동부전자 주식회사 | Method for forming copper metal line of semiconductor device |
| KR100725710B1 (en) * | 2005-12-29 | 2007-06-07 | 동부일렉트로닉스 주식회사 | Formation method of thin layer |
| KR100727256B1 (en) * | 2005-12-29 | 2007-06-11 | 동부일렉트로닉스 주식회사 | Formation method of thin layer |
| KR100727258B1 (en) * | 2005-12-29 | 2007-06-11 | 동부일렉트로닉스 주식회사 | Fabricating method of thin film and metal line in semiconductor device |
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