KR20000043832A - Fuse structure of semiconductor memory - Google Patents
Fuse structure of semiconductor memory Download PDFInfo
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- KR20000043832A KR20000043832A KR1019980060256A KR19980060256A KR20000043832A KR 20000043832 A KR20000043832 A KR 20000043832A KR 1019980060256 A KR1019980060256 A KR 1019980060256A KR 19980060256 A KR19980060256 A KR 19980060256A KR 20000043832 A KR20000043832 A KR 20000043832A
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- fuse structure
- active regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
Abstract
Description
본 발명은 반도체 메모리의 퓨즈 구조에 관한 것으로, 특히 게이트산화막에 파괴전압(break down voltage)을 인가함에 따라 게이트와 액티브가 도통되는 것을 이용한 퓨즈연결을 통해 리던던시 셀(redundancy cell)로의 대체가 가능하도록 한 반도체 메모리의 퓨즈 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fuse structure of a semiconductor memory, and in particular, to replace a redundancy cell through a fuse connection using conduction between a gate and an active layer when a breakdown voltage is applied to the gate oxide layer. It relates to a fuse structure of a semiconductor memory.
일반적으로, 반도체 메모리는 주 메모리셀과 그 주 메모리셀에 이상이 발생한 경우, 이를 대체하기 위한 리던던시 셀을 함께 포함하며, 메모리를 제조한 후 테스트를 통해 각 주 메모리셀의 이상여부를 판정하여 이상이 있는 메모리셀은 퓨즈 커팅에 의해 리던던시 셀로 경로를 변경하여 이후에 상기 이상이 있는 메모리셀을 억세스하는 어드레스신호가 인가되는 경우, 오류가 없는 리던던시 셀을 선택하도록 하며, 상기와 같이 경로 변환의 역할을 하는 종래의 반도체 메모리의 퓨즈 구조를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In general, a semiconductor memory includes a redundancy cell for replacing a main memory cell and a main memory cell when an abnormality occurs, and after manufacturing the memory, determine whether the main memory cell is abnormal through a test. This memory cell changes the path to the redundancy cell by fuse cutting so that when an address signal for accessing the abnormal memory cell is subsequently applied, the redundancy cell without error is selected. Hereinafter, a fuse structure of a conventional semiconductor memory is described in detail with reference to the accompanying drawings.
먼저, 도1a는 종래 반도체 메모리의 퓨즈 구조를 보인 평면도로서, 이에 도시한 바와같이 반도체 웨이퍼 상에 퓨즈부(1)를 보호하기 위하여 형성되는 가드링(guard ring : 2)과; 상기 퓨즈부(1) 내에 소정거리씩 이격 형성되는 다수개의 퓨즈(3A∼3C)와; 외부 대체회로에 접속되어 상기 퓨즈(3A∼3C)의 양측 가장자리에 각각 콘택(4)을 통해 접속되는 배선(5)으로 구성된다.First, FIG. 1A is a plan view showing a fuse structure of a conventional semiconductor memory, and as shown therein, a guard ring 2 formed on a semiconductor wafer to protect the fuse unit 1; A plurality of fuses 3A to 3C formed in the fuse unit 1 by a predetermined distance; A wiring 5 connected to an external replacement circuit and connected to both edges of the fuses 3A to 3C via a contact 4, respectively.
그리고, 도1b는 상기 도1a의 X-X선 단면도로서, 이에 도시한 바와같이 반도체소자가 형성된 기판(11)에 가드링(2)이 형성되고, 상기 가드링(2) 내에 퓨즈(3A)가 형성되며, 상기 퓨즈(3A)의 상부에 층간절연막(12)을 형성한 후, 퓨즈(3A)의 양측 가장자리를 식각하여 도전성물질을 채움으로써, 콘택(4)을 형성한 다음 그 콘택(4)과 각각 접속되는 배선(5)이 형성되어 구성된다.1B is a cross-sectional view taken along the line XX of FIG. 1A, and as shown therein, a guard ring 2 is formed on a substrate 11 on which a semiconductor element is formed, and a fuse 3A is formed in the guard ring 2. After the interlayer insulating film 12 is formed on the fuse 3A, the edges of both sides of the fuse 3A are etched to fill the conductive material, thereby forming the contact 4 and then forming the contact 4. The wirings 5 connected to each other are formed and configured.
상기한 바와같은 반도체 메모리의 퓨즈는 초기에 모든 퓨즈가 턴온상태에서 레이저빔을 통해 턴오프되어 컷팅이 이루어지며, 레이저빔이 조사되면 퓨즈(3A)가 미설명부호 '10'으로 도시한 바와같이 컷팅된다.The fuse of the semiconductor memory as described above is initially turned off through the laser beam when all the fuses are turned on to be cut. When the laser beam is irradiated, the fuse 3A is shown by the reference numeral '10'. Is cut.
그러나, 상기한 바와같은 종래 반도체 메모리의 퓨즈 구조는 레이저빔에 의한 퓨즈의 컷팅을 이용함에 따라 도1a에 도시한 바와같이 레이저빔의 사이즈(10:약 6㎛)에 적당하도록 퓨즈간의 이격거리를 확보해야 되며, 아울러 퓨즈부의 보호를 위한 가드링이 필요하므로, 전체적으로 칩면적이 증가되는 문제점과 아울러 레이저빔에 의한 퓨즈부의 물리적 손상이 큰 문제점이 있었다.However, the fuse structure of the conventional semiconductor memory as described above uses the cutting of the fuse by the laser beam, and as shown in Fig. 1A, the separation distance between the fuses is appropriate to the size of the laser beam (10: about 6 mu m). In addition, since the guard ring for protecting the fuse part is required, the chip area is increased as a whole, and there is a big problem of physical damage to the fuse part by the laser beam.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 게이트산화막에 파괴전압을 인가함에 따라 게이트와 액티브가 도통되는 것을 이용한 퓨즈연결을 통해 리던던시 셀로의 대체가 가능하도록 한 반도체 메모리의 퓨즈 구조를 제공하는데 있다.The present invention has been devised to solve the above-mentioned problems, and an object of the present invention is to replace the redundancy cell through a fuse connection using the conductive conduction of the gate as the breakdown voltage is applied to the gate oxide film. It is to provide a fuse structure of a semiconductor memory.
도1a은 종래 반도체 메모리의 퓨즈 구조를 보인 평면도.1A is a plan view showing a fuse structure of a conventional semiconductor memory.
도1b는 도1a의 X-X선 단면도.FIG. 1B is a cross-sectional view taken along the line X-X of FIG. 1A. FIG.
도2a는 본 발명의 일 실시예를 보인 평면도.Figure 2a is a plan view showing an embodiment of the present invention.
도2b는 도2a의 Y-Y선 단면도.FIG. 2B is a cross-sectional view taken along the line Y-Y in FIG. 2A. FIG.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
21:필드영역 22A∼22C:액티브영역21: field area 22A to 22C: active area
23A∼23C:게이트 24,26,27:배선23A to 23C: Gates 24, 26 and 27: Wiring
25:전압인가패드25: Voltage application pad
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체 메모리의 퓨즈 구조는 반도체기판 상에 필드영역을 통해 각각 격리되어 형성된 다수의 액티브영역과; 상기 각각의 액티브영역과 필드영역을 일부분 공유하여 형성된 다수의 게이트와; 상기 각각의 게이트에 선택적으로 게이트산화막 파괴전압을 인가하는 전압인가패드와; 상기 다수의 게이트를 외부 대체회로에 접속시키는 제1배선과; 상기 다수의 액티브영역을 접지시키는 제2배선을 포함하여 이루어지는 것을 특징으로 한다.The fuse structure of the semiconductor memory for achieving the object of the present invention as described above comprises a plurality of active regions formed on the semiconductor substrate to be isolated from each other through the field region; A plurality of gates formed by partially sharing each of the active regions and the field regions; A voltage application pad for selectively applying a gate oxide breakdown voltage to each of the gates; A first wiring connecting the plurality of gates to an external replacement circuit; And a second wiring for grounding the plurality of active regions.
상기한 바와같은 본 발명에 의한 반도체 메모리의 퓨즈 구조를 첨부한 도면을 일 실시예로 하여 상세히 설명하면 다음과 같다.Referring to the accompanying drawings of the fuse structure of the semiconductor memory according to the present invention as described above in detail as an embodiment as follows.
먼저, 도2a는 본 발명의 일 실시예를 보인 평면도로서, 이에 도시한 바와같이 반도체기판 상에 필드영역(21)을 통해 각각 격리되어 형성된 액티브영역(22A∼22C)과; 상기 각각의 액티브영역(22A∼22C)과 필드영역(21)을 일부분 공유하여 형성된 게이트(23A∼23C)와; 상기 각각의 게이트(23A∼23C)에 배선(24)을 통해 선택적으로 게이트산화막 파괴전압을 인가하는 전압인가패드(25)와; 상기 게이트(23A∼23C)를 외부 대체회로에 접속시키는 배선(26)과; 상기 액티브영역(22A∼22C)을 접지시키는 배선(27)으로 이루어진다. 이때, 상기 액티브영역(22A∼22C)은 통상의 반도체 제조공정 중의 웰과 동일한 도핑영역이 형성되며, 상기 액티브영역(22A∼22C)과 필드영역(21)을 일부분 공유하도록 게이트(23A∼23C)를 형성하는 이유는 게이트(23A∼23C)가 액티브영역(22A∼22C) 상에만 형성되는 것에 비해 게이트산화막 파괴전압이 낮기 때문이다.First, Fig. 2A is a plan view showing an embodiment of the present invention, and as shown therein, active regions 22A to 22C formed on the semiconductor substrate through the field regions 21, respectively; Gates 23A to 23C formed by partially sharing each of the active regions 22A to 22C and the field regions 21; A voltage application pad (25) for selectively applying a gate oxide film breakdown voltage to each of the gates (23A to 23C) through a wiring (24); Wiring (26) connecting the gates (23A to 23C) to an external replacement circuit; A wiring 27 for grounding the active regions 22A to 22C. At this time, the active regions 22A to 22C are formed with the same doped regions as the wells in a conventional semiconductor manufacturing process, and the gates 23A to 23C are partially shared with the active regions 22A to 22C. The reason for forming is because the gate oxide film breakdown voltage is lower than the gates 23A to 23C are formed only on the active regions 22A to 22C.
그리고, 도2b는 도2a의 Y-Y선 단면도로서, 이에 도시한 바와같이 반도체기판(31) 상에 필드영역(21) 및 액티브영역(22C)을 형성하고, 상기 필드영역(21)과 액티브영역(22C)을 일부분 공유하도록 게이트(23C)를 형성한 다음 게이트(23C)와 전압인가패드(미도시)를 접속시키는 배선(24) 및 게이트(23C)와 외부 대체회로를 접속시키는 배선(26)을 형성하고, 상기 액티브영역(22C)을 접지시키는 배선(27)을 형성하여 이루어진다.2B is a cross-sectional view taken along the line YY of FIG. 2A. As shown therein, a field region 21 and an active region 22C are formed on the semiconductor substrate 31, and the field region 21 and the active region ( The gate 23C is formed to partially share the 22C, and then the wiring 24 connecting the gate 23C and the voltage application pad (not shown) and the wiring 26 connecting the gate 23C and the external replacement circuit are provided. And a wiring 27 for grounding the active region 22C.
상기한 바와같은 본 발명에 의한 퓨즈 구조는 초기에 모든 퓨즈가 턴오프 상태에서 게이트산화막 파괴전압에 의해 게이트(23A∼23C)와 액티브영역(22A∼22C)이 선택적으로 턴온되어 퓨즈연결이 이루어진다.In the fuse structure according to the present invention as described above, the gates 23A to 23C and the active regions 22A to 22C are selectively turned on by the gate oxide breakdown voltage in a state where all the fuses are initially turned off, thereby making a fuse connection.
상기한 바와같은 본 발명에 의한 반도체 메모리의 퓨즈 구조는 레이저빔의 사이즈를 고려할 필요가 없으며 가드링을 형성할 필요가 없으므로, 퓨즈부의 면적을 감소시킴과 아울러 보호막을 증착하고 퓨즈부를 오픈시킴에 따른 신뢰성저하를 방지할 수 있고, 레이저빔에 의한 퓨즈부의 물리적인 손상을 차단할 수 있는 효과가 있다.As described above, the fuse structure of the semiconductor memory according to the present invention does not need to consider the size of the laser beam and does not need to form the guard ring, thereby reducing the area of the fuse and depositing a protective film and opening the fuse. Reliability can be prevented, and physical damage to the fuse part by the laser beam can be prevented.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980060256A KR20000043832A (en) | 1998-12-29 | 1998-12-29 | Fuse structure of semiconductor memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980060256A KR20000043832A (en) | 1998-12-29 | 1998-12-29 | Fuse structure of semiconductor memory |
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| KR20000043832A true KR20000043832A (en) | 2000-07-15 |
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| KR1019980060256A KR20000043832A (en) | 1998-12-29 | 1998-12-29 | Fuse structure of semiconductor memory |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100557630B1 (en) * | 2002-07-18 | 2006-03-10 | 주식회사 하이닉스반도체 | Forming method for fuse of semiconductor device |
| KR20110090064A (en) * | 2010-02-02 | 2011-08-10 | 삼성전자주식회사 | Semiconductor chip and semiconductor module having the same |
| WO2023236268A1 (en) * | 2022-06-10 | 2023-12-14 | 长鑫存储技术有限公司 | Bit breakdown condition determining method and device |
-
1998
- 1998-12-29 KR KR1019980060256A patent/KR20000043832A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100557630B1 (en) * | 2002-07-18 | 2006-03-10 | 주식회사 하이닉스반도체 | Forming method for fuse of semiconductor device |
| KR20110090064A (en) * | 2010-02-02 | 2011-08-10 | 삼성전자주식회사 | Semiconductor chip and semiconductor module having the same |
| WO2023236268A1 (en) * | 2022-06-10 | 2023-12-14 | 长鑫存储技术有限公司 | Bit breakdown condition determining method and device |
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| Date | Code | Title | Description |
|---|---|---|---|
| N231 | Notification of change of applicant | ||
| WITN | Withdrawal due to no request for examination |