KR20010017201A - Semiconductor device having fuse cutting by laser beam - Google Patents

Abstract

PURPOSE: A semiconductor device having fuse cut by laser beam is provided to minimize the damage influenced on adjacent gate electrode patterns by the influence of a laser beam in cutting a fuse CONSTITUTION: The semiconductor device having fuse cut by laser beam comprises plural gate electrode patterns(110), a fuse(150), an insulation layer(130) and a dummy gate electrode pattern(120). The gate electrode patterns(110) are formed on a semiconductor substrate(100). The fuse(150) electrically connects at least two gate electrode patterns(110) and insulates the patterns through a cutting process due to a laser beam. The insulation layer(130) is formed on the fuse to define a fuse box portion to be exposed by the laser beam. The dummy gate electrode pattern(120) is formed a conductor as same as the gate electrode pattern and disposed between the fuse box portion and the gate electrode pattern.

Description

Semiconductor device having fuse cutting by laser beam

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor device in which damage to adjacent gate electrode patterns is minimized when fuses are cut using a laser beam.

In semiconductor devices, fuses are commonly used to repair memory cells through repair, and replacing a defective cell with a redundancy cell is a redundancy decoder corresponding to an address of a main cell to be replaced. ) Is cut by using a technique such as a laser beam.

As semiconductor memory devices become more integrated, they require a larger number of redundancy cells and a larger number of fuses to repair them. As a result, the gaps, widths, and the like of the fuses are further narrowed, and a more precise manufacturing process is required. This means that fuses with fine spacing must be accurately aligned to cut the fuses corresponding to the defective cells.

1A is a plan view illustrating a conventional fuse box fb, and FIG. 1B is a cross-sectional view taken along line AA ′ of FIG. 1A. 1A and 1B, reference numeral 10 denotes a semiconductor substrate, 12 denotes a gate electrode pattern, 15 denotes a bit line conductive layer, 16 denotes a contact, and 18 denotes a fuse. For example, "20" represents a first insulating layer, "22" represents a second insulating layer, and "fb" represents a fuse box, respectively.

1A and 1B, gate electrode patterns 12 are formed on a semiconductor substrate 10, and two gate electrode patterns 12 are electrically connected through a contact 16 and a fuse 18. Connected. These gate electrode patterns 12 are electrically insulated through a cutting process of the fuse 18 using a laser beam.

In this cutting process, as mentioned, it is necessary to accurately align the fuses with fine spacing. However, when some misalignment occurs or when excessive energy is used, the active area located below the fuse box fb may be damaged. That is, the energy of the laser beam for cutting the fuse is transferred to the active region, resulting in damage such as crystal defects in the adjacent gate electrode pattern 12 or the substrate 10 and, in severe cases, destruction of the adjacent gate electrode pattern 12. Done. These damages are more serious as semiconductor devices become more integrated and closer to fuses and surrounding circuits, which not only have a devastating effect on the electrical characteristics of the device, but also become a fundamental cause of failure in reliability tests such as moisture penetration. have.

An object of the present invention is to provide a semiconductor device with minimal damage to adjacent gate electrode patterns during fuse cutting.

Figure 1a is a plan view showing a conventional fuse box.

FIG. 1B is a cross-sectional view taken along line AA ′ of FIG. 1A.

2A is a layout diagram of a fuse according to a first embodiment of the present invention.

FIG. 2B is a cross-sectional view taken along line BB ′ of FIG. 2A.

3A is a layout diagram of a fuse according to a second embodiment of the present invention.

3B is a cross-sectional view taken along the line CC ′ of FIG. 3A.

In accordance with another aspect of the present invention, a semiconductor device includes a plurality of gate electrode patterns formed on a semiconductor substrate, and a plurality of gate electrode patterns formed on the gate electrode pattern to electrically connect at least two gate electrode patterns among the plurality of gate electrode patterns. A fuse which electrically connects the circuit board, and electrically insulates them through a cutting process by a laser beam, an insulating layer formed on the fuse to define a portion of a fuse box to be exposed by a laser beam for cutting the fuse; And a dummy gate electrode pattern formed of the same conductive layer as the gate electrode pattern and formed between the fuse box portion and the gate electrode pattern.

The dummy gate electrode pattern may be maintained at a constant voltage level such as Vss, Vcc, and Vbb. In addition to the dummy gate electrode pattern, a dummy metal pattern formed on the fuse to be electrically insulated from the fuse, and formed between the fuse box portion and the gate electrode pattern, the dummy gate electrode pattern and the dummy metal. A dummy contact may be further provided to electrically connect the pattern.

According to the present invention, the laser beam affects the dummy gate electrode patterns located closer to the fuse box, even if a misalignment occurs or excessive energy is used to damage the adjacent gate electrode patterns. Crazy As a result, damage or destruction of the gate electrode pattern due to the energy of the laser beam is minimized.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various forms, and only the embodiments of the present invention may be completed by the present invention to those skilled in the art. It is provided to fully inform the category. In the embodiments disclosed below, when either film is referred to as being on another film or substrate, it is noted that it may be directly over the other film or substrate and an interlayer film may be present.

2A is a layout diagram of a fuse according to a first embodiment of the present invention, and FIG. 2B is a cross-sectional view taken along line BB ′ of FIG. 2A. 2A and 2B, reference numeral 100 denotes a semiconductor substrate, 110 denotes a gate electrode pattern, 120 denotes a dummy gate electrode pattern, 130 denotes an interlayer insulating layer, and 135 denotes an interlayer insulating layer. Is a bit line conductive layer, "140" is a contact, "150" is a fuse, "160" is a first insulating layer, "170" is a second insulating layer, and "fb1" is a fuse box. .

First, referring to FIG. 2B, the cross-sectional structure of the semiconductor device according to the first exemplary embodiment of the present invention is described. The gate electrode pattern 110 and the dummy gate electrode pattern 120 are formed on the semiconductor substrate 100. The interlayer insulating layer 130 is formed on the gate electrode pattern 110 and the dummy gate electrode pattern 120. A fuse 150 is formed on the interlayer insulating layer 130, and the fuse 150 is electrically connected to the gate electrode pattern 110 through the contact 140. The first insulating layer 160 and the second insulating layer 170 are formed on the fuse 150, and the portion of the first insulating layer 160 exposed by removing the second insulating layer 170 is lasered. It corresponds to the fuse box fb1 to be cut by the beam.

Here, the dummy gate electrode pattern 120 may be formed of the same conductive layer when the gate electrode pattern 110 is formed. The dummy gate electrode pattern 120 is formed to minimize damage of the gate electrode pattern 110 and does not affect the operation of the device. The dummy gate electrode pattern 120 may be maintained at a constant voltage level such as Vss, Vcc, and Vbb.

Meanwhile, the fuse 150 may be formed of the same conductive layer when the bit line conductive layer 135 is formed, and the contact 140 is formed when the contact connecting the bit line and the drain is formed in the memory cell array. It is preferable.

As shown in FIG. 2A, the dummy gate electrode pattern 120 surrounds the fuse box fb1, and the fuse box fb1 and the gate electrode pattern 110 are viewed from a layout side. It is formed between.

As described above, according to the first exemplary embodiment of the present invention, the dummy gate electrode pattern 120 is formed outside the fuse box fb1 exposed to the laser beam. In particular, the dummy gate electrode pattern 120 is formed closer to the fuse box fb1 than to the gate electrode pattern 110. As a result, when the fuse is cut, even if a misalignment occurs or excessive energy is used to damage the adjacent gate electrode pattern, the laser beam is located closer to the fuse box fb1. Affects.

Therefore, the energy of the laser beam transmitted directly to the gate electrode pattern 110 can be minimized. As mentioned above, since the dummy gate electrode pattern 120 does not affect the operation of the device, the dummy gate electrode pattern 120 does not affect the operation of the device even if it is damaged by the laser beam energy. As a result, the aforementioned conventional problem, that is, damage or destruction of the gate electrode pattern due to the energy of the laser beam is minimized.

3A is a layout diagram of a fuse according to a second embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along line CC ′ of FIG. 3A. 3A and 3B, reference numeral 200 denotes a semiconductor substrate, 210 denotes a gate electrode pattern, 220 denotes a dummy gate electrode pattern, 230 denotes an interlayer insulating layer, and 240. Silver contact, "245" for bit line conductive layer, "250" for fuses, "260" for dummy contact, "270" for dummy metal pattern, "280" for first insulating layer, "290" Represents a second insulating layer, and " fb2 " represents a fuse box, respectively.

The second embodiment of the present invention is the same as the first embodiment except that the dummy metal pattern 270 connected through the dummy contact 260 is formed on the dummy gate electrode pattern.

Referring to FIG. 3B, the cross-sectional structure of the semiconductor device according to the second embodiment of the present invention will be described. Similarly to the first embodiment, the gate electrode pattern 210 and the dummy gate electrode pattern on the semiconductor substrate 200 will be described. 220 is formed, and an interlayer insulating layer 230 is formed on the gate electrode pattern 210 and the dummy gate electrode pattern 220. A fuse 250 is formed on the interlayer insulating layer 230, and the fuse 250 is electrically connected to the gate electrode pattern 210 through the contact 240. A first insulating layer 280 and a second insulating layer 290 are formed on the fuse 250, and the dummy gate electrode pattern 220 is formed in the second insulating layer 290 through a dummy contact 260. ) And a dummy metal pattern 270 electrically connected thereto. As in the first embodiment, the portion of the second insulating layer 290 removed to expose the first insulating layer 280 corresponds to the fuse box fb2 to be cut by the laser beam.

The dummy gate electrode pattern 220 may be formed of the same conductive layer when the gate electrode pattern 210 is formed, and the fuse 250 may be the same conductive layer when the bit line conductive layer 245 is formed. It is preferably formed. In addition, the contact 240 may be formed when forming a contact connecting a bit line and a drain in a memory cell array, and the dummy metal pattern may be formed of the same conductive layer when forming a wiring layer.

Unlike the first embodiment, in addition to the dummy gate electrode pattern 220, a dummy contact 260 and a dummy metal pattern 270 are further formed. Like the dummy gate electrode pattern 220, the dummy contact 270 or the dummy metal pattern 270 is formed to minimize damage of the gate electrode pattern 210. In addition, the dummy metal pattern 270 is preferably floated so as not to affect the operation of the device.

The dummy gate electrode pattern 220 and the dummy metal pattern 270 surround the fuse box fb2, as shown in FIG. 3A. The layout of the dummy gate electrode pattern 220 and the dummy metal pattern 270 is similar to that of the fuse box fb2. It is formed between the gate electrode pattern 210. Preferably, the dummy gate electrode pattern 220 and the dummy metal pattern 270 are formed in the same pattern. The dummy gate electrode pattern 220 may also be maintained at a constant voltage level such as Vss, Vcc, and Vbb.

As described above, according to the second exemplary embodiment of the present invention, the dummy gate electrode pattern 220 and the dummy metal pattern 270 are formed on the outer side of the fuse box fb2 exposed to the laser beam. The dummy gate electrode pattern 220, the dummy contact 260, and the dummy metal pattern 270 are formed closer to the fuse box fb2 than the gate electrode pattern 210. As a result, when the fuse 250 is cut, the energy of the laser beam is mainly applied to the dummy gate electrode pattern 220, the dummy contact 260, and the dummy metal pattern 270, and thus is directly applied to the gate electrode pattern 210. The energy of the laser beam delivered to it can be minimized. As described above, the dummy gate electrode pattern 220 and the dummy metal pattern 270 do not affect the operation of the device. As a result, the aforementioned conventional problem, that is, damage or destruction of the gate electrode pattern due to the energy of the laser beam is minimized.

The best embodiments have been described in the drawings and specification. Herein, specific terms have been used, but they are used only for the purpose of illustrating the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, the scope of the present invention should be defined by the technical spirit of the appended claims.

According to the present invention, a dummy gate electrode pattern having no influence on the operation of the device is formed outside the fuse box exposed to the laser beam, particularly between the fuse box and the gate electrode pattern (first embodiment), or the dummy gate. An electrode pattern, a dummy contact and a dummy metal pattern are formed (second embodiment). Therefore, when the fuse is cut, even if misalignment or excessive energy is used to damage adjacent gate electrode patterns, the laser beam affects dummy gate electrode patterns located closer to the fuse box. As a result, damage or destruction of the gate electrode pattern due to the energy of the laser beam can be minimized, and thus adverse effects on the electrical characteristics of the device can be minimized.

Claims (3)

A plurality of gate electrode patterns formed on the semiconductor substrate; A fuse formed on the gate electrode pattern to electrically connect at least two gate electrode patterns of the plurality of gate electrode patterns, and electrically insulate them through a cutting process by a laser beam; An insulating layer formed on the fuse and defining a portion of the fuse box to be exposed by a laser beam for cutting the fuse; And And a dummy gate electrode pattern formed of the same conductive layer as the gate electrode pattern and formed between the fuse box portion and the gate electrode pattern. The semiconductor device of claim 1, wherein the dummy gate electrode pattern is maintained at a constant voltage level such as Vss, Vcc, and Vbb. The semiconductor device of claim 1, wherein the semiconductor device comprises: A dummy metal pattern formed on the fuse to be electrically insulated from the fuse and formed between the fuse box portion and the gate electrode pattern; And And a dummy contact electrically connecting the dummy gate electrode pattern and the dummy metal pattern.