WO2023236268A1 - Bit breakdown condition determining method and device - Google Patents

Abstract

A bit breakdown condition determining method and device. The method comprises: determining a plurality of first breakdown conditions (S101); breaking down, according to each first breakdown condition, a corresponding first bit respectively, to obtain a first breakdown result of each first breakdown condition, wherein different first breakdown conditions correspond to different first bits (S102); and determining a second breakdown condition from the plurality of first breakdown conditions according to the first breakdown results (S103). Because the second breakdown condition is selected based on the results of breakdown experiments, a good breakdown effect can be achieved.

Description

Method and equipment for determining bit breakdown conditions

This application claims priority to the Chinese patent application submitted to the China Patent Office on June 10, 2022, with the application number 202210655464.0 and the application title "Method and Equipment for Determining Bit Breakdown Conditions", the entire content of which is incorporated by reference in in this application.

Technical field

Embodiments of the present application relate to the field of semiconductor technology, and in particular, to a method and device for determining bit breakdown conditions.

Background technique

In the field of semiconductor technology, memory arrays are used to store data. Among them, the storage array is composed of multiple bits, each bit is used to store one bit of data. The storage array can be divided into a main array and a redundant array. The bits in the redundant array (which can be called redundant bits) are used to replace the failed bits (which can be called failed bits) in the main array. After replacing the failed bits, the data that needs to be stored in the failed bits is actually stored in the corresponding redundant bits.

In the prior art, before the above replacement process is performed, the oxide layer between the gate and drain of the redundant bit needs to be broken down to form a via. The breakdown process is carried out according to breakdown conditions, where the breakdown conditions may include but are not limited to: breakdown duration and breakdown voltage. When the breakdown time and/or breakdown voltage are small, breakdown failure may occur.

It can be seen that the breakdown conditions used in the above breakdown process affect the breakdown effect, so how to select the breakdown conditions for redundant bits is an issue that needs to be solved urgently.

Contents of the invention

Embodiments of the present application provide a method and device for determining a bit breakdown condition to determine the breakdown condition of a redundant bit.

In a first aspect, embodiments of the present application provide a method for determining bit breakdown conditions. The method includes:

Determine multiple first breakdown conditions;

According to each first breakdown condition, the corresponding first element is broken down to obtain the first breakdown result of each first breakdown condition. Different first breakdown conditions correspond to different first breakdown conditions. Describe the first element;

A second breakdown condition is determined from the plurality of first breakdown conditions based on the first breakdown result.

Optionally, the first breakdown result is used to indicate whether the plurality of first elements broken down by the first breakdown condition have respectively broken down, and the first breakdown result is obtained from the plurality of first elements according to the first breakdown result. The second breakdown condition is determined from the first breakdown condition, including:

Determine the breakdown success rate of the first breakdown condition according to the first breakdown result;

The second breakdown condition is determined from the first breakdown condition where the breakdown success rate is greater than or equal to a preset success rate threshold.

Optionally, determining the second breakdown condition from the first breakdown condition where the breakdown success rate is greater than or equal to a preset success rate threshold includes:

The first breakdown condition in which the breakdown success rate is greater than or equal to the preset success rate threshold is used as the third breakdown condition;

The third breakdown condition that satisfies a preset condition is determined as a second breakdown condition. The preset condition is a condition for at least one parameter: false breakdown rate, current difference, and the first breakdown condition. The breakdown duration is included, the breakdown voltage included in the first breakdown condition is included, and the current difference is the difference in current size between the bit cells that have not broken down and the bit cells that have broken down.

Optionally, the conditions for the false breakdown rate include at least one of the following: the false breakdown rate is less than or equal to the preset false breakdown rate, and is ranked in the top M positions in ascending order according to the false breakdown rate;

The conditions for the current difference include at least one of the following: the current difference is greater than or equal to the preset current difference, and the top N positions are arranged in descending order according to the current difference;

The conditions for the breakdown duration include at least one of the following: the breakdown duration is less than or equal to the preset duration, and is ranked in the top L positions in ascending order according to the breakdown duration;

The conditions for the breakdown voltage include at least one of the following: the breakdown voltage is less than or equal to a preset voltage, and the top K positions are arranged in ascending order of the breakdown voltage.

Optionally, the method also includes:

If the first breakdown condition in which the breakdown success rate is greater than or equal to the preset success rate threshold does not exist, then increase the breakdown duration and/or the breakdown voltage included in the first breakdown condition, And enter the step of performing breakdown on the corresponding first element according to each of the first breakdown conditions to obtain the first breakdown result of each first breakdown condition.

Optionally, increasing the breakdown duration and/or the breakdown voltage included in the first breakdown condition includes:

Increasing the breakdown duration in the first target breakdown condition, the first target breakdown condition being the one or more first breakdown conditions with the largest breakdown duration;

and/or, increasing the breakdown voltage in a second target breakdown condition, which is one or more first breakdown conditions in which the breakdown voltage is maximum.

Optionally, before determining the third breakdown condition that satisfies the preset condition as the second breakdown condition, the method further includes:

Determining a second bit to be broken down and a third bit other than the second bit for the third breakdown condition;

Perform breakdown on the second bit according to the third breakdown condition to obtain a second breakdown result;

The false breakdown rate for the third bit is determined according to the second breakdown result.

Optionally, the second breakdown result is used to indicate whether the third bit has been broken down, and determining the false breakdown rate for the third bit according to the second breakdown result includes: :

determining a total number of said second bits and said third bits;

The false breakdown rate is determined based on the ratio of the number of breakdown third bits to the total number.

Optionally, also includes:

If the third breakdown condition in which the false breakdown rate satisfies the corresponding condition does not exist, then reduce the breakdown duration and/or breakdown voltage included in the third breakdown condition, and enter the process according to the third breakdown condition. The step of performing breakdown on the second bit under three breakdown conditions to obtain a second breakdown result.

Optionally, reducing the breakdown duration and/or breakdown voltage included in the third breakdown condition includes:

Reduce the breakdown duration in a third target breakdown condition, the third target breakdown condition being one or more third breakdown conditions with the smallest breakdown duration;

and/or, reducing the breakdown voltage in a fourth target breakdown condition, which is one or more third breakdown conditions in which the breakdown voltage is minimum.

Optionally, the third bit is provided at an adjacent position of the second bit.

Optionally, the first breakdown condition corresponds to multiple first elements, and the multiple first elements corresponding to the same first breakdown condition are located in at least two non-adjacent areas of the redundant array. middle;

The third breakdown condition corresponds to a plurality of second bits, and the plurality of second bits corresponding to the same third breakdown condition are located in at least two non-adjacent areas of the redundant array.

Optionally, multiple first elements corresponding to the same first breakdown condition are located in two centrally symmetrical non-adjacent areas of the redundant array;

A plurality of second bits corresponding to the same third breakdown condition are located in two centrally symmetrical non-adjacent areas of the redundant array.

Optionally, before determining the third breakdown condition that satisfies the preset condition as the second breakdown condition, the method further includes:

For the third breakdown condition, a first current passing through a bit that has been broken down and a second current passing through a bit that has not been broken down are determined, and the bit that has been broken down includes at least one of the following: broken down The first bit and the second bit that have been broken down, and the unbroken bits include at least one of the following: the third bit that has not been broken down;

The current difference is determined based on the first current and the second current.

In a second aspect, embodiments of the present application provide a device for determining bit breakdown conditions. The device includes:

A first breakdown condition determination module, configured to determine a plurality of first breakdown conditions;

The first element breakdown module is used to conduct breakdown on the corresponding first element according to each of the first breakdown conditions, and obtain the first breakdown result of each first breakdown condition. The first breakdown condition corresponds to different first elements;

A second breakdown condition determination module is configured to determine a second breakdown condition from the plurality of first breakdown conditions according to the first breakdown result.

Optionally, the first breakdown result is used to indicate whether the plurality of first elements broken down by the first breakdown condition have been broken down respectively, and the second breakdown condition determination module is also used to:

Determine the breakdown success rate of the first breakdown condition according to the first breakdown result;

The second breakdown condition is determined from the first breakdown condition where the breakdown success rate is greater than or equal to a preset success rate threshold.

Optionally, the second breakdown condition determination module is also used to:

In the process of determining the second breakdown condition from the first breakdown condition whose breakdown success rate is greater than or equal to the preset success rate threshold, the first breakdown condition whose breakdown success rate is greater than or equal to the preset success rate threshold is determined. The first breakdown condition serves as the third breakdown condition;

The third breakdown condition that satisfies a preset condition is determined as a second breakdown condition. The preset condition is a condition for at least one parameter: false breakdown rate, current difference, and the first breakdown condition. The breakdown duration is included, the breakdown voltage included in the first breakdown condition is included, and the current difference is the difference in current size between the bit cells that have not broken down and the bit cells that have broken down.

Optionally, the conditions for the false breakdown rate include at least one of the following: the false breakdown rate is less than or equal to the preset false breakdown rate, and is ranked in the top M positions in ascending order according to the false breakdown rate;

The conditions for the current difference include at least one of the following: the current difference is greater than or equal to the preset current difference, and the top N positions are arranged in descending order according to the current difference;

The conditions for the breakdown duration include at least one of the following: the breakdown duration is less than or equal to the preset duration, and is ranked in the top L positions in ascending order according to the breakdown duration;

The conditions for the breakdown voltage include at least one of the following: the breakdown voltage is less than or equal to a preset voltage, and the top K positions are arranged in ascending order of the breakdown voltage.

Optionally, the device also includes:

A first breakdown condition adjustment module, configured to increase the breakdown included in the first breakdown condition if the first breakdown condition in which the breakdown success rate is greater than or equal to the preset success rate threshold does not exist. duration and/or the breakdown voltage, and enters the first element breakdown module.

Optionally, the first breakdown condition adjustment module is used for:

In the process of increasing the breakdown duration and/or the breakdown voltage included in the first breakdown condition, increasing the breakdown duration in the first target breakdown condition, the first target breakdown The condition is one or more first breakdown conditions with the maximum breakdown duration;

and/or, in the process of increasing the breakdown duration and/or the breakdown voltage included in the first breakdown condition, increasing the breakdown voltage in the second target breakdown condition, the third The second target breakdown condition is one or more first breakdown conditions where the breakdown voltage is maximum.

Optionally, the device also includes:

A bit determination module, configured to determine the second bit to be broken down and the second bit to be broken down for the third breakdown condition before determining the third breakdown condition that satisfies the preset condition as the second breakdown condition. The third bit beyond the second bit;

A second bit breakdown module, configured to breakdown the second bit according to the third breakdown condition to obtain a second breakdown result;

A false breakdown rate determination module, configured to determine a false breakdown rate for the third bit according to the second breakdown result.

Optionally, the second breakdown result is used to indicate whether the third bit has been broken down, and the false breakdown rate determination module is also used to:

In the process of determining the false breakdown rate for the third bit according to the second breakdown result, determining the total number of the second bit and the third bit;

The false breakdown rate is determined based on the ratio of the number of breakdown third bits to the total number.

Optionally, the device also includes:

The second breakdown condition adjustment module is configured to reduce the breakdown duration and/or breakdown included in the third breakdown condition if the third breakdown condition for which the false breakdown rate satisfies the corresponding condition does not exist. voltage and enters the second bit breakdown module.

Optionally, the second breakdown condition adjustment module is also used to:

In the process of reducing the breakdown duration and/or breakdown voltage included in the third breakdown condition, the breakdown duration in the third target breakdown condition is reduced, and the third target breakdown condition is the One or more third breakdown conditions with the smallest breakdown duration;

and/or, in the process of reducing the breakdown duration and/or breakdown voltage included in the third breakdown condition, reducing the breakdown voltage in the fourth target breakdown condition, the fourth target breakdown The conditions are one or more third breakdown conditions where the breakdown voltage is minimum.

Optionally, the third bit is provided at an adjacent position of the second bit.

Optionally, the first breakdown condition corresponds to multiple first elements, and the multiple first elements corresponding to the same first breakdown condition are located in at least two non-adjacent areas of the redundant array. middle;

The third breakdown condition corresponds to a plurality of second bits, and the plurality of second bits corresponding to the same third breakdown condition are located in at least two non-adjacent areas of the redundant array.

Optionally, multiple first elements corresponding to the same first breakdown condition are located in two centrally symmetrical non-adjacent areas of the redundant array;

A plurality of second bits corresponding to the same third breakdown condition are located in two centrally symmetrical non-adjacent areas of the redundant array.

Optionally, the device also includes:

a current determination module, configured to determine the first current passing through the broken down bit cell for the third breakdown condition before determining the third breakdown condition that satisfies the preset condition as the second breakdown condition, and , the second current passing through the unbroken bit, the bit that has been broken down includes at least one of the following: the first bit that has been broken down and the second bit that has been broken down, the bit that has not been broken down. The breakdown bits include at least one of the following: the third bit that is not broken down;

a current difference determining module, configured to determine the current difference according to the first current and the second current.

In a third aspect, embodiments of the present application provide an electronic device, including: at least one processor and a memory;

The memory stores computer execution instructions;

The at least one processor executes the computer execution instructions stored in the memory, so that the electronic device implements the method described in the first aspect.

In a fourth aspect, embodiments of the present application provide a computer-readable storage medium. Computer-executable instructions are stored in the computer-readable storage medium. When the computing device executes the computer-executable instructions, the computing device implements the first aspect. the method described.

In a fifth aspect, embodiments of the present application provide a computer program, the computer program being used to execute the method described in the first aspect.

The method and device for determining bit breakdown conditions provided by the embodiments of the present application can determine multiple first breakdown conditions; perform breakdown on the corresponding first bit according to each first breakdown condition to obtain each The first breakdown result of the first breakdown condition, different first breakdown conditions correspond to different first elements; the second breakdown condition is determined from multiple first breakdown conditions according to the first breakdown result. Embodiments of the present application can conduct breakdown experiments through multiple first breakdown conditions to determine second breakdown conditions. Since the second breakdown condition is selected based on the breakdown result of the breakdown experiment, it can be ensured that the second breakdown condition has a better breakdown effect in practice.

Description of the drawings

Figure 1 is a schematic structural diagram of a redundant array provided by an embodiment of the present application;

Figure 2 is a step flow chart of a method for determining bit breakdown conditions provided by an embodiment of the present application;

Figure 3 is a schematic structural diagram of a breakdown result detection circuit provided by an embodiment of the present application;

Figure 4 is a schematic diagram of the impact of an abnormal area on the breakdown result provided by the embodiment of the present application;

Figure 5 is a schematic diagram of the distribution of first elements in a redundant array provided by an embodiment of the present application;

Figure 6 is a schematic diagram of current distribution provided by an embodiment of the present application;

Figure 7 is a detailed flow chart of a second breakdown condition determination process provided by an embodiment of the present application;

Figure 8 is a schematic structural diagram of a device for determining bit breakdown conditions provided by an embodiment of the present application;

Figure 9 is a structural block diagram of an electronic device provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

The terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances so that the embodiments of the application described herein can, for example, be practiced in sequences other than those illustrated or described herein.

In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus that encompasses a series of steps or units and need not be limited to those explicitly listed. Those steps or elements may instead include other steps or elements not expressly listed or inherent to the process, method, product or apparatus.

In the embodiment of the present application, a plurality of first breakdown conditions are selected in advance, and breakdown experiments are performed on the bits through these first breakdown conditions to select appropriate second breakdown conditions. Since the second breakdown condition is selected based on the breakdown result of the breakdown experiment, it can be ensured that the second breakdown condition has a better breakdown effect in practice.

The above-mentioned bits in the embodiment of the present application may be redundant bits in a redundant array. The redundant array may include redundant bits in M rows and N columns, where M and N are values greater than or equal to 1. Figure 1 is a schematic structural diagram of a redundant array provided by an embodiment of the present application. Referring to Figure 1, the redundant array includes 10 rows and 10 columns of redundant bits, that is, 10×10=100 redundant bits. One redundant bit is used to store one bit of data, so the redundant array shown in Figure 1 can store 100 bits of data. Each redundant bit can be used to patch a bit in one main array, which means that the redundant array shown in Figure 1 can replace 100 bits in 100 main arrays.

FIG. 2 is a step flow chart of a method for determining bit breakdown conditions provided by an embodiment of the present application. Please refer to Figure 2. The above methods include:

S101: Determine multiple first breakdown conditions.

Each first breakdown condition may be a combination of breakdown conditions in one or more dimensions, and the first breakdown condition may include but is not limited to: breakdown duration and breakdown voltage. Among them, breakdown time and breakdown voltage are breakdown conditions in two dimensions.

For breakdown duration, it is used to indicate how long breakdown lasts, for example, 0.5ms (milliseconds), 1ms, 5ms, 10ms, and 30ms. Only when the breakdown time reaches a certain length can the redundant bits be broken down.

For the breakdown voltage, it is used to represent the voltage used to breakdown the redundant bits. For example, a default voltage V is set, so that the breakdown voltage can include: 0.8V, 0.85V, 0.9V, 0.95V and V. Only when the breakdown voltage reaches a certain voltage can the redundant bits be broken down.

In order to achieve accurate breakdown, it is usually necessary to include breakdown conditions in all dimensions that affect the breakdown effect in the first breakdown condition. When the breakdown conditions in all dimensions include the above-mentioned breakdown duration and breakdown voltage, multiple values of the breakdown duration and multiple values of the breakdown voltage can be combined in any way to obtain multiple first breakdown conditions, Each first breakdown condition includes a value of breakdown time and a value of breakdown voltage. For example, combining the breakdown durations of 0.5ms, 1ms, 5ms, 10ms and 30ms, as well as 0.8V, 0.85V, 0.9V, 0.95V and V, we get the 25 first breakdown conditions shown in the table below.

S102: Break down the corresponding first element according to each first breakdown condition to obtain the first breakdown result of each first breakdown condition. Different first breakdown conditions correspond to different first elements. Yuan.

Each first breakdown condition may correspond to one or more first bits, where the first bit is any redundant bit. Correspondingly, the first breakdown result is a breakdown result of the first element being broken down through the first breakdown condition, and the first breakdown result is used to indicate whether the first element has been broken down.

The above first breakdown result can be detected through a circuit. FIG. 3 is a schematic structural diagram of a breakdown result detection circuit provided by an embodiment of the present application. Referring to Figure 3, for each first element, after it is broken down according to the first breakdown condition, the resistor divided voltage of the first element can be measured and input into the comparator to output The first breakdown result corresponding to the first bit can be stored in the latch.

Among them, the above-mentioned comparator outputs the first breakdown result according to the following principle: when the resistance divided voltage of the first element is greater than the reference voltage, the comparator outputs the first value as the first breakdown result, which means that the first element has broken down. . On the contrary, when the resistor divided voltage of the first element is less than or equal to the reference voltage, the comparator outputs the second value as the first breakdown result, which means that the first element has not broken down. For example, the first value may be 1 and the second value may be 0.

It should be noted that in actual applications, each first element is connected to a comparator, and the comparators connected to each first element are connected to a latch. In this way, multiple values can be stored in the latch. The first breakdown result of the first element. Therefore, after the first cell is broken down through multiple first breakdown conditions, the first breakdown result of each first cell can be obtained from the latch.

In order to ensure that the first breakdown condition corresponds to a unique first breakdown result, that is, a first breakdown result is determined by a first breakdown condition, the embodiment of the present application assigns different first breakdown conditions to different The first element. In this way, the breakdown result of each first element is only affected by the corresponding first breakdown condition, which helps to accurately analyze the impact of each first breakdown condition on breakdown, thereby ensuring the final selection. Accuracy of breakdown conditions.

Optionally, when allocating corresponding one or more first bits to each first breakdown condition, the redundant bits in the redundant array can be divided into N equal parts, each equal part including one or a plurality of redundant bits, so that each equally divided redundant bit can be assigned to a first breakdown condition. In this way, the above N needs to be greater than or equal to the number of first breakdown conditions. For example, when the number of first breakdown conditions is 25, N may be 25. Referring to Figure 4, the first to second redundant bits in the first row and the first to second redundant bits in the second row in Figure 4 constitute a first breakdown condition D11. The first element. In addition, the first to second redundant bits in the second row and the first to second redundant bits in the third row in Figure 4 constitute another first breakdown condition D12. Bits. By analogy, the four adjacent redundant bits of the same pattern in Figure 4 can be used as the first bit corresponding to a first breakdown condition.

As can be seen from Figure 4, the first elements corresponding to the same first breakdown condition are arranged adjacently, but this arrangement may cause the first breakdown result to be affected by the position, resulting in lower accuracy. For example, as shown in FIG. 4 , there is an abnormal area in the redundant array, and the abnormal area includes 9 first bits in the upper left corner of the redundant array. In this scenario, the first breakdown condition of the following first element is affected by its position, causing the first breakdown result to be non-breakdown: all the first elements B11, B12, B21 and B22, partial first elements B31 and B32 of the first breakdown condition D12, partial first breakdown results of the first elements B13 and B23 of the first breakdown condition D13, and partial first elements of the first breakdown condition D14 Bit B33. The first breakdown results corresponding to the remaining first elements outside the abnormal area are only affected by the first breakdown condition.

It can be seen from the above results that the first breakdown results affected by the position are sorted from high to low as follows: the first breakdown results of the first breakdown condition D11, the first breakdown results of the first breakdown conditions D12 and D13 The result is the first breakdown result of the first breakdown condition D14. In this way, the accuracy of the first breakdown result of the first breakdown condition D11 is the lowest, the accuracy of the first breakdown result of the first breakdown conditions D12 and D13 is higher, and the accuracy of the first breakdown result of the first breakdown condition D14 is higher. The accuracy of wearing results is the highest.

In order to solve the problem of low accuracy of the first breakdown result caused by the above positional influence, embodiments of the present application may consider distributing multiple first elements corresponding to the same first breakdown condition in non-adjacent areas. . In this way, the first elements corresponding to the same first breakdown condition are distributed at different positions as much as possible, which helps to reduce the problem of low accuracy of the first breakdown result caused by the influence of position, and improves the accuracy of the first breakdown result. The accuracy of the wear results.

Optionally, multiple first elements corresponding to the same first breakdown condition are located in two centrally symmetrical non-adjacent areas of the redundant array. For example, FIG. 5 is a schematic diagram of the distribution of first elements in a redundant array provided by an embodiment of the present application. Referring to 5, the first element of D11 includes B11, B22, B33, B44, B55, B66, B77, B88, B99 and B00. Among them, the area where B11, B22, B33, B44 and B55 are located is the same as B66, The area where B77, B88, B99 and B00 are located is symmetrical about the center of symmetry. Similarly, the first element of D12 includes B01, B92, B83, B74, B65, B56, B47, B38, B29 and B00. Among them, the area where B11, B22, B33, B44 and B55 are located is the same as B66, B77, The area where B88, B99 and B10 are located is symmetrical about the center of symmetry. Of course, according to the symmetry center in Figure 5, the first elements of the remaining areas that are symmetrical to the symmetry center can be assigned to the remaining first breakdown conditions. Not all centrosymmetric first elements are shown in FIG. 5 .

S103: Determine a second breakdown condition from a plurality of first breakdown conditions according to the first breakdown result.

The second breakdown condition may be the first breakdown condition for successful breakdown, or the first breakdown condition for which the breakdown success rate is greater. The successful breakdown means that the first breakdown result is breakdown. Among them, the breakdown success rate is determined by the proportion of the first element that has a successful breakdown. For example, a certain first breakdown condition corresponds to 10 first elements, of which 9 are the first breakdowns of the first element. The result is that breakdown has occurred, so the breakdown success rate of the first breakdown condition can be 0.9.

When determining the second breakdown condition based on the first breakdown success rate, the second breakdown condition may be selected from the first breakdown conditions whose breakdown success rate is greater than or equal to the preset success rate threshold. In this way, it can be ensured that the selected second breakdown condition has a greater breakdown success rate, which helps to improve the success rate of repairing invalid bits by redundant bits.

Embodiments of the present application can provide two strategies for selecting the second breakdown condition to select the second breakdown condition from the first breakdown condition whose breakdown success rate is greater than or equal to the preset success rate threshold.

In the first strategy for selecting the second breakdown condition, the first breakdown condition whose breakdown success rate is greater than or equal to the preset success rate threshold is determined as the second breakdown condition.

In the second strategy for selecting the second breakdown condition, the first breakdown condition with a breakdown success rate greater than or equal to the preset success rate threshold is used as the third breakdown condition, so that the third breakdown condition that meets the preset condition is The breakdown condition is determined as the second breakdown condition.

The preset conditions here are conditions for at least one parameter: false breakdown rate, current difference, breakdown duration included in the first breakdown condition, and breakdown voltage included in the first breakdown condition.

Among them, the false breakdown rate is used to represent the proportion of bits with false breakdowns. The bits with false breakdowns refer to the bits that are broken down due to the breakdown of adjacent bits. For example, the redundant bits in the redundant array can be divided into bits that need to be broken down and bits that do not need to be broken down, so that after breakdown, the number of bits that do not need to be broken down can be counted. The number of bits is N1, and N1 can be used to determine the false breakdown rate. The false breakdown rate can be the ratio of N1 to the total number of bits that do not require breakdown, or the ratio of N1 to the total number of all bits.

It can be understood that the smaller the false breakdown rate, the better, so we can select the second breakdown condition from the third breakdown condition with a smaller false breakdown rate. In this way, it can be ensured that the selected second breakdown condition has a low false breakdown rate for redundant bits, thereby helping to avoid breakdown of redundant bits that do not need to be broken down, and helping to improve breakdown accuracy. Spend.

Specifically, the conditions for the false breakdown rate include at least one of the following: the false breakdown rate is less than or equal to the preset false breakdown rate, and they are ranked in the top M positions in ascending order of false breakdown rate. That is to say, the third breakdown condition whose false breakdown rate is less than or equal to the preset false breakdown rate and/or is ranked in the top M positions in ascending order of false breakdown rate can be determined as the second breakdown condition.

The above-mentioned current difference is the difference in current size between the unbroken bit and the broken bit. The current of the broken bit is usually greater than the current of the unbroken bit. The greater the current difference, the second hit. The breakdown condition of the redundant bits is more thorough, the breakdown effect is better, and the conductivity of the punctured redundant bits is better. Therefore, the second breakdown condition can be selected from the third breakdown condition with a larger current difference. In this way, it can be ensured that the selected second breakdown condition can breakdown the redundant bits more thoroughly and achieve better conductivity.

Specifically, the conditions for the current difference include at least one of the following: the current difference is greater than or equal to the preset current difference, and the top N positions are arranged in descending order of the current difference. That is to say, the third breakdown condition whose current difference is greater than or equal to the preset current difference, and/or is ranked in the top N positions in descending order of current difference can be determined as the second breakdown condition.

For the above breakdown duration, the second breakdown condition can be selected from the third breakdown condition with smaller breakdown duration. In this way, it can be ensured that the time required for the selected second breakdown condition to break down the redundant bits is short, which helps to shorten the breakdown time and the repair time, thereby saving time.

Specifically, the conditions for the breakdown duration include at least one of the following: the breakdown duration is less than or equal to the preset duration, and the devices are ranked in the top L positions in ascending order of breakdown duration. That is to say, the third breakdown condition whose breakdown duration is less than or equal to the preset duration, and/or is ranked in the top L positions in ascending order of breakdown duration can be determined as the second breakdown condition.

For the above breakdown voltage, the second breakdown condition may be selected from the third breakdown condition with a smaller breakdown voltage. In this way, it can be ensured that the selected second breakdown condition requires a smaller voltage to break down the redundant bit, which helps to save electric energy.

Specifically, the conditions for the breakdown voltage include at least one of the following: the breakdown voltage is less than or equal to the preset voltage, and the top K positions are arranged in ascending order of breakdown voltage. That is to say, the third breakdown condition whose breakdown voltage is less than or equal to the preset voltage and/or is ranked in the top K positions in ascending order of breakdown voltage can be determined as the second breakdown condition.

It should be noted that the above M, N, L and K are all integers greater than 1, and M, N, L and K may be the same or different.

In practical applications, one or more of the above-mentioned false breakdown rate, current difference, breakdown voltage and breakdown duration can be used in combination to select the second breakdown condition from the third breakdown condition. For example, the third breakdown condition in which the current difference is greater than or equal to the preset current difference and the false breakdown rate is less than or equal to the preset false breakdown rate can be determined as the second breakdown condition to ensure the second breakdown condition The false breakdown rate is smaller and the breakdown is more complete. For another example, the third breakdown condition that is ranked in the top M positions in ascending order of false breakdown rate and whose breakdown duration is less than or equal to the preset duration can also be determined as the second breakdown condition to ensure that the second breakdown condition The false breakdown rate is small and the time required for breakdown is small.

Of course, the third breakdown condition that meets the following conditions can also be determined as the second breakdown condition: the false breakdown rate is less than or equal to the preset false breakdown rate, the current difference is greater than or equal to the preset current difference, and the breakdown time is less than or equal to the preset time period, and the breakdown voltage is less than or equal to the preset voltage.

In an optional embodiment, after determining the breakdown success rate, the false breakdown rate can also be determined through a breakdown experiment on the second bit. That is to say, after determining the third breakdown condition, and before determining the third breakdown condition that satisfies the preset conditions as the second breakdown condition, it is necessary to conduct a second-bit breakdown experiment to determine whether the accidental breakdown penetration rate. This method decouples the first bit used to determine the breakdown success rate and the second bit used to determine the false breakdown rate, which helps to improve the accuracy of the breakdown success rate and the false breakdown rate. Accuracy.

The second bit is different from the first bit, and the second bit and the first bit may be located in the same redundant array or in different redundant arrays.

Specifically, the second bit to be broken down and the third bit other than the second bit are first determined based on the third breakdown condition; then, the second bit is broken down according to the third breakdown condition, and we obtain The second breakdown result; finally, determine the false breakdown rate for the third bit based on the second breakdown result.

Among them, the second bit can be understood as the bit that needs to be broken down, and the third bit can be understood as the bit that does not need to be broken down, so as to determine whether the third bit is in the process of breaking down the second bit. whether it was penetrated. Therefore, the proportion of the third bit that is penetrated among the third bits can be counted to determine the false breakdown rate.

In order to detect whether the third bit will be punctured as much as possible, the third bit can be set at an adjacent position of the second bit. In this way, the third bit is closer to the second bit. When the second bit is broken down, it has the greatest impact on the third bit. Therefore, it can be better detected whether the third bit is affected by the second bit. The breakdown of the bit affects the accuracy of the breakdown, which helps to improve the false breakdown rate.

The above-mentioned second breakdown result is used to indicate whether the second bit has broken down and whether the third bit has broken down. Therefore, the above-mentioned false breakdown rate can be the ratio of the number of breakdown third bits to the total number of bits, and the total number of bits can be the total number of second bits and third bits.

In the embodiment of the present application, the false breakdown rate can be expressed by the ratio of the number of the third bits that have been broken down to the total number of bits. The false breakdown rate not only takes into account the number of the third bits, but also the second bits. The amount of yuan. Compared with taking the ratio of the number of penetrated third bits to the total number of third bits as the false breakdown rate, the accuracy is higher.

Optionally, there are multiple second bits. The distribution is the same as the first bit. Multiple second bits corresponding to the same third breakdown condition can be located in at least two non-adjacent bits of the redundant array. in the area. In this way, the influence of the position of the second breakdown result of the third breakdown condition can be reduced as much as possible, which helps to improve the accuracy of the second breakdown result and the accuracy of the false breakdown rate, and can improve the false breakdown rate. The accuracy of selecting the second breakdown condition.

Further, similar to the distribution of the first bits, multiple second bits corresponding to the same third breakdown condition are located in two centrally symmetrical non-adjacent areas of the redundant array.

In another example of the embodiment of the present application, before determining the third breakdown condition that satisfies the preset condition as the second breakdown condition, the current difference also needs to be determined. Specifically, for the third breakdown condition, a first current passing through the bit cell that has been broken down and a second current passing through the bit cell that has not been broken down are determined, and the bit cell that has been broken down includes at least one of the following: broken down The first bit and the broken down second bit, the unbroken bit includes at least one of the following: the unbroken third bit; then, the current difference is determined according to the first current and the second current.

Since there are usually multiple unbroken bits and broken bits, the current difference can be calculated through the following steps: first determine the statistical value of the first current, including but not limited to: average value, maximum value, minimum value, etc. ; Then, determine the statistical value of the second current, including but not limited to: average value, maximum value, minimum value, etc.; Finally, subtract the statistical value of the second current from the statistical value of the first current to obtain the current difference.

Embodiments of the present application can determine the current difference by combining the aforementioned breakdown results of the first bit, the second bit, and the third bit, so that the current difference is determined through two breakdown experiments, thereby helping to improve the current. Difference accuracy. Furthermore, it helps to improve the accuracy of selecting the second breakdown condition based on the current difference.

Figure 6 is a schematic diagram of current distribution provided by an embodiment of the present application. Referring to FIG. 6 , the current distribution includes the following two parts: the current distribution passing through the unbroken bit cells and the current distribution passing through the broken down bit cells.

Referring to FIG. 6 , for the current distribution through unbroken bits, the abscissa is the current, and the unit can be microamperes (μA). The ordinate is the number of unbroken bits, and the unit can be units. As can be seen from Figure 6, the number of unbroken bits with current S1 is N1.

Referring to FIG. 6 , for the current distribution passing through the bit cells that have been broken down, the abscissa is the current. The ordinate is the number of bits that have been penetrated. It can be seen from Figure 6 that the number of broken down bits with current S2 is N2.

It can be seen from FIG. 6 that the difference between the maximum current passing through the unbroken bit cell and the minimum current passing through the broken down bit cell can be determined as the current difference. In this way, it can be ensured that the current difference is the minimum difference between the current passing through the bit that has been broken down and the current passing through the bit that has not been broken down. This minimum difference can more accurately represent the degree of difference between the first current and the second current. , helps to improve the accuracy of determining the second breakdown condition based on the current difference.

FIG. 7 is a detailed flow chart of a second breakdown condition determination process provided by an embodiment of the present application. Referring to FIG. 7 , the above-mentioned determination process of the second breakdown condition may include the following steps S1 to S12:

S1: Determine multiple first breakdown conditions to enter S2.

S2: Break down the corresponding first element according to each first breakdown condition to obtain the first breakdown result of each first breakdown condition. The first breakdown result is used to represent each first element. Whether the element has broken down to enter S3.

S3: Determine the breakdown success rate of the first breakdown condition based on the first breakdown result to enter S4.

S4: Determine the first breakdown condition whose breakdown success rate is greater than or equal to the preset success rate threshold as the third breakdown condition to enter S5.

S5: Determine whether the third breakdown condition exists. If it exists, go to S6. If it does not exist, go to S7.

S6: Select the third breakdown condition with smaller breakdown time and/or smaller breakdown voltage to enter S8.

S7: Increase the breakdown time and/or breakdown voltage in the first breakdown condition and enter S2.

It can be understood that increasing the breakdown duration and/or breakdown voltage in the first breakdown condition is to adjust the first breakdown condition so that the adjusted first breakdown condition breaks down the first element. The probability increases until there is a first breakdown condition in which the breakdown success rate is greater than or equal to the preset success rate threshold. In this way, successful determination of the second breakdown condition can be guaranteed.

In a first way of increasing, the breakdown duration and/or the breakdown voltage in all first breakdown conditions can be increased.

In the second way of increasing, some of the first breakdown conditions can be adjusted. Specifically, increase the breakdown duration in the first target breakdown condition, which is one or more first breakdown conditions with the largest breakdown duration; and/or increase the second target breakdown condition. The breakdown voltage in the condition, the second target breakdown condition is one or more first breakdown conditions with the maximum breakdown voltage.

It can be seen that the second increase method only increases the larger breakdown time and/or increases the larger breakdown voltage. Since a smaller breakdown duration needs to be increased by a larger margin to be able to penetrate the first element, this part of the breakdown duration can not be increased, but only a larger breakdown duration can be increased to achieve a faster Reach the breakdown time of the first element, saving time.

Similarly, since a smaller breakdown voltage needs to be increased to a larger extent to be able to break down the first element, this part of the breakdown voltage can not be increased, but only a larger breakdown voltage can be increased. Reach the breakdown voltage of the first element faster, saving time.

S8: The second bit is broken down through the third breakdown condition to obtain the second breakdown result. The second breakdown result is used to indicate whether the third bit has been broken down to enter S9.

S9: Determine the false penetration rate based on the ratio between the number of third bits that have been penetrated and the total number of bits, which is the number of second bits and the total number of third bits to enter S10.

S10: Determine whether the third breakdown bar with a false breakdown rate smaller than the preset false breakdown rate exists. If it exists, go to S11, if not, go to S12. In this way, it can be ensured that the false breakdown rate of the finally selected second breakdown condition is within a controllable range.

S11: Through the third breakdown condition with smaller breakdown time and/or smaller breakdown voltage and smaller false breakdown rate, the current difference is calculated to enter S13.

For this step, reference can be made to the detailed description of the statistical current difference mentioned above and will not be described again here.

S12: Reduce the breakdown time and/or breakdown voltage in the third breakdown condition to enter S8.

Specifically, reducing the breakdown duration and/or breakdown voltage in the third breakdown condition is to adjust the third breakdown condition so that the false breakdown rate of the adjusted third breakdown condition is reduced, Until there is a third breakdown condition where the false breakdown rate is less than the preset success rate threshold. In this way, successful determination of the second breakdown condition can be guaranteed.

In a first reduction manner, the breakdown duration and/or breakdown voltage in all first breakdown conditions can be reduced.

In the second reduction method, part of the third breakdown condition can be adjusted. Specifically, the breakdown duration in the third target breakdown condition can be reduced, and the third target breakdown condition is one or more third breakdown conditions with the smallest breakdown duration; and/or the fourth target breakdown condition can be reduced. The breakdown voltage in the breakdown condition, the fourth target breakdown condition is one or more third breakdown conditions with the smallest breakdown voltage.

It can be seen that the second reduction method only reduces the smaller breakdown time and/or reduces the smaller breakdown voltage. Since a larger breakdown time requires a larger reduction to make the false breakdown rate less than the preset false breakdown rate, this part of the breakdown time can not be reduced, and only the smaller breakdown can be reduced. time to make the false breakdown rate less than the preset false breakdown rate faster and save time.

Similarly, since a larger breakdown voltage requires a larger reduction to make the false breakdown rate less than the preset false breakdown rate, this part of the breakdown voltage can not be reduced, and only the smaller one can be reduced. Breakdown voltage to make the false breakdown rate less than the preset false breakdown rate faster, saving time.

S13: Determine the third breakdown condition with smaller breakdown time and/or smaller breakdown voltage, smaller false breakdown rate, and larger current difference as the second breakdown condition.

Corresponding to the above method embodiment, FIG. 8 is a schematic structural diagram of a device for determining bit breakdown conditions provided by an embodiment of the present application. Please refer to Figure 8. The device 200 for determining the above-mentioned bit breakdown condition includes:

The first breakdown condition determination module 201 is used to determine a plurality of first breakdown conditions.

The first element breakdown module 202 is used to conduct breakdown on the corresponding first element according to each first breakdown condition, and obtain the first breakdown result of each first breakdown condition. Different The first breakdown condition corresponds to different first elements.

The second breakdown condition determination module 203 is configured to determine a second breakdown condition from the plurality of first breakdown conditions according to the first breakdown result.

Optionally, the first breakdown result is used to indicate whether the plurality of first elements broken down by the first breakdown condition have been broken down respectively, and the second breakdown condition determination module is also used to:

The breakdown success rate of the first breakdown condition is determined according to the first breakdown result.

The second breakdown condition is determined from the first breakdown condition where the breakdown success rate is greater than or equal to a preset success rate threshold.

Optionally, the second breakdown condition determination module is also used to:

In the process of determining the second breakdown condition from the first breakdown condition whose breakdown success rate is greater than or equal to the preset success rate threshold, the first breakdown condition whose breakdown success rate is greater than or equal to the preset success rate threshold is determined. The first breakdown condition serves as the third breakdown condition.

The third breakdown condition that satisfies a preset condition is determined as a second breakdown condition. The preset condition is a condition for at least one parameter: false breakdown rate, current difference, and the first breakdown condition. The breakdown duration is included, the breakdown voltage included in the first breakdown condition is included, and the current difference is the difference in current size between the bit cells that have not broken down and the bit cells that have broken down.

Optionally, the conditions for the false breakdown rate include at least one of the following: the false breakdown rate is less than or equal to a preset false breakdown rate, and the top M positions are arranged in ascending order according to the false breakdown rate.

The conditions for the current difference include at least one of the following: the current difference is greater than or equal to a preset current difference, and the top N positions are arranged in descending order according to the current difference.

The conditions for the breakdown duration include at least one of the following: the breakdown duration is less than or equal to a preset duration, and the devices are ranked in the top L positions in ascending order according to the breakdown duration.

The conditions for the breakdown voltage include at least one of the following: the breakdown voltage is less than or equal to a preset voltage, and the top K positions are arranged in ascending order of the breakdown voltage.

Optionally, the device also includes:

A first breakdown condition adjustment module, configured to increase the breakdown included in the first breakdown condition if the first breakdown condition in which the breakdown success rate is greater than or equal to the preset success rate threshold does not exist. duration and/or the breakdown voltage, and enters the first cell breakdown module.

Optionally, the first breakdown condition adjustment module is used for:

In the process of increasing the breakdown duration and/or the breakdown voltage included in the first breakdown condition, increasing the breakdown duration in the first target breakdown condition, the first target breakdown The condition is one or more first breakdown conditions with the largest breakdown duration.

and/or, in the process of increasing the breakdown duration and/or the breakdown voltage included in the first breakdown condition, increasing the breakdown voltage in the second target breakdown condition, the third The second target breakdown condition is one or more first breakdown conditions where the breakdown voltage is maximum.

Optionally, the device also includes:

A bit determination module, configured to determine the second bit to be broken down and the second bit to be broken down for the third breakdown condition before determining the third breakdown condition that satisfies the preset condition as the second breakdown condition. The third bit beyond the second bit.

A second bit breakdown module is used to breakdown the second bit according to the third breakdown condition to obtain a second breakdown result.

A false breakdown rate determination module, configured to determine a false breakdown rate for the third bit according to the second breakdown result.

Optionally, the second breakdown result is used to indicate whether the third bit has been broken down, and the false breakdown rate determination module is also used to:

In the process of determining the false breakdown rate for the third bit according to the second breakdown result, a total number of the second bit and the third bit is determined.

The false breakdown rate is determined based on the ratio of the number of breakdown third bits to the total number.

Optionally, the device also includes:

The second breakdown condition adjustment module is configured to reduce the breakdown duration and/or breakdown included in the third breakdown condition if the third breakdown condition for which the false breakdown rate satisfies the corresponding condition does not exist. voltage and enters the second bit breakdown module.

Optionally, the second breakdown condition adjustment module is also used to:

In the process of reducing the breakdown duration and/or breakdown voltage included in the third breakdown condition, the breakdown duration in the third target breakdown condition is reduced, and the third target breakdown condition is the One or more third breakdown conditions with the smallest breakdown duration;

and/or, in the process of reducing the breakdown duration and/or breakdown voltage included in the third breakdown condition, reducing the breakdown voltage in the fourth target breakdown condition, the fourth target breakdown The conditions are one or more third breakdown conditions where the breakdown voltage is minimum.

Optionally, the third bit is provided at an adjacent position of the second bit.

Optionally, the first breakdown condition corresponds to multiple first elements, and the multiple first elements corresponding to the same first breakdown condition are located in at least two non-adjacent areas of the redundant array. middle.

The third breakdown condition corresponds to a plurality of second bits, and the plurality of second bits corresponding to the same third breakdown condition are located in at least two non-adjacent areas of the redundant array.

Optionally, multiple first elements corresponding to the same first breakdown condition are located in two centrally symmetrical non-adjacent areas of the redundant array.

A plurality of second bits corresponding to the same third breakdown condition are located in two centrally symmetrical non-adjacent areas of the redundant array.

Optionally, the device also includes:

a current determination module, configured to determine the first current passing through the broken down bit cell for the third breakdown condition before determining the third breakdown condition that satisfies the preset condition as the second breakdown condition, and , the second current passing through the unbroken bit, the bit that has been broken down includes at least one of the following: the first bit that has been broken down and the second bit that has been broken down, the bit that has not been broken down. The breakdown bits include at least one of the following: the third bit that is not broken down.

a current difference determining module, configured to determine the current difference according to the first current and the second current.

The above device embodiments are embodiments corresponding to the foregoing method embodiments, and have the same technical effects as the method embodiments. For detailed description of the device embodiment, reference may be made to the detailed description of the foregoing method embodiment, which will not be described again here.

Figure 9 is a structural block diagram of an electronic device provided by an embodiment of the present application. The electronic device 600 includes a memory 602 and at least one processor 601 .

Among them, memory 602 stores computer execution instructions.

At least one processor 601 executes computer execution instructions stored in the memory 602, so that the electronic device 601 implements the aforementioned method in FIG. 2 .

In addition, the electronic device may also include a receiver 603 for receiving information from other devices or devices and forwarding it to the processor 601, and a transmitter 604 for sending information to other devices or devices. .

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present application, but not to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features can be equivalently replaced; and these modifications or substitutions do not deviate from the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present application. scope.

For convenience of explanation, the above description has been made in conjunction with specific implementation modes. However, the above illustrative discussion is not intended to be exhaustive or to limit the embodiments to the specific forms disclosed. Various modifications and variations are possible in light of the above teachings. The above embodiments are selected and described to better explain the principles and practical applications, so that those skilled in the art can better use the embodiments and various modified embodiments suitable for specific use considerations.

Claims (18)

1. A method for determining bit breakdown conditions, including:

   Determine multiple first breakdown conditions;

   According to each first breakdown condition, the corresponding first element is broken down to obtain the first breakdown result of each first breakdown condition. Different first breakdown conditions correspond to different first breakdown conditions. Describe the first element;

   A second breakdown condition is determined from the plurality of first breakdown conditions based on the first breakdown result.
2. The method according to claim 1, wherein the first breakdown result is used to indicate whether the plurality of first elements broken down by the first breakdown condition have broken down respectively, and the first breakdown result according to the first breakdown condition is broken down. The breakdown result determines a second breakdown condition from the plurality of first breakdown conditions, including:

   Determine the breakdown success rate of the first breakdown condition according to the first breakdown result;

   The second breakdown condition is determined from the first breakdown condition where the breakdown success rate is greater than or equal to a preset success rate threshold.
3. The method of claim 2, wherein determining the second breakdown condition from the first breakdown condition where the breakdown success rate is greater than or equal to a preset success rate threshold includes:

   The first breakdown condition in which the breakdown success rate is greater than or equal to the preset success rate threshold is used as the third breakdown condition;

   The third breakdown condition that satisfies a preset condition is determined as a second breakdown condition. The preset condition is a condition for at least one parameter: false breakdown rate, current difference, and the first breakdown condition. The breakdown duration is included, the breakdown voltage included in the first breakdown condition is included, and the current difference is the difference in current size between the bit cells that have not broken down and the bit cells that have broken down.
4. The method of claim 3, wherein,

   The conditions for the false breakdown rate include at least one of the following: the false breakdown rate is less than or equal to the preset false breakdown rate, and the top M positions are arranged in ascending order according to the false breakdown rate;

   The conditions for the current difference include at least one of the following: the current difference is greater than or equal to the preset current difference, and the top N positions are arranged in descending order according to the current difference;

   The conditions for the breakdown duration include at least one of the following: the breakdown duration is less than or equal to the preset duration, and is ranked in the top L positions in ascending order according to the breakdown duration;

   The conditions for the breakdown voltage include at least one of the following: the breakdown voltage is less than or equal to a preset voltage, and the top K positions are arranged in ascending order of the breakdown voltage.
5. The method of claim 3, further comprising:

   If the first breakdown condition in which the breakdown success rate is greater than or equal to the preset success rate threshold does not exist, then increase the breakdown duration and/or the breakdown voltage included in the first breakdown condition, And enter the step of performing breakdown on the corresponding first element according to each of the first breakdown conditions to obtain the first breakdown result of each first breakdown condition.
6. The method according to claim 5, wherein said increasing the breakdown duration and/or the breakdown voltage included in the first breakdown condition includes:

   Increasing the breakdown duration in the first target breakdown condition, the first target breakdown condition being the one or more first breakdown conditions with the largest breakdown duration;

   and/or, increasing the breakdown voltage in a second target breakdown condition, which is one or more first breakdown conditions in which the breakdown voltage is maximum.
7. The method according to claim 3 or 4, wherein before determining the third breakdown condition that satisfies the preset condition as the second breakdown condition, it further includes:

   Determining a second bit to be broken down and a third bit other than the second bit for the third breakdown condition;

   Perform breakdown on the second bit according to the third breakdown condition to obtain a second breakdown result;

   The false breakdown rate for the third bit is determined according to the second breakdown result.
8. The method of claim 7, wherein the second breakdown result is used to indicate whether the third bit has been broken down, and the determination based on the second breakdown result for the third bit The false breakdown rate includes:

   determining a total number of said second bits and said third bits;

   The false breakdown rate is determined based on the ratio of the number of breakdown third bits to the total number.
9. The method of claim 7, further comprising:

   If the third breakdown condition in which the false breakdown rate satisfies the corresponding condition does not exist, then reduce the breakdown duration and/or breakdown voltage included in the third breakdown condition, and enter the process according to the third breakdown condition. The step of performing breakdown on the second bit under three breakdown conditions to obtain a second breakdown result.
10. The method of claim 9, wherein reducing the breakdown duration and/or breakdown voltage included in the third breakdown condition includes:

    Reduce the breakdown duration in a third target breakdown condition, the third target breakdown condition being one or more third breakdown conditions with the smallest breakdown duration;

    and/or, reducing the breakdown voltage in a fourth target breakdown condition, which is one or more third breakdown conditions in which the breakdown voltage is minimum.
11. The method of claim 7, wherein the third bit is positioned adjacent to the second bit.
12. The method of claim 8, wherein,

    The first breakdown condition corresponds to multiple first elements, and the multiple first elements corresponding to the same first breakdown condition are located in at least two non-adjacent areas of the redundant array;

    The third breakdown condition corresponds to a plurality of second bits, and the plurality of second bits corresponding to the same third breakdown condition are located in at least two non-adjacent areas of the redundant array.
13. The method of claim 12, wherein:

    Multiple first elements corresponding to the same first breakdown condition are located in two centrally symmetrical non-adjacent areas of the redundant array;

    A plurality of second bits corresponding to the same third breakdown condition are located in two centrally symmetrical non-adjacent areas of the redundant array.
14. The method according to claim 7, wherein before determining the third breakdown condition that satisfies the preset condition as the second breakdown condition, the method further includes:

    For the third breakdown condition, a first current passing through a bit that has been broken down and a second current passing through a bit that has not been broken down are determined, and the bit that has been broken down includes at least one of the following: broken down The first bit and the second bit that have been broken down, and the unbroken bits include at least one of the following: the third bit that has not been broken down;

    The current difference is determined based on the first current and the second current.
15. A device for determining bit breakdown conditions, including:

    A first breakdown condition determination module, configured to determine a plurality of first breakdown conditions;

    The first element breakdown module is used to conduct breakdown on the corresponding first element according to each of the first breakdown conditions, and obtain the first breakdown result of each first breakdown condition. The first breakdown condition corresponds to different first elements;

    A second breakdown condition determination module is configured to determine a second breakdown condition from the plurality of first breakdown conditions according to the first breakdown result.
16. An electronic device including: at least one processor and memory;

    The memory stores computer execution instructions;

    The at least one processor executes computer-executable instructions stored in the memory, so that the electronic device implements the method according to any one of claims 1 to 14.
17. A computer-readable storage medium that stores computer-executable instructions. When a computing device executes the computer-executable instructions, the computing device implements the method according to any one of claims 1 to 14. .
18. A computer program for executing the method of any one of claims 1 to 14.

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