JP2004118896A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device having a redundant structure and capable of increasing saving efficiency and suppressing an increase in a circuit area caused by the redundant structure. <P>SOLUTION: Upon reception of a line address signal A<m+n:0>, a determination circuit A performs a coincidence comparison operation between its higher-order address signal A<m+n:m+1> and the higher-order address FA<m+n:m+1> of a defective memory cell stored in a fuse latch group A to determine the selection/nonselection of a spare row block A. Upon reception of a determination signal for selecting the spare row block A, a coincidence comparison operation is performed between the lower-order address FC<m:0> of a defective redundant memory cell stored in a fuse latch group C and a lower-order address signal A<m:0> to determinate selection/nonselection of a spare row C. When the spare row C is selected, the spare row block A is set to be unselective at the end. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a redundant configuration for repairing a defective memory cell.
[0002]
[Prior art]
In a semiconductor memory device called a DRAM (Dynamic Random Access Memory), when a defect occurs in a part of a memory cell array, the defective part is replaced by a redundant circuit provided on a chip and relieved.
[0003]
As a rescue method, a spare (spare) row or column is provided in advance in a memory cell, and a memory cell defective due to a defect is replaced with a spare memory cell in a unit of row or column.
[0004]
Specifically, the address information of the defective memory cell is programmed in a redundant circuit and stored in a nonvolatile manner inside. When the access to the defective memory cell is requested in use, Data reading and data writing are performed using a redundancy circuit instead of a memory cell.
[0005]
With this configuration, even when a defective memory cell occurs due to a manufacturing defect, the entire semiconductor memory device can be normally operated using the redundant circuit including the spare memory cell. Thereby, it is possible to secure a product yield.
[0006]
However, in the above-described conventional remedy method, while a defective normal memory cell can be remedied by a spare memory cell, there is no means for remedying a defect in the spare memory cell.
[0007]
Therefore, a semiconductor memory device replaced with a defective spare memory cell still cannot operate normally due to a defect, making it difficult to secure a yield.
[0008]
As means for solving such a problem, for example, a semiconductor memory device disclosed in Patent Document 1 has been conventionally proposed.
[0009]
FIG. 14 is a principle explanatory diagram for explaining a rescue method in an example of a conventional semiconductor memory device.
[0010]
Referring to FIG. 14, first address storage circuit 100 stores an address for selecting a normal block including a plurality of word lines or bit lines as a first redundant address.
[0011]
The first redundant decoder 101 compares an externally input address signal with a first redundant address stored in the first address storage circuit 100, and if they match, the first redundant decoder 101 uses the externally input address signal. A first match determination signal JUG1 for replacing the selected normal block with a redundant block including a plurality of redundant word lines or a plurality of redundant bit lines is output.
[0012]
The second address storage circuit 102 stores a redundant word line to which a defective cell in a redundant block is connected, a plurality of redundant word lines including the redundant word line, a redundant bit line to which a defective cell is connected, or a redundant bit line thereof. A redundant address for selecting a plurality of redundant bit lines is stored as a second redundant address.
[0013]
The second redundant decoder 103 compares an externally input address signal with the second redundant address stored in the second address storage circuit 102, and if both match, replaces the defective cell in the redundant block with a new one. Alternatively, it outputs a second coincidence determination signal JUG2 for redundancy with a plurality of redundant word lines or one or more new redundant bit lines.
[0014]
Note that the first redundancy decoder 101 is inactivated based on the second match determination signal JUG2. Thus, the redundant word line to which the defective cell in the redundant block is connected or a plurality of redundant word lines including the redundant word line is not selected by the first redundant decoder.
[0015]
Therefore, according to the conventional semiconductor memory device, even if there is a defective cell in a redundant block, a redundant word line having the defective cell or a plurality of redundant word lines including the redundant word line is replaced with a new redundant word line. , The relief efficiency can be improved.
[0016]
[Patent Document 1]
JP-A-11-110996 (page 3, FIG. 1)
[0017]
[Problems to be solved by the invention]
Here, in the rescue method shown in FIG. 14, the first redundancy decoder 101 and the second redundancy decoder 103 serve as the first address storage circuit 100 and the second address storage circuit 102, respectively, as a first redundancy ROM (not shown) and a second redundancy storage (not shown). It has a two-redundant ROM, and the first redundant ROM stores addresses of defective blocks that are redundant by the first redundant decoder 101. On the other hand, the address of one defective word line generated in the redundant block is stored in the second redundant ROM.
[0018]
In this configuration, the first redundancy decoder 101 and the second redundancy decoder 103 separately decode an address signal input from the outside, and the first redundancy decoder 101 and the second redundancy decoder 103 decode the first redundancy decoder in accordance with a second match determination signal output from the second redundancy decoder. Deactivate the redundant decoder.
[0019]
Therefore, the selection / non-selection of the second redundancy decoder is determined independently of the selection / non-selection of the first redundancy decoder, so that the second address storage circuit 102 has the same scale as the first address storage circuit 100. Is required, and the circuit scale of the entire semiconductor memory device increases.
[0020]
On the other hand, in the remedy method in the conventional semiconductor memory device shown in FIG. 14, an operation test for obtaining address information for specifying a defective cell of a redundant block stored in the second address storage circuit 102 forms a redundant block. This is performed by designating redundant word lines as targets to be sequentially accessed and writing / reading data to / from the redundant word lines.
[0021]
For this purpose, the first storage circuit 100 needs to store (program) in advance address information for instructing access to the redundant word line instead of the normal word line, so that the conventional operation test Has provided a fuse blowing step before the execution of the operation test. Since the fuse blowing step is performed by applying a treatment such as laser cutting to the fuse element in the first storage circuit 100, there is a problem that a process in an operation test is complicated and a high cost is required.
[0022]
Therefore, the present invention has been made to solve such a problem, and one object of the present invention is to increase the rescue efficiency in a semiconductor memory device having a redundant configuration and suppress an increase in circuit area due to the redundant configuration. It is an object of the present invention to provide a semiconductor memory device capable of performing the following.
[0023]
Another object of the present invention is to provide a semiconductor memory device capable of performing an operation test for detecting a defective cell in a redundant block without cutting a fuse element in a storage circuit for storing address information of the redundant block. To provide.
[0024]
[Means for Solving the Problems]
One aspect of the present invention is a semiconductor memory device having a redundant configuration, comprising a first memory for replacing a plurality of memory cells and a defective memory cell generated in the plurality of memory cells in block units. A redundant circuit, a second redundant circuit for replacing and repairing a defective redundant memory cell generated in the first redundant circuit in a unit of row or column, and when the defective memory cell is designated as an access target, A redundancy control circuit for selectively activating either the first redundancy circuit or the second redundancy circuit. The redundancy control circuit is arranged corresponding to the first redundancy circuit, and is arranged corresponding to the first program circuit for storing an upper address of the address information specifying the defective memory cell, and the second redundancy circuit. A second program circuit for storing a lower address of the address information specifying the defective redundant memory cell, and an upper address of the defective memory cell for storing the first memory stored in the first program circuit. When the first redundant circuit is activated and the lower address of the defective memory cell stored in the second program circuit is designated as an access target when the first redundant circuit is activated, the second redundant circuit is activated. A determination circuit for activating the circuit and deactivating the first redundant circuit.
[0025]
Preferably, the determination circuit performs a match comparison operation between the upper address and an address signal for indicating an access target, and outputs a first match / mismatch determination signal, a lower comparator, A second comparison circuit that performs a match comparison operation with an address signal for indicating an access target and outputs a second match / mismatch judgment signal, and receives the first and second match / mismatch judgment signals Means for selecting activation / inactivation of the first and second redundant circuits. Upon receiving the first match determination signal from the first comparison circuit, the second comparison circuit performs a match comparison operation and outputs a second match / mismatch determination signal. When receiving the first coincidence determination signal and the second coincidence determination signal, the selection means deactivates the first redundant circuit and activates the second redundant circuit.
[0026]
More preferably, the first program circuit includes n first address circuits for nonvolatilely storing address information for specifying a defective address bit composed of n (n: natural number) bits forming an upper address of the defective memory cell. , A second program element for nonvolatilely storing an enable signal for activating the first redundant circuit, and a memory for outputting storage information of the first and second program elements to the determination circuit. (N + 1) first logic elements. The second program circuit includes m third program elements for nonvolatilely storing address information that specifies m (m: natural number) bits of defective address bits forming the lower address of the defective memory cell. A fourth program element for nonvolatilely storing an enable signal for activating the second redundant circuit, and (m + 1) pieces of information for outputting storage information of the third and fourth program elements to the determination circuit. And a second logic element.
[0027]
More preferably, the first and second program circuits further include a reset signal for initializing stored contents of the first to fourth program elements when the external power supply voltage is turned on, and Means for inputting to each of the first and second logic elements. The reset signal has a first logic level for a predetermined period after the external power supply voltage is turned on, initializes the storage contents of the first to fourth program elements, and changes to a second logic level after a predetermined period has elapsed. When the first and third program elements receive the reset signal of the second logical level, they store address information for specifying a defective address bit. The second and fourth program elements store an enable signal for activating the first and second redundant circuits when the reset signal of the second logic level is input.
[0028]
Preferably, when the reset signal of the second logic level is input, the first and second logic elements include address information for specifying a defective address bit stored in the first and third program elements; And an enable signal stored in the fourth program element are output to the determination circuit.
[0029]
According to another aspect of the present invention, there is further provided a test mode means for obtaining address information for specifying a defective redundant memory cell stored in the second program circuit. At the time of entry of the test mode means, a predetermined upper address stored in the first program circuit is designated as an access target, the first redundant circuit is activated, and a lower address for specifying a redundant memory cell in the first redundant circuit is specified. An operation test is performed by sequentially designating addresses as access targets.
[0030]
Preferably, there is further provided a test mode means for obtaining address information for specifying a defective redundant memory cell stored in the second program circuit. The test mode means includes a test entry signal input means for entering the test mode. When the test entry signal is input during a predetermined period after the external power supply voltage is turned on, the first program circuit fixes the reset signal to a first logic level and inputs the reset signal to each of the first logic elements. When the first logic element receives the reset signal of the first logic level, the first logic element stores address information for specifying a predetermined upper address stored in the first program element and the first logic element stored in the second program element. An enable signal for activating the redundant circuit is output to the determination circuit. When a predetermined upper address is designated as an access target, the determination circuit activates the first redundant circuit, and sequentially designates lower addresses specifying redundant memory cells in the first redundant circuit as access targets. Perform an operation test.
[0031]
More preferably, the predetermined upper address and the enable signal for activating the first redundant circuit are uniquely specified by the reset signal of the first logic level, and depend on the storage information of the first and second program elements. do not do.
[0032]
Preferably, the apparatus further comprises test mode means for obtaining address information for specifying a defective redundant memory cell generated in the plurality of first redundant circuits. At the time of entry of the test mode means, a plurality of first redundant circuits are sequentially stored by designating a predetermined upper address stored in a first program circuit corresponding to one of the plurality of first redundant circuits as an access target. When activated, an operation test is performed with the activated redundant memory cell in the first redundant circuit as an access target.
[0033]
Preferably, the predetermined upper address is specified in a first program circuit corresponding to each of the plurality of first redundant circuits so as not to match each other.
[0034]
Preferably, in a first program circuit corresponding to each of the plurality of first redundant circuits, a first logic element in one first program circuit and a first logic element in another first program circuit Are different from each other.
[0035]
Therefore, according to one aspect of the present invention, in a semiconductor memory device, if there is a defective redundant memory cell in a first redundant circuit that replaces and repairs a defective memory cell, a redundant configuration that is further replaced and repaired by a second redundant circuit. By doing so, the relief efficiency for the defective memory cell can be improved, so that the yield can be ensured, and the first program circuit and the second program circuit respectively perform the higher-order address information of the defective memory cell row. Since only the address or the lower address needs to be stored, the circuit scale can be reduced, and the increase in the circuit area due to the redundant configuration can be suppressed.
[0036]
Further, according to another aspect of the present invention, the operation test for obtaining the address information of the defective cell in the first redundant circuit stored in the second program circuit is performed by cutting the fuse element in the first program circuit. , The operation test process can be simplified and the cost can be reduced.
[0037]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.
[0038]
[Embodiment 1]
FIG. 1 is a configuration diagram showing details of an example of a portion of a memory cell array for schematically explaining a repair method in the semiconductor memory device according to the first embodiment of the present invention.
[0039]
Referring to FIG. 1, the memory cell array includes a regular memory cell array 1 composed of regular memory cells, and redundant memory cells for relieving regular memory cells A and B that have become defective due to defects. Spare row block (A) 2 and spare row block (B) 3, and spare rows (S) for repairing defective redundant memory cells in spare row block (A) 2 and spare row block (B) 3, respectively. C) 4 and a spare row (D) 5.
[0040]
In the semiconductor memory device including the memory cell array having the configuration shown in FIG. 1, a normal memory cell array is generated by an external row address signal A <m + n: 0> (= A (m + n) to A (0) (m and n are natural numbers)). When the memory cell row including the defective memory cell A in 1 is designated as an access target, the defective memory cell row is remedied by replacing the defective memory cell row with the spare row block (A) 2 in block units.
[0041]
In this embodiment, upper row address information A <m + n: m + 1> (= A (m + n) to A (m + 1)) is given to the memory cell row including the defective memory cell A in the normal memory cell array 1. The same plurality of memory cell rows are integrally replaced with a spare row block (A) 2.
[0042]
Here, the configuration in which a defective memory cell is replaced in a block unit is that if a redundant configuration is used to rescue individual memory cells, a fuse and a decoder are required for each configuration, and the circuit area increases. It is because.
[0043]
Further, as shown in FIG. 1, when a defective redundant memory cell RA exists in spare row block (A) 2 and a redundant memory cell row including this defective redundant memory cell RA is designated as an access target. By replacing this defective redundant memory cell row with a spare row (C) 3, it is relieved.
[0044]
In the present embodiment, a plurality of redundant memory cell rows that are selected by the higher address signal A <m + n: m + 1> of the row address signals A <m + n: 0> and constitute the replaced spare row block (A) 2 are described. The replacement is performed by replacing the defective redundant memory cell row selected by the lower address signal A <m: 0> with the spare row (C) 4.
[0045]
Similarly, the repair for the defective memory cell B in the normal memory cell array 1 is also selected by the memory cell row including the defective memory cell B and the higher address signal A <m + n: m + 1> of the row address signals A <m + n: 0>. This is performed by replacing a plurality of memory cell rows with spare row blocks (B) 3 in block units.
[0046]
Further, when a defective redundant memory cell RB among the replaced spare row blocks (B) 3 is designated as an access target, the redundant memory cell row including the defective redundant memory cell RB is replaced with the spare row (D). ) Is replaced by 5;
[0047]
Also at this time, the spare row block (B) 3 selected by the upper address signal A <m + n: m + 1> of the row address signal A <m + n: 0> is designated by the lower address signal A <m: 0>. The defective row is replaced by a spare row (D) 5 to replace the defective redundant memory cell row.
[0048]
Therefore, the semiconductor memory device having the redundant configuration shown in FIG. 1 can increase the efficiency of repairing a defective memory cell, and can secure a yield.
[0049]
Further, since the program circuits corresponding to the spare row block and the spare row only need to store only the upper address or the lower address of the addresses of the defective memory cell row, the circuit scale can be reduced, and the circuit associated with the redundant configuration can be reduced. An increase in area can be suppressed.
[0050]
FIG. 2 is a block diagram for extracting and explaining a portion related to the redundant configuration shown in FIG. 1 in the semiconductor memory device of the first embodiment.
[0051]
Referring to FIG. 2, the semiconductor memory device decodes a normal memory cell array 1 having a plurality of memory cells arranged in a matrix and a row address signal A <m + n: 0> to select a memory cell row. , A spare row block (A) 2 and a spare row block (B) 3 each composed of a redundant memory cell for relieving a defective memory cell, and spare row blocks (A) and (B). (A) 7 and decoder (B) 8 for executing selection of a spare row, and a spare row composed of redundant memory cells for repairing a defective redundant memory cell in spare row blocks (A) and (B). (C) 4 and a spare row (D) 5; and a decoder (C) 9 and a decoder (D) 10 for selecting the spare rows (C) and (D).
[0052]
The semiconductor memory device further includes fuse latch groups (A) to (D) 14 to 17 for storing address information relating to the defective memory cell in a nonvolatile manner in advance, a determination circuit (A) 11 and a determination circuit (B) 12 And
[0053]
Here, as described later, the fuse latch group (A) 14 and the fuse latch group (B) 16 correspond to the upper address of the address information A <m + n: 0> of the memory cell row including the defective memory cell. A <m + n: m + 1> is programmed.
[0054]
The fuse latch group (C) 15 and the fuse latch group (D) 17 have A <m corresponding to the lower address of the address information A <m + n: 0> of the memory cell row including the defective redundant memory cell. : 0> is programmed.
[0055]
The determination circuit (A) 11 and the determination circuit (B) 12 are provided with address information of a defective memory cell programmed in advance in the fuse latch groups (A) to (D) 14 to 17 and a row address signal input from the outside. And if the defective memory cell is to be accessed, the access is instructed to the corresponding spare row block (A) or (B) and spare block (C) or (D). I do.
[0056]
In the semiconductor memory device having the above-described configuration, the row address signal A <m + n: 0> input from the outside is input to the decoder 7 and simultaneously sent to the determination circuit (A) 11 and the determination circuit (B) 12. Is entered.
[0057]
The determination circuit (A) 11 further includes a memory cell row including a defective memory cell output from the fuse latch group (A) 14 and a plurality of memories to be accessed by an upper address of the defective memory cell row. Address information FA <m + n: m + 1> (= FA (m + n) to FA (m + 1)) for specifying a block including a cell row, and an enable signal FAE for activating the spare row block (A) 2 Is entered.
[0058]
Further, from the fuse latch group (C) 15, address signals FC <m: 0> (= FC (m) 〜 for specifying a redundant memory cell row including a defective memory cell in the spare row block (A) 2. FC (0)) and an enable signal FCE for activating the spare row (C) 4.
[0059]
Similarly, in addition to the row address signal A <m + n: 0>, the determination circuit (B) 12 is accessed by the upper address of the defective memory cell row output from the fuse latch group (B) 16. Information FB <m + n: m + 1> (= FB (m + n) to FB (m + 1)) for specifying a block including a plurality of memory cell rows and an enable for activating the spare row block (B) 3 Signal FBE is input.
[0060]
From the fuse latch group (D) 17, address information FD <m: 0> (= FD (m) 〜) for specifying a redundant memory cell row including a defective memory cell in the spare row block (B) 3 FD (0)) and an enable signal FDE for activating the spare row (D) 5.
[0061]
Here, the enable signals FAE to FAD of each spare row block and spare row disconnect the fuse element FS in the fuse latch circuits included in each of the fuse latch groups (A) to (D) 14 to 17 as described later. This signal is irreversibly activated to the “H” level. When a fuse element FS of a corresponding fuse latch circuit is cut off in response to detection of a defective memory cell and a defective redundant memory cell in the test mode, an enable signal at "H" level is output and spare It activates the row block and the spare row.
[0062]
Next, the determination circuit (A) 11 outputs a row address signal A <m + n: 0>, and address information FA <m + n: m + 1> and FC stored in the fuse latch group (A) 14 and the fuse latch group (C) 15. <M: 0> and a spare decoder (A) enable signal SDEA and spare signal for causing the decoder (A) 7 and the decoder (C) 9 to execute a row selection operation as a result of the match comparison. The decoder (C) outputs an enable signal SDEC.
[0063]
Similarly, in the determination circuit (B) 16, the row address signal A <m + n: 0> and the address information FB <m + n: m + 1> stored in the fuse latch group (B) 16 and the fuse latch group (D) 17 and A match comparison operation with FD <m: 0> is performed. As a result of the match comparison, spare decoder (B) enable signal SDEB and spare decoder (D) enable are provided to decoders (B) 8 and (D) 10. The signal SDED is output.
[0064]
Further, spare decoder enable signals SDEA to SDED are input to corresponding decoders (A) to (D) 7 to 10 and are also input to 4-input OR circuit 13.
[0065]
From the output node of the four-input OR circuit 13, a normal element disable signal NED is output as an operation result of the logical sum of the four input spare decoder enable signals SDEA to SDED, and is input to the decoder 6.
[0066]
Normal element disable signal NED is a signal for inactivating a defective memory cell in normal memory cell array 1, and is activated in response to activation of any one of four spare decoder enable signals SDEA to SDED. Then, it is input to the decoder 6 to stop the row selection operation of the normal decoder.
[0067]
That is, in the above-described semiconductor memory circuit, upon receiving an external row address signal A <m + n: 0>, selection / non-selection of the spare row block (A) 2 is performed for the upper address A <m + n: m + 1>. When the selection is determined and the spare row block (A) 2 is selected, the address of the defective redundant memory cell (corresponding to the lower address A <m: 0> of the row address signal) is received in response to the determination signal. Of the spare row (C) 4 is determined. When the spare row (C) 4 is selected, the spare row block (A) 2 is finally deselected.
[0068]
Therefore, the fuse latch group (A) 14 and the fuse latch group (C) 15 may be configured to store only the upper or lower address of the address information specifying the defective memory cell.
[0069]
Thereby, the address information for specifying the defective memory cell is stored in each of the first address storage circuit 100 and the second address storage circuit 102 and is separately decoded from the conventional semiconductor storage device shown in FIG. The circuit scale of the relief circuit can be reduced, and an increase in circuit area due to the redundant configuration can be suppressed.
[0070]
FIG. 3 is a circuit diagram showing details of an example of the determination circuit (A) 11 of FIG.
The determination circuit (B) 12 has the same configuration as that of the determination circuit (A) 11, and converts input address information from the fuse latch group and spare row block and spare row enable signals into corresponding signals. Since the same description can be made by replacing, the determination circuit (A) 11 will be described as an example, and the description of the determination circuit (B) 12 will be omitted.
[0071]
Referring to FIG. 3, determination circuit (A) 11 includes two-input EXNOR circuits 20 and 21, two-input AND circuits 22 and 24, and a three-input AND circuit 23.
[0072]
The 2-input EXNOR circuit 20 receives address information FA <m + n: m + 1> for specifying a defective memory cell stored in the fuse latch group (A) 14 of FIG. 2 at a first input node, and receives an external row address signal A When <m + n: 0> is received by the second input node, a match comparison operation between FA <m + n: m + 1> and the higher address A <m + n: m + 1> of the row address signal A <m + n: 0> is performed. I do.
[0073]
From the output node of the two-input EXNOR circuit 20, when the higher address A <m + n: m + 1> of the row address signal A <m + n: 0> matches the FA <m + n: m + 1> as a result of the match comparison (failure) "Meaning that the memory cell is to be accessed.", An "H" (logic high) level signal is output.
[0074]
On the other hand, if the upper address of the row address signal A <m + n: 0> does not match the FA <m + n: m + 1> (meaning that a defective memory cell is not to be accessed), it is “L” (logic). A low-level signal is output.
[0075]
On the other hand, the two-input EXNOR circuit 21 receives address information FC <m: 0> for specifying a defective redundant memory cell stored in the fuse latch group (C) 15 in FIG. When <m + n: 0> is received by the second input node, a match comparison operation between FC <m: 0> and the lower address A <m: 0> of the row address signal A <m + n: 0> is performed. I do.
[0076]
From the output node of the two-input EXNOR21 circuit, if the row address signal A <m + n: 0> matches the FC <m: 0> as a result of the match comparison (this indicates that the defective redundant memory cell is to be accessed). Means "H" level signal is output.
[0077]
On the other hand, if the row address signal A <m + n: 0> does not match FC <m: 0> (meaning that a defective redundant memory cell is not to be accessed), the signal at the “L” level is output. Is output.
[0078]
Next, the two-input AND circuit 22 receives a match comparison result output signal from the two-input EXNOR circuit 20 at a first input node, and receives a spare row block (A) enable signal FAE at a second input node. An operation result of a logical product of two signals is output to an output node.
[0079]
That is, the row address signal A <m + n: 0> matches the address information FA <m + n: m + 1> stored in the fuse latch group (A) 14 and the spare row block (A) enable signal FAE is set to “H”. When it is activated to the "" level, the output signal goes to the "H" level.
[0080]
The three-input AND circuit 23 receives an output signal of the two-input AND circuit 22 at a first input node, and receives a match comparison result output signal from the two-input EXNOR circuit 21 at a second input node. Further, the third input node receives a spare row (C) enable signal FCE.
[0081]
Thereby, the operation result of the logical product of these three signals is output to the output node of the three-input AND circuit 23.
[0082]
That is, the row address signal A <m + n: 0> matches the address information FA <m + n: m + 1> stored in the fuse latch group (A) 14 and the spare row block (A) enable signal FAE is set to “H”. Level, the row address signal A <m + n: 0> further matches the address information FC <m: 0> stored in the fuse latch group (C) 15. When spare row (C) enable signal FCE is activated to the “H” level, an “H” level signal is output from the output node of 3-input AND circuit 23.
[0083]
Output signals from the two-input AND circuit 22 and the three-input AND circuit 23 are input to the subsequent two-input AND circuit 24.
[0084]
At this time, the output signal of the three-input AND circuit 23 is inverted and input to the two-input AND circuit 24, and the spare decoder (C) that activates the decoder (C) 9 from the output node of the determination circuit (A) 11 ) Output as an enable signal SDEC.
[0085]
In the two-input AND circuit 24, the logical product of the output signal of the two-input AND circuit 22 and the inverted output signal of the three-input AND circuit 23 is calculated, and the calculation result is output to the decoder (A) 7. It is output as a spare decoder (A) enable signal SDEA to be activated.
[0086]
Here, the row address signal A <m + n: 0> matches the defective address FA <m + n: m + 1> stored in the fuse latch group (A) 14 and the defective address stored in the spare row (C) 4. If the spare address (F) and the spare row (C) enable signal FCE are both activated to the “H” level in the case where the redundant address FC <m: 0> is also matched, 2 The output node of input AND circuit 24 outputs spare decoder (A) enable signal SDEA at "L" level.
[0087]
On the other hand, an "H" level spare decoder (C) enable signal SDEC is output via an output node of the three-input AND circuit 23.
[0088]
Therefore, when row address signal A <m + n: 0> matches both defective address FA <m + n: m + 1> and defective redundant address FC <m: 0>, decoder (C) 10 is activated. Thus, the memory cell row including the defective memory cell in the normal memory cell is relieved by being replaced with the spare row (C) 4.
[0089]
On the other hand, when the row address signal A <m + n: 0> matches the defective address FA <m + n: m + 1> but does not match the defective redundant address FC <m: 0>, the two-input AND circuit 22 outputs An “H” level output signal is output, and an “L” level spare decoder (C) enable signal SDEC is output from 3-input AND circuit 23. In response, spare decoder (A) enable signal SDEA output from two-input AND circuit 24 attains "H" level.
[0090]
At this time, since the decoder (A) 7 is activated to execute the row selecting operation, the memory cell row including the defective memory cell in the normal memory cell is stored in the plurality of memories to be accessed by the upper address. Along with the cell row, the spare row block (A) is replaced in block units.
[0091]
A series of rescue processes in the determination circuit (A) 11 are executed in the same procedure in the determination circuit (B) 12, and the defective memory cell in the normal memory cell is replaced with the spare row block (B) 3 or the spare row (D). ) It is replaced by 5 and relieved.
[0092]
More specifically, if row address signal A <m + n: 0> matches both defective address FB <m + n: m + 1> and defective redundant address FD <m: 0>, spare at H level is set. Since the decoder (D) 10 is activated by the decoder (D) enable signal SDED to execute the row selecting operation, the memory cell row including the defective memory cell in the normal memory cell array 1 is replaced with the spare row (D) 5. To be relieved.
[0093]
On the other hand, if the row address signal A <m + n: 0> matches the defective address FB <m + n: m + 1> but does not match the defective redundant address FD <m: 0>, the “H” level spare decoder is used. (B) Since the decoder (B) 8 is activated by the enable signal SDEB to execute a row selecting operation, a plurality of memory cell rows including defective memory cells in the normal memory cell array 1 are selected by an upper address. Is replaced with a spare row block (B) 3 in block units together with the memory cell row of (1).
[0094]
FIG. 4 is a diagram for comprehensively explaining the operation of the memory when the above-described rescue processing is performed in the semiconductor memory device of the first embodiment.
[0095]
Referring to FIG. 4, when there is no defect in normal memory cell array 1 of FIG. 1, spare row block (A) enable signal FAE is at "L" level, and spare row block (A) 2 is non-active. In the active state, normal memory operation of data writing / reading is executed in normal memory cell 1.
[0096]
On the other hand, when a defect occurs in the normal memory cell array 1, the spare row block (A) enable signal FAE receives the signal and goes to the “H” level to activate the spare row block (A) 2. Therefore, the spare row block (A) 2 is accessed instead of the normal memory cell, and the memory operation is performed in the redundant memory cell of the spare row block (A) 2.
[0097]
The above is the rescue method when no defect occurs in the spare row block (A) 2. At this time, since spare row (C) enable signal FCE remains at the “L” level, spare row (C) 4 is in an inactive state.
[0098]
Here, if a defect occurs in the spare block A2 that replaces and repairs the normal memory cell, the spare column C enable signal FCE further goes to the “H” level, and the spare row (C) 4 is activated.
[0099]
Therefore, when a defective redundant memory cell is designated as an access target by an external row address signal, an access is instructed to spare row (C) 4 in place of the defective redundant memory cell. A memory operation is performed on spare row (C) 4.
[0100]
Similarly, the spare row block (B) 3 and the spare row (D) 5 for replacing and rescuing another defective memory cell in the normal memory cell array 1 also have a spare row block (B) enable signal FBE and a spare row ( D) When the spare row block (B) 3 and the spare row (D) 5 are activated in response to the enable signal FDE, the defective memory cells are replaced and rescued, and the memory operation shown in FIG. Be eligible.
[0101]
As described above, according to the first embodiment of the present invention, when a defective cell occurs in a spare row block for replacing and relieving a defective memory cell, and when the defective redundant memory cell becomes an access target, Since the defective memory cell is replaced and rescued by the spare row, the rescue efficiency can be improved, and the yield can be secured.
[0102]
Furthermore, since the spare row block and the fuse latch group corresponding to the spare row need only store the upper address or the lower address of the address information of the defective memory cell, the circuit scale of the repair circuit can be reduced. Thus, an increase in circuit area due to the redundant configuration can be suppressed.
[0103]
[Embodiment 2]
FIG. 5 is a block diagram for extracting and describing a portion related to a redundant configuration in the semiconductor memory device according to the second embodiment.
Referring to FIG. 5, the semiconductor memory device selects normal memory cell array 1, decoder 6, spare row block (A) 2 and spare row block (B) 3, and selection of spare row blocks (A) and B. It is composed of a decoder (A) 7 and a decoder (B) 8 to be executed, and redundant memory cells for repairing defective redundant memory cells in the spare row block (A) 2 and the spare row block (B) 3. Spare row (C) 4 and a decoder (C) 9 for selecting the spare row (C).
[0104]
Further, fuse latch groups (A) to (C) 14 to 16 for previously programming address information relating to the defective memory cell in a nonvolatile manner are compared with row address signals A <m + n: 0> for comparison. A determination circuit 30 for accessing the spare row block (A) 2 and the spare row block (B) 3 and the spare row (C) 4 according to the result is provided.
[0105]
The semiconductor memory device of FIG. 5 performs repair of spare row block (A) 2 and spare row block (B) 3 only with spare row (C) 4 in the semiconductor memory device of the first embodiment shown in FIG. Different in that.
[0106]
This is because, when the defect density of the spare row block is low, one spare row can sufficiently repair a plurality of spare row blocks.
[0107]
Therefore, by reducing the number of spare rows, it becomes possible to eliminate or reduce the fuse latch group and the judgment circuit and the like accompanying the spare rows, thereby reducing the circuit scale as compared with the configuration in which a spare row is provided for each spare block in FIG. Can be smaller.
[0108]
FIG. 6 is a circuit diagram showing details of an example of the determination circuit 30 of FIG.
Referring to FIG. 6, determination circuit 30 includes two-input EXNOR circuits 32-34, two-input AND circuits 35, 37, 39, 40, a three-input AND circuit 36, and a two-input OR circuit 38.
[0109]
In this configuration, the two-input EXNOR circuits 32-34 respectively include a row address signal A <m + n: 0> and a fuse latch, similarly to the two-input EXNOR circuits 20, 21 of the determination circuit (A) 11 shown in FIG. When the address information FA <m + n: m + 1>, FB <m + n: m + 1>, and FC <m: 0> of the defective memory cells stored in the groups (A) to (C) are received by the input node, a match comparison operation is performed. And outputs a signal corresponding to the result of the match comparison to the output node.
[0110]
Next, the output signals of the result of the match comparison of the two-input EXNOR circuits 32 to 34 are input to the first input nodes of the two-input AND circuits 35 and 37 or the three-input AND circuit 36 at the subsequent stage, respectively.
[0111]
The second input nodes of the two-input AND circuits 35 and 37 and the three-input AND circuit 36 respectively have a spare row block (A) enable signal FAE, a spare row block (B) enable signal FBE, and a spare row (C) enable. The signal FCE is input.
[0112]
An output signal FAECC is output from an output node of the two-input AND circuit 35 as a result of a logical product of the output signal of the result of the match comparison of the two-input EXNOR circuit 32 and the spare row block (A) enable signal FAE.
[0113]
The output signal FAECC is input to the first input node of the two-input AND circuit 39 and is also input to the first input node of the two-input OR circuit 38.
[0114]
Similarly, an output signal FBECC is output from the output node of the two-input AND circuit 37 as a result of the logical product of the output signal of the result of the match comparison of the two-input EXNOR circuit 34 and the spare row block (B) enable signal FBE. Is input to a first input node of a two-input AND circuit 40 and is input to a second input node of a two-input OR circuit 38.
[0115]
The two-input OR circuit 38 calculates the logical sum of the output signal FAECC and the output signal FBECC, and outputs the calculation result as the output signal FABE.
[0116]
When the output signal FABE is input to the third input node of the three-input AND circuit 36, the output signal FABE is logically connected between the output signal of the result of the match comparison from the aforementioned two-input EXNOR circuit 33 and the spare row (C) enable signal FCE. The product is calculated.
[0117]
Further, the output signal of the operation result of the three-input AND circuit 36 is output as a spare decoder (C) enable signal SDEC for activating the decoder (C) 9 in FIG. The signals are input to the second input nodes of the circuits 39 and 40.
[0118]
In the above configuration, the output signal FAECC is such that the upper address A <m + n: m + 1> of the row address signal A <m + n: 0> matches the address FA <m + n: m + 1> of the defective memory cell A, and the output signal FAECC is spare. When the row block (A) enable signal FAE is at the "H" level, the signal is at the "H" level.
[0119]
On the other hand, in the output signal FBECC, the higher address signal A <m + n: m + 1> of the row address signal A <m + n: 0> matches the address FB <m + n: m + 1> of the defective memory cell B and the spare row block (B) This signal is at the “H” level when the enable signal FBE is at the “H” level.
[0120]
Therefore, the signal FABE output from the two-input OR circuit 38 as the result of the logical sum of the output signals FAECC and FBECC is at the “H” level if one of the two output signals is at the “H” level. It becomes.
[0121]
That is, when either the defective memory cell A or B in the normal memory cell is to be accessed, the output signal FABE indicates the “H” level.
[0122]
Further, the spare decoder (C) enable signal SDEC output from the three-input AND circuit 36 is a signal that goes to “H” level when any of the input signals is at “H” level. If the lower address <m: 0> of <m + n: 0> matches the lower address FC <m: 0> of the defective memory cell, and the spare row (C) enable signal FCE is at “H” level, the output is low. When the signal FABE is at the "H" level, it goes to the "H" level.
[0123]
That is, when either the spare row block (A) 2 or the spare row block (B) 3 is to be accessed instead of the defective memory cell A or B in the normal memory cell, the redundant memory If the cell is further defective, spare decoder (C) enable signal SDEC goes to "H" level to indicate access to spare row (C) instead of the redundant memory cell row including the redundant memory cell, and the decoder ( C) 9 will be activated.
[0124]
At this time, the spare decoder (A) enable signal SDEA and the spare decoder (B) enable signal SDEB output from the two-input AND circuits 39 and 40 are the spare decoder (C) whose logic level is inverted to "L". Upon receiving the enable signal SDEC, the level becomes “L” level, and the decoder (A) 7 and the decoder (B) 8 are deactivated.
[0125]
Further, when the spare decoder enable signals SDEA, SDEB and SDEC are input to the three-input OR circuit 31 in FIG. 5, the logical sum of the three signals is calculated, and the "H" level normal element disable signal NED To stop the row selecting operation of the decoder 7.
[0126]
As described above, according to the second embodiment of the present invention, a semiconductor memory device has a redundant configuration in which a plurality of spare row blocks are repaired by one spare row, thereby maintaining a high repair efficiency and Since the circuit scale of the spare row and the associated fuse latch group and determination circuit can be reduced, it is possible to further suppress an increase in the circuit area due to the redundant configuration.
[0127]
[Embodiment 3]
FIG. 7 is a circuit diagram showing details of an example of the fuse latch group (A) 14 in FIG.
[0128]
Referring to FIG. 7, fuse latch group (A) 14 includes fuse latch circuits (FLA1) to (FLAn) 41 for programming each address bit of upper address information FA <m + n: m + 1> of the defective memory cell. -1,. . . 41-n and a fuse latch circuit (FLAE) 42 for programming a spare row block (A) enable signal FAE.
[0129]
Note that the fuse latch circuits (FLA1) to (FLAn) 41-1,. . . 41-n are provided corresponding to each of the defective address bits FA (m + 1) to FA (m + n), and fuse elements FS43-1,... For programming address information for each defective address bit. . . 43-n.
[0130]
The fuse latch circuits (FLA1) to (FLAn) 41-1,. . . Each input node of 41-n and fuse latch circuit (FLAE) 42 is connected to the output node of reset signal SFC generation circuit 18 for initializing fuse latch group (A) 14, and the output node has two inputs. The NAND circuits 45-1,. . . 45-n, 46-n.
[0131]
Here, the reset signal SFC is supplied to the fuse latch circuits (FLA1) to (FLAn) 41-1,. . . A reset signal SFC is generated based on the power-on reset signal POR output from the POR (power-on reset) circuit 19 shown in FIG. Generated by the circuit 18. The reset signal SFC indicates an “L” level during a certain period after turning on the external power supply (hereinafter, referred to as a “reset period”), and indicates an “H” level during a normal operation period.
[0132]
In the present embodiment, the reset signal SFC is generated based on the power-on reset signal POR. However, a reset signal SFC generation circuit may be independently provided outside, and may be directly input from there. This is the same as the operation and effect of the present embodiment described below.
[0133]
In the above configuration, the fuse latch circuits (FLA1) to (FLAn) 41-1,. . . When the reset signal SFC at the “H” level is input during the normal operation period, the fuse elements FS43-1,. . . By selecting cutting / non-cutting of 43-n, 1-bit program information is stored in a non-volatile manner, and program signals FAC1 to FACn of a level corresponding to the program information are generated.
[0134]
When the “H” level reset signal SFC is input, the fuse latch circuit (FLAE) 42 cuts the fuse element FS44 in accordance with whether or not the spare row block (A) 2 in FIG. / Non-cut, and activate / inactive information of the spare row block (A) 2 is stored in a nonvolatile manner to generate a program signal FACE.
[0135]
Next, the program signals FAC1 to FACn and FACE are supplied to the fuse latch circuits (FLA1) to (FLAn) 41-1,. . . 41-n and two-input NAND circuits 45-1,... Connected to respective output nodes of a fuse latch circuit (FLAE) 42. . . 45-n and 46 are input to the first input nodes.
[0136]
The two-input NAND circuits 45-1,. . . The “H” level reset signal SFC is input to each of the second input nodes 45-n and 46-n.
[0137]
Thereby, the two-input NAND circuits 45-1,. . . 45-n and 46 calculate the logical product of the program signals FAC1 to FACn and FACE and the reset signal SFC, and as the calculation result, FA (m + 1) to FA (m + n) which are information of each address bit and a spare row block. (A) Output enable signal FAE.
[0138]
FIG. 8 is a circuit diagram showing details of an example of a fuse latch circuit constituting the fuse latch group (A) 14 of FIG.
[0139]
Note that the fuse latch circuits (FLA1) to (FLAn), (FLAE) 41-1,. . . Since 41-n and 42-n have the same configuration, only one of the fuse latch circuits (FLA1) 41-1 will be described as an example.
[0140]
Referring to FIG. 8, a fuse latch circuit (FLA1) 41-1 includes a pulse generation circuit 60, a fuse element FS43-1, a P-channel MOS transistor 61, an N-channel MOS transistor 62, a transfer gate 64, It comprises inverters 65-69.
[0141]
An input node of fuse latch circuit (FLA1) 41-1 is connected to an input node of pulse generating circuit 60, and an output node of pulse generating circuit 60 is connected to a P-channel MOS transistor 61 and an N-channel MOS transistor 62 constituting a CMOS inverter. Connected to gate.
[0142]
The source of P-channel MOS transistor 61 is connected to external power supply node 63, and fuse element FS43-1 is connected between the source of N-channel MOS transistor 62 and the ground node.
[0143]
Fuse element FS43-1 is uncut and conductive in the initial state, and irreversibly changes to a non-conductive state when blown by an external blow input or the like. As a result, when fuse element FS43-1 is conductive, the source of N-channel MOS transistor 62 is electrically coupled to the ground node. The source of transistor 62 is electrically disconnected from the ground node.
[0144]
Transfer gate 64 is connected between the drain of P channel MOS transistor 61 and the input node of the latch circuit including inverters 67 and 68. Transfer gate 64 receives an inverted signal of output signal ISFC of pulse generation circuit 60 via inverter 65 and output signal ISFC via inverters 65 and 66, and electrically connects the output node of the CMOS inverter and the input node of the latch circuit. To combine.
[0145]
The output node of the latch circuit including inverters 67 and 68 is connected to inverter 69, and the output node of inverter 69 is connected to the output node of fuse latch circuit 41.
[0146]
In this configuration, when the reset signal SFC is input to the pulse generation circuit 60, one pulse waveform ISFC is generated and output from the pulse generation circuit 60.
[0147]
Next, when the output signal ISFC is input to the subsequent CMOS inverter, the output signal ISFC is output as a signal NI whose logic level is inverted.
[0148]
Here, transfer gate 64 is turned on when the logic level of output signal ISFC is "L", and transmits signal NI to a latch circuit including inverters 67 and 68.
[0149]
Finally, when the output signal of the latch circuit is input to the inverter 69, its logic level is inverted to generate a program signal FAC1, which is output from the output node of the fuse latch circuit 41-1 not shown.
[0150]
FIG. 9 is an operation waveform diagram of each output signal in the fuse latch circuit (FLA1) 41-1.
[0151]
Referring to FIG. 9, reset signal SFC (a) input to fuse latch circuit 41-1, signal ISFC (b) generated by pulse generation circuit 60, and signal ISFC are output via a CMOS inverter. FIG. 7 shows waveform diagrams of signals NI (c) and (e) and signals FAC1 (d) and (f) output from inverter 69 after signal NI is transmitted from transfer gate 64 to the latch circuit.
[0152]
In response to the change of the reset signal SFC in FIG. 9A from the reset period (corresponding to “L” level) to the normal operation state (corresponding to “H” level), the output signal IFC of the pulse generation circuit 60 becomes In the reset period, one pulse is generated at the voltage level that has been at the “H” level, and transitions to the “H” level again after falling to the “L” level for a predetermined period (FIG. 9B).
[0153]
In response to this, as shown in FIG. 9C, the signal NI is at either the “H” level or the “L” level during the reset period, but the signal ISFC that has transitioned to the “L” level is at the subsequent stage. The logic level is inverted by the CMOS inverter, and thereby the state transits to the “H” level.
[0154]
Further, the signal NI passes through the transfer gate 64 which is turned on after the signal ISFC at the "L" level is input, and is held at the "H" level in the latch circuit.
[0155]
Here, when the potential of the pulse in the signal ISFC changes from the “L” level to the “H” level, a change in the voltage level of the signal NI is shown below depending on whether the fuse element FS43-1 is cut or not cut. It follows two processes.
[0156]
When the fuse element FS43-1 is not cut and is in a conductive state, the electric potential of the signal NI held at the “H” level is equal to the electric charge between the N-channel MOS transistor 62 of the CMOS inverter and the fuse element FS43-1. As shown in FIG. 9 (c), the signal changes to the “L” level because the signal is pulled out to the ground node via the switch.
[0157]
At this time, the program signal FAC1 output via the output node of the inverter 69 transitions from “H” level to “L” level in response to the transition of the potential of the signal NI (FIG. 9D).
[0158]
On the other hand, when the fuse element FS43-1 is cut by an external blow input or the like and changes from the conductive state to the non-conductive state, the potential of the signal NI held at the “H” level becomes the fuse element FS43-1. Since the charge is not extracted from the N-channel MOS transistor 62 separated from the ground node by the disconnection of -1, the "H" level is maintained as shown in FIG.
[0159]
Receiving this, program signal FAC1 output via the output node of inverter 69 also holds "H" level (FIG. 9 (f)).
[0160]
As a result, in the normal operation state, the program signal FAC1 output from the fuse latch circuit (FLA1) 41-1 holds the “H” level due to the cutting of the fuse element FS43-1. The “L” level is maintained by the disconnection.
[0161]
Therefore, the fuse latch circuits (FLA1) to (FLAn), (FLAE) 41-1,. . . From 41-n and 42-n, program signals FAC1 to FACn and FACE which become “H” level when the internal fuse element FS is cut and become “L” level when not blown are output, respectively, and a two-stage NAND circuit at the subsequent stage 45-1,. . . The logic levels are inverted and input to first input nodes 45-n and 46-n, respectively.
[0162]
On the other hand, as described above, the two-input NAND circuits 45-1,. . . The “H” level reset signal SFC is input to the second input nodes 45-n and 46 in the normal operation state.
[0163]
Therefore, receiving the two signals, the two-input NAND circuits 45-1,. . . Defective address bit information FA (m + 1) to FA (m + n) and spare row block (A) enable signal FAE output from 45-n and 46-n respectively reflect the logic levels of program signals FAC1 to FACn and FACE as they are. It will be. For example, if the program signal FAC1 is at "H" level, the information FA (m + 1) of the defective address bit is at "H" level, and if the program signal FAC1 is at "L" level, FA (m + 1) is at "L" level. Level.
[0164]
Therefore, defective address bit information FA (m + 1) to FA (m + n) and spare row block (A) enable signal FAE are connected to fuse element FS43-1 in the normal operation state (reset signal SFC corresponds to "H" level). ,. . . 43-n and 44 are cut to "H" level, and the fuse elements FS43-1,. . . Since the level is set to “L” level when 43-n and 43- are not cut, the upper address FA <m + n: m + 1> of the defective memory cell is nonvolatile by selecting cutting / non-cutting of the corresponding fuse element FS. Can be stored.
[0165]
On the other hand, during the reset period (the reset signal SFC corresponds to the “L” level), the two-input NAND circuits 45-1,. . . The signals FA (m + 1) to FA (m + n) output from the output nodes 45-n and 46 and the spare row block (A) enable signal FAE have no relation to the logic levels of the program signals FAC1 to FACn and FACE. , Is always set to the “H” level.
[0166]
This means that the "L" level reset signal SFC is supplied to the two-input NAND circuits 45-1,. . . 45-n and 46-n, the logical level of the upper address FA <m + n: m + 1> of the address information of the defective memory cell and the spare row block (A) enable signal FAE is changed to the fuse element FS43-. 1,. . . 43-n and 44 can always be set to the "H" level regardless of whether the connection is cut or not.
[0167]
Therefore, if this reset signal SFC is used in fuse latch group (A) 14, an operation test of spare row block (A) 2 can be performed without cutting fuse element FS, as described below. , The address information of the redundant defective memory cell to be stored in the fuse latch group (C) 15 can be obtained.
[0168]
First, a test entry signal TE is input from a test entry signal generation circuit (not shown) to the reset signal SFC generation circuit 18 shown in FIG. 7 in order to enter the test mode during the reset period.
[0169]
At this time, when the test entry signal TE is input to the reset signal SFC generation circuit 18, the mode shifts to the test mode, and the logic level of the reset signal SFC, which is the "L" level, is fixed at "L".
[0170]
Therefore, in the test mode, the address information FA (m + 1) to FA (m + n) of the upper address bits and the spare row block (A) enable signal FAE are all set to the “H” level by the “L” level reset signal SFC. Is set to.
[0171]
Next, a row address signal A <m + n: 0> that sets all the upper addresses A <m + n: m + 1> to the “H” level is input from outside.
[0172]
As a result, the spare row block (A) 2 is designated as an access target instead of the normal memory cell.
[0173]
Therefore, spare row block (A) 2 is replaced with a normal memory cell and operates, and data can be written and read in the same manner as a normal memory cell.
[0174]
Further, by sequentially switching the lower row address signals A <m: 0>, the redundant memory cells of the spare row block (A) are successively accessed and an operation test is performed, so that a defect in the spare row block (A) is performed. Cells can be detected.
[0175]
As described above, according to the third embodiment, in the test mode, by using the reset signal SFC, the fuse latch group holds the address information of the predetermined logic level independent of the cutting / uncutting of the fuse element. Therefore, by setting the address of the predetermined logical level as an access target, it becomes possible to perform an operation test on the spare row block without cutting the fuse element, thereby simplifying the operation test. And cost is reduced.
[0176]
[Embodiment 4]
FIG. 10 is a circuit diagram showing details of an example of the fuse latch group (A) 14 and the fuse latch group (B) 16 in FIG.
[0177]
In a semiconductor memory device having a redundant configuration including a plurality of spare row blocks, an operation test on a spare row block described in the third embodiment is performed by changing the configuration of a fuse latch group corresponding to each spare row block. In each spare row block, the operation can be performed without cutting the fuse element FS.
[0178]
This time, an example in which an operation test is performed on spare row block (A) 2 and spare row block (B) 3 in the semiconductor memory device shown in FIG. 2 of the first embodiment will be described.
[0179]
Referring to FIG. 10, (a) shows a circuit configuration of fuse latch group (A) 14, and (b) shows a circuit configuration of fuse latch group (B) 16.
[0180]
The fuse latch group (A) 14 in FIG. 10A has the same configuration as the fuse latch group (A) 14 shown in FIG. 7 in the semiconductor memory device of the third embodiment.
[0181]
The fuse latch group (B) 16 in FIG. 10B has basically the same configuration as the fuse latch group (A) 14, and the upper address FB <m + n: m + 1> of the address information of the defective memory cell. Of the fuse latch circuits (FLB1) to (FLBn) 47-1,. . . 47-n and a fuse latch circuit (FLBE) 48 for programming a spare row block (B) enable signal FBE.
[0182]
The fuse latch circuits (FLB1) to (FLBn), (FLBE) 47-1,. . . Each input node of 47-n and 48 is connected to the output node of reset signal SFC generation circuit 18.
[0183]
Here, similarly to the fuse latch group (A) 14 of (a), the fuse latch circuits (FLB2) to (FLBn) and (FLBE) 47-2,. . . 47-n, 48-n are connected to two-input NAND circuits 51-2,. . . 51-n and 52 are connected to first input nodes.
[0184]
On the other hand, the output node of the fuse latch circuit (FLB1) 47-1 is connected to the two-input NAND circuit 45-1 while the output node of the fuse latch circuit (FLA1) 41-1 in FIG. It differs in that it is connected to the input AND circuit 51-1.
[0185]
Therefore, when the program signal FBC1 from the fuse latch circuit (FLB1) 47-1 is input to the first input node and the reset signal SFC is input to the second input node, the two-input AND circuit 51-1 An output signal FB (m + 1) is output as a logical product of the two signals.
[0186]
In the normal operation state (the reset signal SFC corresponds to the “H” level), the program signal FBC1 from the fuse latch circuit (FLB1) 47-1 cuts the fuse element FS49-1 similarly to the aforementioned program signal FAC1. And the signal FB (m + 1) output from the two-input AND circuit 51-1 disconnects the fuse element FS49-1. To an "H" level, and to an "L" level when the fuse element FS49-1 is not cut.
[0187]
Therefore, by selecting cutting / non-cutting of the corresponding fuse element FS49-1, the address information FB (m + 1) of the defective address bit can be stored in a nonvolatile manner.
[0188]
On the other hand, when the reset signal SFC is at the “L” level, the output signal FB (m + 1) of the two-input AND circuit 51-1 has no relation to the logic level of the program signal FBC1, and is always set to the “L” level. .
[0189]
That is, when the reset signal SFC is at the “L” level, the signal FB (m + 1) output from the output node of the two-input AND circuit 51-1 is “L” regardless of whether the fuse element FS49-1 is cut or not. ”Level, and the two-input NAND circuits 51-2,. . . Signals FB (m + 2) to FB (m + n) and FBE output from 51-n and 52-n are all set to "H" level.
[0190]
This is because the “L” level reset signal SFC is supplied to the two-input AND circuit 51-1 and the two-input NAND circuits 51-2,. . . 51-n and 52-52, the logical level of the upper address FB <m + n: m + 1> and the spare row block (B) enable signal FBE in the address information of the defective memory cell is changed to the fuse element FS49-. 1,. . . This means that FB (m + 1) = “L”, FB (m + 2) to FB (m + n) = “H”, and FBE = “H” can be set regardless of whether 49-n or 50 is cut or not.
[0191]
Therefore, similarly to the operation test on the spare row block (A) described in the third embodiment, in the test mode, the reset signal SFC is fixed at the “L” level by the test entry signal TE, and the upper address is externally supplied. If a row address signal A <m + n: 0> in which A (m + 1) of A <m + n: m + 1> is set to the “L” level and A (m + 2) to A (m + n) are all set to the “H” level, , Spare row block (B) 3 can be designated as an access target instead of a normal memory cell.
[0192]
Therefore, data can be written to and read from spare row block (B) 3 in the same manner as normal memory cells. Therefore, by sequentially switching lower row address signals A <m: 0>, The operation test can be performed by sequentially accessing the redundant memory cells of the spare row block (B) 3.
[0193]
The method of performing the operation test of each spare row block in the semiconductor memory device including the spare row block (A) 2 and the spare row block (B) 3 has been described above.
[0194]
Further, in a semiconductor memory device composed of two or more spare row blocks, in each fuse latch group, different combinations of a two-input AND circuit and a two-input NAND circuit are set to different upper addresses. Therefore, an operation test can be performed on a corresponding spare row block by sequentially designating the respective upper addresses as objects to be accessed.
[0195]
As described above, according to the fourth embodiment, the configuration of the logic circuit is mutually changed between the fuse latch groups corresponding to each of the plurality of spare row blocks, so that the individual fuse latch Since different address information can be held in the group by using the reset signal SFC, if the different address information is sequentially designated as an access target, a plurality of address information can be stored without disconnection of the fuse element. An operation test can be performed on the spare row block.
[0196]
[Embodiment 5]
FIG. 11 is a block diagram for extracting and explaining a portion related to a redundant configuration in the semiconductor memory device of the fifth embodiment.
[0197]
Referring to FIG. 11, the semiconductor memory device decodes normal memory cell array 1 and a row address signal RA <m + n: 0> (= RA (m + n) to RA (0)) to select a memory cell row. And a column decoder 71 that decodes a column address signal CA <p + q: 0> (= CA (p + q) to CA (0) (p, q: natural number)) to select a memory cell column. Spare row block (A) 2 composed of redundant memory cells for row repair of defective memory cells, and spare column composed of redundant memory cells for column repair of defective memory cells. A block (B) 75, a row decoder (A) 72 and a column decoder (B) 74 for selecting the spare row block (A) 2 and the spare column block (B) 75. , A spare row (C) 4 composed of redundant memory cells for repairing a defective redundant memory cell in spare row block (A) 2, and a defective redundant row in spare column block (B) 75. Spare column (D) 76 composed of redundant memory cells for relieving memory cells, row decoder (C) 73 and column decoder (D) for selecting spare row (C) 4 and spare column (D) 76 ) 77.
[0198]
The semiconductor memory device of the configuration of FIG. 11 has a configuration in which the semiconductor memory device of the first embodiment shown in FIG. 2 rescues a defective memory cell in the word line direction, whereas the semiconductor memory device of the first embodiment shown in FIG. (Row rescue) and bit line rescue (column rescue).
[0199]
This is because if replacement is performed in only one direction, a defective memory cell may not be able to be completely repaired. Therefore, by providing both the row repair and the column repair, the repair efficiency is improved. It is a thing.
[0200]
Furthermore, the spare latches (A) 14 and (C) 15 for programming the row address information relating to the defective memory cell are compared with the row address signal RA <m + n: 0>, and the spare row is executed. A determination circuit (A) 11 for accessing the block (A) 2 and the spare row (C) 4 is provided.
[0201]
Further, the semiconductor memory device compares the fuse latch group (B) 16 and the fuse latch group (D) 17 for programming column address information relating to the defective memory cell with the column address signal CA <p + q: 0>. A determination circuit (B) 12 for executing and accessing the spare column block (B) 75 and the spare column (D) 76 is provided.
[0202]
Here, similarly to the semiconductor memory device of the first embodiment, the fuse latch group (A) 14 corresponds to the upper address of the row address information FA <m + n: 0> of the memory cell row including the defective memory cell. FA <m + n: m + 1> is programmed.
[0203]
In the fuse latch group (C) 15, FA <m: 0> corresponding to the lower address of the row address information FA <m + n: 0> of the redundant memory cell row including the defective redundant memory cell is programmed. .
[0204]
On the other hand, in the fuse latch group (B) 16, FB <p + q: p + 1 corresponding to the upper address of the column address information FB <p + q: 0> (= FB (p + q) to FB (0)) including the defective memory cell > Has been programmed.
[0205]
In the fuse latch group (D) 17, FB <q: 0> corresponding to the lower address of the column address information FB <p + q: 0> of the memory cell column including the defective redundant memory cell is programmed.
[0206]
In the relief circuit having the above configuration, the row address signal RA <m + n: 0> input from the outside is input to the row decoder 70 and also to the determination circuit (A) 11 in parallel.
[0207]
Further, the address information FA <m + n: m + 1> of the defective memory cell row and the spare row block (A) enable signal FAE output from the fuse latch group (A) 14 are input to the determination circuit (A). .
[0208]
Further, from the fuse latch group (C) 15, address information FC <m: 0> of the defective redundant memory cell and a spare row (C) enable signal FCE are input.
[0209]
Similarly, in addition to the external column address signal CA <p + q: 0>, the address information FB <p + q: p + 1 of the defective memory cell column output from the fuse latch group (B) 16 is supplied to the determination circuit (B). > And spare column block (B) enable signal FBE.
[0210]
Further, address information FD <p: 0> of the defective redundant memory cell column in spare column block (B) 75 and spare column (D) enable signal FDE are input from fuse latch group (D) 17. .
[0211]
Next, the determination circuit (A) 11 performs a match comparison operation between the row address signal RA <m + n: 0> and the address information FA <m + n: m + 1> and FC <m: 0> of the defective memory cell row. The spare decoder (A) enable signal SDEA and the spare decoder (C) enable signal SDEC for executing the row selecting operation are output to the row decoder (A) 72 and the row decoder (C) 73 as the match comparison result. .
[0212]
Similarly, determination circuit (B) 12 performs a comparison operation between column address signal CA <p + q: 0> and address information FB <p + q: p + 1> and FD <p: 0> of the defective memory cell column. As a result of the match comparison, column decoder (B) 74 and column decoder (D) 77 output spare decoder (B) enable signal SDEB and spare decoder (D) enable signal SDED for executing a column selection operation, respectively. I do.
[0213]
Further, spare decoder (A) enable signal SDEA and spare decoder (C) enable signal SDEC are input to corresponding row decoder (A) 72 and row decoder (C) 73 and input to two-input OR circuit 79. Is done.
[0214]
From the output node of the two-input OR circuit 79, a normal element disable signal NEDRD activated when one of the spare decoder (A) enable signal SDEA and the spare decoder (C) enable signal SDEC is activated. Is output.
[0215]
As a result, the row decoder 70 is deactivated by the activated normal element disable signal NEDRD, and stops the row selection operation.
[0216]
On the other hand, spare decoder (B) enable signal SDEB and spare decoder (D) enable signal SDED are input to corresponding column decoder (B) 74 and column decoder (D) 77 and input to two-input OR circuit 78. Is done.
[0217]
A normal element disable signal NEDCD, which is activated by activating one of the spare decoder (B) enable signal SDEB and the spare decoder (D) enable signal SDED, is output from the output node of the two-input OR circuit 78. Then, column decoder 71 is deactivated and stops the column selection operation.
[0218]
Therefore, the semiconductor memory device of FIG. 11 is provided with a redundant configuration including the row rescue and the column rescue from the semiconductor memory device of the first embodiment, so that the rescue efficiency can be further improved, and the yield can be reduced. It can be further improved.
[0219]
Further, similarly to the semiconductor memory device of the first embodiment, the fuse latch group (A) 14 and the fuse latch group (C) 15 each include upper or lower addresses of the address information for specifying the defective memory cell row. The fuse latch group (B) 16 and the fuse latch group (D) 17 may store only the upper or lower address of the address information specifying the defective memory cell column. Therefore, it is possible to suppress an increase in the circuit scale due to the redundant configuration.
[0220]
As described above, according to the fifth embodiment of the present invention, a redundant configuration including a row rescue and a column rescue is provided, and a spare row and a spare column for replacing and reparing a spare row block and a spare column block are provided. Efficiency can be further increased.
[0221]
Further, since only the upper address or the lower address of the address information of the defective memory cell needs to be stored in each spare, it is possible to suppress an increase in circuit area due to the redundant configuration.
[0222]
Embodiment 6
FIG. 12 is a circuit diagram showing details of an example of fuse latch group (A) 14 and fuse latch group (B) 16 in the semiconductor memory device of the fifth embodiment shown in FIG.
[0223]
In the sixth embodiment, the operation test shown in the third embodiment is executed for each of the spare row block and the spare column block in the semiconductor memory device having the redundant configuration including the row repair and the column repair shown in FIG. The configuration of the fuse latch group for performing the operation will be described.
[0224]
Referring to FIG. 12, fuse latch group (A) 14 has a higher address FA <m + n: m + 1> in the row address information of the defective memory cell, similarly to fuse latch group (A) 14 shown in FIG. Fuse latch circuits (FLA1) to (FLAn) 41-1,. . . 41-n and a fuse latch circuit (FLAE) 42 for programming a spare row block (A) enable signal FAE.
[0225]
Further, the fuse latch circuits (FLA1) to (FLAn) 41-1,. . . 41-n and the output node of the fuse latch circuit (FLAE) 42 are connected to two-input NAND circuits 45-1,. . . 45-n, 46-n.
[0226]
Fuse latch group (B) 16 has the same configuration as fuse latch group (B) 16 shown in FIG. 10, but in order to perform column relief, upper address FB <p + q of column address information of defective memory cells: p + 1>, the fuse latch circuits (FLB1) to (FLBq) 82-1,. . . 82-q, and a fuse latch circuit (FLBE) 83 for programming the spare column block B enable signal FBE.
[0227]
Further, the fuse latch circuits (FLB1) to (FLBq), (FLBE) 82-1,. . . 82-q, 83 have 2-input AND circuits 84-1,. . . 84-q, 85 are connected to the first input nodes.
[0228]
Output nodes of the reset signal SFC generation circuit 18 are connected to the fuse latch circuits (FLA1) to (FLAn) and (FLAE) 41-1,. . . 41-n, 42-n, and are connected to the fuse latch circuits (FLB1) to (FLBq), (FLBE) 82-1,. . . 82-q, 83 are connected to the input nodes.
[0229]
The output node of the reset signal SFC generation circuit 18 further has two input NAND circuits 45-1,. . . 45-n, 46-n, and the two-input NAND circuits 84-1,. . . 84-q, 85 are connected to the second input nodes.
[0230]
An output node of the reset signal SFC generation circuit 18 is further connected to first input nodes of two-input OR circuits 86 and 88.
[0231]
In the two-input OR circuit 86, a reset signal SFC is input to a first input node, and a control signal RSCL is input to a second input node.
[0232]
Here, the control signal RSCL is a signal for selecting whether to perform row rescue or column rescue for a defective memory cell. During normal operation, the spare row block (A) enable signal FAE and spare column block (B) enable signal FBE are activated / deactivated independently of each other regardless of the level of control signal RSCL. In the mode, as will be described later, in response to the "H" / "L" level input of the control signal RSCL, one of them is activated and the other is inactivated. Thereby, either spare row block (A) 2 or spare column block (B) 75 can be selectively activated, and an operation test can be performed on the selected spare.
[0233]
When receiving the reset signal SFC and the control signal RCSL, the two-input OR circuit 86 outputs a row control signal RSL as an operation result of a logical sum of the two signals.
[0234]
The row control signal RSL is input to the second input node of the two-input NAND circuit 46 in the fuse latch group (A) 14, and the logic level is inverted through the inverter 87, so that the two-input OR circuit 88 Is input to the second input node.
[0235]
When the reset signal SFC and the row selection signal RSL whose logic level is inverted are input, the two-input OR circuit 88 outputs a column control signal CSL as an operation result of a logical sum of the two signals.
[0236]
The column control signal CSL is input to a second input node of the two-input NAND circuit 85 in the fuse latch group (B) 16.
[0237]
The operation test of the spare row block (A) 2 and the spare column block (B) 75 in the semiconductor memory device provided with the fuse latch group (A) 14 and the fuse latch group (B) 16 having the above configuration is as follows. It is performed according to the procedure shown.
[0238]
First, when a test entry signal is input to the reset signal SFC generation circuit 18 during the reset period after the external power supply voltage is turned on, the test mode is entered and the reset signal SFC is fixed at a logic level "L". You.
[0239]
Next, the “L” level reset signal SFC is output from the fuse latch circuits (FLA1) to (FLAn) 41-1,. . . 41-n, 2-input NAND circuits 45-1,. . . 45-n, the output signal FA (m + 1) set to the "H" level without depending on whether the fuse element FS (not shown) is cut or not cut, as described in the third embodiment. To FA (m + n) are output.
[0240]
On the other hand, the reset signal SFC at the “L” level is output from the fuse latch circuits (FLB1) to (FLBn) 82-1,. . . 82-q and two-input NAND circuit 85, output signals FB (p + 1),. . . FB (p + q) is output.
[0241]
In parallel with this, the control signal RCSL is input to the two-input OR circuit 86 together with the reset signal SFC at the “L” level.
[0242]
Here, when the control signal RCSL is at “H” level, the “H” level row selection signal RSL is output from the two-input OR circuit 86.
[0243]
Further, an “L” level reset signal SFC is input to the fuse latch circuit (FLAE) 42 in the fuse latch group (A) 14, and an “H” level row selection signal RSL is input to the two-input NAND circuit 46. Is done.
[0244]
Therefore, in two-input NAND circuit 46, program signal FACE set to “L” level in response to uncut fuse element FS (not shown) from fuse latch circuit (FLAE) 42 and row selection of “H” level Upon receiving signal RSL, spare row block (A) enable signal FAE at "L" level is output.
[0245]
On the other hand, the two-input OR circuit 88 receives the row selection signal RSL inverted to the “L” level by the inverter 87 and the “L” level reset signal SFC, and receives the “L” level column selection signal. Output CSL.
[0246]
Therefore, an “L” level reset signal SFC is input to fuse latch circuit (FLBE) 83 in fuse latch group (B) 16, and “L” level column selection signal CSL is input to 2-input NAND circuit 85. As a result, 2-input NAND circuit 85 outputs an “H” level spare column block (B) enable signal.
[0247]
That is, in response to the input of control signal RSCL at "H" level, spare row block (A) enable signal FAE is set to "L" level, and spare column block (B) enable signal FBE is set to "H" level. , The spare row block (A) 2 is deactivated, while the spare column block (B) 75 is activated.
[0248]
When the control signal RSCL at the “L” level is input, the opposite is true, the spare row block (A) enable signal FAE is set to the “H” level, and the spare column block (B) enable signal FBE is set. Is set to the “L” level, the spare row block (A) 2 is activated, while the spare column block (B) 75 is deactivated.
[0249]
When an operation test is to be performed on spare column block (B) 75 based on the above results, control signal RSCL at “H” level is input to activate spare column block (B) 75 in the test mode. By instructing access to address information FB <p + q: p + 1> output from fuse latch group (B) 16, data can be written / read to / from spare column block (B) 75 in the same manner as a normal memory cell. By sequentially switching the lower column address signals CA <p: 0>, the redundant memory cells of the spare column block (B) 75 can be sequentially accessed and executed.
[0250]
On the other hand, when an operation test is performed on spare row block (A) 2, inputting “L” level control signal RCSL in test mode activates spare row block (A) 2. , And instructs access to address information FA <m + n: m + 1> output from fuse latch group (A) 14, and redundant memory cells in spare row block (A) 2 by lower order row address signal RA <m: 0>. This can be done by accessing the rows sequentially.
[0251]
As described above, according to the sixth embodiment of the present invention, in a semiconductor memory device having a redundant configuration including row rescue and column rescue, control signal RCSL for selecting activation / inactivation of spare row block and spare column block is provided. By inputting, an operation test for each spare can be performed.
[0252]
Embodiment 7
In a semiconductor memory device having a redundant configuration for performing row rescue and column rescue, as shown in FIG. 12 of the sixth embodiment, a fuse latch group in a rescue circuit activates / deactivates a spare row block and a spare column block. By inputting a control signal RCSL for selecting a spare, an operation test can be performed for each spare.
[0253]
However, on the other hand, in the configuration of FIG. 12, only one of the spares is selected and activated such that spare row block (A) 2 is inactivated when spare column B75 is activated. Therefore, in the intersection area 80 between the spare row block (A) 2 and the spare column block (B) 75 shown by the hatched area in FIG. 11, the control signal RCSL is set to either “H” or “L”. Since it is not activated even at the logic level, an operation test cannot be performed.
[0254]
Therefore, by providing the control signal RCSL independently for the spare row block and the spare column block, it is possible to perform an operation test also on the intersection area 80 indicated by oblique lines.
[0255]
FIG. 13 is a circuit diagram showing details of an example of the fuse latch group (A) 14 and the fuse latch group (B) 16 of the semiconductor memory device according to the seventh embodiment.
[0256]
Referring to FIG. 13, the fuse latch group of the seventh embodiment is different from the fuse latch group of FIG. 12 in that the selection of activation / inactivation of spare row block (A) 2 and spare column block (B) 75 is performed. It differs in that it has input means for a row control signal RCSLR and a column control signal RCSLC for independent operation, and the fuse latch group (A) 14 and the fuse latch group (B) 16 have the same configuration. Will not be described again.
[0257]
In the configuration shown in FIG. 13, in the test mode, row control signal RCSLR for selecting activation / inactivation of spare row block (A) 2 is a two-input OR signal together with reset signal SFC fixed at “L” level. The signal is input to the circuit 89.
[0258]
Here, when row control signal RCSLR is at “H” level, 2-input OR circuit 89 outputs a row selection signal RSL at “H” level.
[0259]
As a result, the “L” level reset signal SFC is input to the fuse latch circuit (FLAE) 42 in the fuse latch group (A) 14, and the “H” level row selection signal RSL is input to the two-input NAND circuit 46. Is entered.
[0260]
Therefore, in two-input NAND circuit 46, program signal FACE set to “L” level in response to uncut fuse element FS (not shown) from fuse latch circuit (FLAE) 42 and row selection of “H” level Upon receiving signal RSL, spare row block (A) enable signal FAE at "L" level is output.
[0261]
On the other hand, when row control signal RCSLR is at “L” level, 2-input OR circuit 89 outputs a row selection signal RSL at “L” level.
[0262]
Accordingly, the fuse latch circuit (FLAE) 42 in the fuse latch group (A) 14 receives the “L” level reset signal SFC, and the two-input NAND circuit 46 receives the “L” level row selection signal RSL. As a result, the two-input NAND circuit 46 outputs an "H" level spare row block (A) enable signal FAE.
[0263]
That is, in the test mode, spare row block (A) enable signal FAE attains an “L” level in response to “H” level row control signal RCSLR, and spare row block (A) 2 is inactivated. , Spare row block (A) 2 is activated since spare row block (A) enable signal FAE attains “H” level in response to row control signal RCSLR of “L” level.
[0264]
Therefore, when an operation test is performed on spare row block (A) 2, spare row block (A) 2 is activated by inputting “L” level row control signal RCSLR in the test mode. , And instructs access to address information FA <m + n: m + 1> output from fuse latch group (A) 14, and redundant memory cells in spare row block (A) 2 by lower order row address signal RA <m: 0>. This can be done by accessing the rows sequentially.
[0265]
The above is the operation test on the spare row block (A) 2 using the row control signal RCSLR. Similarly, the operation test on the spare column block (B) 75 is performed similarly to the activation / deactivation of the spare column block (B) 75. By inputting the column control signal RCSLC for selecting inactivation to the two-input OR circuit 90, it is possible to perform the operation independently.
[0266]
More specifically, in test mode, spare column block (B) enable signal FBE attains an L level in response to an H level column control signal RCSLC, so that spare column block (B) 75 is inactivated. , Spare column block (B) 75 is activated since spare column block (B) enable signal FBE attains an H level according to column control signal RCSLC at an L level.
[0267]
Therefore, in the operation test of spare column block (B) 75, in the test mode, column control signal RCSLC of "L" level is input to activate spare column block B75, and output of fuse latch group (B) 16 If the address information FB <p + q: p + 1> to be accessed is designated as an access target, execution is performed by sequentially accessing the redundant memory cell rows in the spare column block (B) 75 by the lower column address signal CA <p: 0>. be able to.
[0268]
As a result, the operation test of spare row block (A) 2 and spare column block (B) 75 can be performed by individually controlling row control signal RCSLR and column control signal RCSLC.
[0269]
Further, if both row control signal RCSLR and column control signal RCSLC are set to “L” level, both spare row block (A) 2 and spare column block (B) 75 are activated, and FIG. The intersection area 80 can be activated.
[0270]
Therefore, when an access is instructed to intersection area 80, an operation test can be performed, and defective redundant memory cells in intersection area 80 can be detected.
[0271]
As described above, according to the seventh embodiment of the present invention, in a semiconductor memory device having a redundant configuration including a row rescue and a column rescue, control for independently selecting activation / inactivation of a spare row block and a spare column block. By inputting signals RCSLR and RCSLC, it is possible to perform an operation test on an intersection region between a spare row block and a spare column block.
[0272]
The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
[0273]
【The invention's effect】
As described above, according to one aspect of the present invention, when a defective redundant memory cell in a spare row block that replaces and repairs a defective memory cell is to be accessed, the defective redundant memory cell is further replaced by a spare row. Since the replacement relief is performed, the relief efficiency can be increased, and the yield can be improved.
[0274]
Furthermore, since the spare row block and the fuse latch circuit corresponding to the spare row only need to store only the upper address or the lower address of the address information of the defective memory cell, the circuit scale of the repair circuit can be reduced. Thus, an increase in circuit area due to the redundant configuration can be suppressed.
[0275]
In addition, by relieving a plurality of spare row blocks with one spare row, a high rescue efficiency can be maintained, and the spare row, the fuse latch group associated therewith, and the circuit scale of the determination circuit can be reduced. It is possible to further suppress an increase in circuit area.
[0276]
Further, by using both the row rescue and the column rescue, and using a configuration of a rescue circuit provided with a spare row and a spare column for each of the spare row block and the spare column block, the rescue efficiency can be further enhanced. Since the fuse latch group for each spare stores only the upper address or the lower address, it is possible to suppress an increase in area due to the redundant configuration.
[0277]
According to another aspect of the present invention, in the test mode, if the reset signal SFC is used, the fuse latch group can hold address information of a predetermined logic level independent of cutting / uncutting of the fuse element. Since it is possible to perform the operation test on the spare row block without cutting the fuse element by making the address of the predetermined logic level an access target, the operation test can be simplified and the cost can be reduced. It becomes.
[0278]
Furthermore, by mutually changing the configuration of the logic circuit between the fuse latch groups corresponding to each of the plurality of spare row blocks, in the test mode, the individual fuse latch groups use the reset signal SFC to perform mutual operation. Since address information of different logical levels can be held in the memory device, if addresses of different logical levels are sequentially specified as targets of access, the operation for a plurality of spare row blocks can be performed without cutting the fuse element. Testing can be performed.
[0279]
Further, in a semiconductor memory device having a redundant configuration including row repair and column repair, an operation test for each spare is performed by inputting a control signal RCSL for selecting activation / inactivation of a spare row block and a spare column block. Can do it.
[0280]
Further, by inputting control signals RCSLR and RCSLC for independently selecting the activation / inactivation of the spare row block and the spare column block, an operation test on an intersection region between the spare row block and the spare column block can be performed. It becomes possible.
[Brief description of the drawings]
FIG. 1 is a configuration diagram illustrating a portion of a memory cell array in a semiconductor memory device according to a first embodiment of the present invention;
FIG. 2 is a block diagram for extracting and explaining a portion related to a redundant configuration in the semiconductor memory device according to the first embodiment of the present invention;
FIG. 3 is a circuit diagram showing details of an example of a determination circuit (A) in FIG. 2;
FIG. 4 is a diagram for comprehensively explaining the operation of the memory in the semiconductor memory device according to the first embodiment;
FIG. 5 is a block diagram for extracting and explaining a portion related to a redundant configuration in a semiconductor memory device according to a second embodiment of the present invention;
FIG. 6 is a circuit diagram illustrating details of an example of a determination circuit of FIG. 5;
FIG. 7 is a circuit diagram showing details of an example of a fuse latch group (A) in FIG. 2;
8 is a circuit diagram showing details of an example of a fuse latch circuit forming the fuse latch group (A) of FIG. 7;
9 is an operation waveform diagram of each output signal in the fuse latch circuit of FIG.
FIG. 10 is a circuit diagram showing details of an example of a fuse latch group (A) and a fuse latch group (B) in FIG. 2;
FIG. 11 is a block diagram for extracting and explaining a portion related to a redundant configuration in a semiconductor memory device according to a fifth embodiment of the present invention;
12 is a circuit diagram showing details of an example of a fuse latch group (A) and a fuse latch group (B) in FIG. 11;
FIG. 13 is a circuit diagram showing details of an example of a fuse latch group (A) and a fuse latch group (B) in the semiconductor memory device of the seventh embodiment.
FIG. 14 is a principle explanatory diagram for explaining a rescue method in an example of a conventional semiconductor memory device.
[Explanation of symbols]
1 normal memory cell array, 2 spare row blocks (A), 3 spare row blocks (B), 4 spare rows (C), 5 spare rows (D), 6 decoders, 7 decoders (A), 8 decoders (B), 9 decoders (C), 10 decoders (D), 11 decision circuits (A), 12 decision circuits (B), 134 input OR circuits, 14 fuse latch groups (A), 15 fuse latch groups (C), 16 fuse latch groups (B), 17 fuse latch group (D), 18 reset signal SFC generation circuit, 19 power-on reset circuit, 20, 21, 32 to 342 two-input EXNOR circuit, 22, 24, 35, 37, 39, 40, 51 -1 2-input AND circuit, 23, 36 3-input AND circuit, 30 judgment circuit, 31 3-input OR circuit, 38, 78, 79, 86, 88, 89, 90 2-input Power OR circuits, 41-1,. . . 41-n fuse latch circuits (FLA1) to (FLAn), 42 fuse latch circuits (FLAE), 43-1,. . . 43-n, 44, 49-1,. . . 49-n, 50 fuse elements FS, 45-1,. . . 45-n, 46, 51-2,. . . 51-n, 52, 84-1,. . . 84-q, 85 2-input NAND circuits, 47-1,. . . 47-n fuse latch circuits (FLB1) to (FLBn), 48 fuse latch circuits (FLBE), 60 pulse generation circuits, 61 P-channel MOS transistors, 62 N-channel MOS transistors, 63 external power supply nodes, 64 transfer gates, 65 to 65 69, 87 inverter, 70 row decoder, 71 column decoder, 72 row decoder (A), 73 row decoder (C), 74 column decoder (B), 75 spare column block (B), 76 spare column (D), 77 Column decoder (D), 80 Intersecting areas of spare row block (A) 2 and spare column block (B) 75, 82-1,. . . 82-q fuse latch circuits (FLB1) to (FLBq), 83 fuse latch circuits (FLBE), 100 first address storage circuit, 101 first redundancy decoder, 102 second address storage circuit, 103 second redundancy decoder.

Claims (11)

A plurality of memory cells,
A first redundancy circuit for replacing and repairing a defective memory cell generated in the plurality of memory cells in block units;
A second redundant circuit for replacing and replacing a defective redundant memory cell generated in the first redundant circuit in a unit of row or column;
A redundancy control circuit for selectively activating one of the first redundancy circuit and the second redundancy circuit when the defective memory cell is designated as an access target;
The redundancy control circuit,
A first program circuit arranged corresponding to the first redundant circuit and storing an upper address of address information for specifying the defective memory cell;
A second program circuit arranged corresponding to the second redundant circuit and storing a lower address of address information specifying the defective redundant memory cell;
Activating the first redundant circuit when an upper address of the defective memory cell stored in the first program circuit is designated as the access target;
When the first redundant circuit is activated and the lower address of the defective memory cell stored in the second program circuit is designated as the access target, the second redundant circuit is activated. And a determination circuit for inactivating the first redundant circuit. The determination circuit includes:
A first comparison circuit that performs a match comparison operation between the upper address and an address signal for indicating the access target, and outputs a first match / mismatch determination signal;
A second comparison circuit that performs a match comparison operation between the lower address and an address signal for indicating the access target, and outputs a second match / mismatch determination signal;
Means for receiving the first and second match / mismatch determination signals and selecting activation / inactivation of the first and second redundant circuits,
The second comparison circuit, upon receiving the first match determination signal from the first comparison circuit, performs a match comparison operation and outputs the second match / mismatch determination signal;
The selection means, when receiving the first match determination signal and the second match determination signal, deactivates the first redundant circuit and activates the second redundant circuit. The semiconductor memory device according to claim 1. The first program circuit includes:
N first program elements for nonvolatilely storing address information that specifies n (n: natural number) bits of defective address bits forming an upper address of the defective memory cell;
A second program element for nonvolatilely storing an enable signal for activating the first redundant circuit;
(N + 1) first logic elements for outputting storage information of the first and second program elements to the determination circuit,
The second program circuit includes:
M number of third program elements for nonvolatilely storing address information for specifying a defective address bit composed of m (m: natural number) bits constituting a lower address of the defective memory cell;
A fourth program element for nonvolatilely storing an enable signal for activating the second redundant circuit;
2. The semiconductor memory device according to claim 1, further comprising: (m + 1) second logic elements for outputting storage information of said third and fourth program elements to said determination circuit. The first and second program circuits further include:
Means for inputting a reset signal for initializing the stored contents of the first to fourth program elements to each of the first to fourth program elements and the first and second logic elements when an external power supply voltage is applied With
The reset signal is
At a predetermined period after the external power supply voltage is turned on, the first logic level is attained, the storage contents of the first to fourth program elements are initialized, and after the predetermined period has passed, the second logic level is attained. Transition to normal operation state,
The first and third program elements store address information specifying the defective address bit when the reset signal of the second logic level is input,
4. The second and fourth program elements according to claim 3, wherein when the reset signal of the second logic level is input, an enable signal for activating the first and second redundant circuits is stored. Semiconductor storage device. When the first and second logic elements receive the reset signal of the second logic level, the first and second logic elements include address information specifying the defective address bits stored in the first and third program elements, and 5. The semiconductor memory device according to claim 4, wherein an enable signal for activating said first and second redundancy circuits stored in second and fourth program elements is output to said determination circuit. Test mode means for obtaining address information for specifying the defective redundant memory cell stored in the second program circuit,
At the time of entry of the test mode means, a predetermined upper address stored in the first program circuit is designated as an access target to activate the first redundant circuit, and a redundant memory cell in the first redundant circuit is activated. 2. The semiconductor memory device according to claim 1, wherein an operation test is performed by sequentially designating lower addresses specifying the address as a target to be accessed. Test mode means for obtaining address information for specifying the defective redundant memory cell stored in the second program circuit,
The test mode means includes:
A test entry signal input means for entering a test mode;
When the test entry signal is input during a predetermined period after the external power supply voltage is turned on, the first program circuit fixes the reset signal to a first logic level and sets each of the first logic elements And enter
When the first logic element receives the reset signal of the first logic level, the first logic element stores address information for specifying a predetermined upper address stored in the first program element and storage of the second program element. And outputting an enable signal for activating the first redundant circuit to the determination circuit.
When the predetermined upper address is designated as an access target, the determination circuit activates the first redundant circuit, and sequentially accesses lower addresses specifying redundant memory cells in the first redundant circuit as access targets. 5. The semiconductor memory device according to claim 4, wherein an operation test is performed by designating the following. The predetermined upper address and an enable signal for activating the first redundant circuit are uniquely specified by the reset signal of the first logic level, and depend on storage information of the first and second program elements. 8. The semiconductor memory device according to claim 7, wherein said memory device is not used. Test mode means for obtaining address information for specifying the defective redundant memory cell generated in the plurality of first redundant circuits,
At the time of entry of the test mode means, by specifying a predetermined upper address stored in the first program circuit corresponding to one of the plurality of first redundant circuits as the access target, 7. The semiconductor memory device according to claim 6, wherein said redundant circuits are sequentially activated, and an operation test is performed with the redundant memory cells in said activated first redundant circuit as access targets. 10. The semiconductor memory device according to claim 9, wherein said predetermined upper address is specified in a mismatch with each other in said first program circuit corresponding to each of said plurality of first redundant circuits. In the first program circuit corresponding to each of the plurality of first redundancy circuits, the first logic element in one first program circuit and the first logic element in another first program circuit The semiconductor memory device according to claim 10, wherein said semiconductor memory device is different from said element.

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