KR20000042391A - Fabrication method of full cmos sram cell - Google Patents

Abstract

PURPOSE: A method for fabricating a full CMOS SRAM cell is provided to decrease the number of conductive layers and to reduce fabrication cost. CONSTITUTION: In a full CMOS cell wherein PMOS transistors are formed on a silicon substrate, the fabrication begins with a formation of a p-well, an n-well, and a field oxide(11) in the substrate. Next, a gate oxide layer(13) and a first polysilicon layer are formed, and then a gate(Q3) and a word line(P1) are formed from a selective etch of the first polysilicon layer. Next, after sidewall spacers(14) and source/drain regions(12) are formed, a nitride layer(15) covers overall surfaces and a first interlayer dielectric(16) is formed thereon. Then, the nitride layer(15) and the first dielectric(16) are selectively etched to form holes for local interconnection wiring(18A) and power supply(18B). At this time, the nitride layer(15) stops the etching, and therefore the spacers(14) are not damaged. Next, a metal layer such as tungsten is formed and selectively etched to form the local interconnection wiring(18A) and the power supply(18B). Next, a second interlayer dielectric(19) and bit lines(20) are formed.

Description

Full CMOS SRAM Cell Manufacturing Method

TECHNICAL FIELD The present invention relates to the field of semiconductor device manufacturing, and more particularly, to a full CMOS SRAM cell.

As shown in FIG. 1, a cell of an SRAM device basically has a structure in which six transistors are connected to each other. In Fig. 1, W / L is a word line, Bit is a bit line, / Bit is a bit bar line, Q1 and Q2 are PMOS transistors, Q3 and Q4 are driver transistors, and Q5 and Q6 are access transistors. transistor), Vcc denotes a supply power line, and Vss denotes a ground power line. The driver transistor and the access transistor are both NMOS transistors.

Q1 and Q2 shown in FIG. 1 can be configured as resistors instead of PMOS transistors. Such SRAMs are referred to as High Resistor Load (HLR) cells. In the case of configuring SRAMs as thin film transistors, a thin film transistor (TFT) is used. The PMOS transistor is formed on a silicon substrate as shown in FIG. 1 and is referred to as a full CMOS cell.

Among the full CMOS cells, since all six transistors are located on a silicon substrate, the performance is superior to other types of cells. However, the full CMOS cell has a large area occupied by one cell, which makes it difficult to improve the device integration.

In order to suppress the cost increase of the product caused by the increased cell size, it is necessary to reduce the cell area or simplify the process. The most essential element in an SRAM cell is a local interconnection contact that locally connects the transistor's gate and active region (node).

In addition, in the structure of the conductive layer forming the SRAM cell, the first polysilicon film P1 used as the gate electrode and the word line of the transistor, the first power supply line Vcc and the first power source used as the ground power supply line Vss There is a metal film and a second metal film used as a bit line. In addition, a third metal layer for word line strapping or global word line through the cell region may be used to improve the operating characteristics of the entire circuit, although not directly related to the characteristics of the cell. have. Therefore, it is formed as a multi-layered structure consisting of one layer of polysilicon film and three layers of metal film as a whole. The more the number of metal layers, the longer the process, the higher the product cost and the more difficult it is to secure the reliability of the metal layer. There is a need for an SRAM manufacturing method that can reduce cost and contribute to improved yield.

The present invention devised to solve the above problems is to provide a full CMOS SRAM cell manufacturing method that can reduce the number of conductive layers to reduce the process steps and manufacturing costs.

1 is a full CMOS SRAM cell circuit diagram;

2a to 2d is an SRAM cell layout according to the present invention,

3A to 3G are cross-sectional views of an SRAM cell manufacturing process according to an embodiment of the present invention.

* Explanation of reference numerals for the main parts of the drawings

active: active region P1: first polysilicon film

Metal1: first metal film Metal2: second metal film

M1C: first metal contact M2C: second metal contact

11: field oxide film 12: high concentration source and drain

13: gate oxide film 14: insulating film spacer

15: nitride film 16: first interlayer insulating film

17A: Locally-connected contact hole 17B: First metal contact hole

18A: Local connection wiring 18B: Supply power line

19: second interlayer insulating film 20: second metal film

The present invention for achieving the above object is a first step of forming an n well and p well in the semiconductor substrate, forming a device isolation film; A second step of forming a gate oxide film and a polysilicon film on the semiconductor substrate on which the first step is completed, and selectively etching the polysilicon film to form a polysilicon film pattern forming a gate and a word line of the transistor; A third step of forming a first interlayer insulating film on the entire structure of which the second step is completed; Selectively etching the first interlayer insulating layer to form a local connection contact hole and a first metal contact hole exposing a gate and an active region of a transistor; Forming a first metal film on the entire structure where the fourth step is completed, selectively etching the first metal film to form a supply power supply line and a ground power supply line, and at the same time, retaining the first metal film in the local connection contact hole. A fifth step of forming a local connection wiring; And a sixth step of forming a second interlayer insulating film and a second metal film to form a bit line on the entire structure where the fifth step is completed.

In addition, the present invention for achieving the above object is a first step of forming an n well and p well in the semiconductor substrate, forming a device isolation film; A gate oxide film and a polysilicon film are formed on the semiconductor substrate on which the first step is completed, and the polysilicon film is selectively etched to form a polysilicon film pattern forming a gate and a word line of the transistor, and ions for forming a low concentration source and drain are formed. A second step of performing an injection process; Forming an insulating film spacer on the sidewalls of the polysilicon film pattern, and performing an ion implantation process for forming a high concentration source and a drain; A fourth step of forming an etch stop film and a first interlayer insulating film on the entire structure in which the third step is completed; A fifth step of selectively etching the first interlayer insulating layer and the etch stop layer to form a local connection contact hole and a first metal contact hole exposing a gate and an active region of a transistor; Forming a first metal film on the entire structure of the fifth step is completed, selectively etching the first metal film to form a supply power supply line and a ground power supply line, and at the same time to leave a first metal film in the local connection contact hole A sixth step of forming a local connection wiring; And a seventh step of forming a second interlayer insulating film and a second metal film forming a bit line on the entire structure in which the sixth step is completed.

In order to simplify the process of manufacturing a full CMOS SRAM cell, the present invention is a first metal film that forms a supply power line and a ground power line, and includes a gate and an active region (node) of a transistor, which is an essential element in an SRAM cell configuration. It is characterized by reducing the number of metal layers by forming a local connection contact to connect the locally.

In a method of manufacturing a full CMOS SRAM cell according to an embodiment of the present invention, a gate and a word line of a transistor are formed of a first polysilicon layer, and a supply power line, a ground power line, a word line strapping, and a global word line are used. In the process of forming the first metal film to form a local connection wiring, the bit line is formed of a second metal film.

Hereinafter, a full CMOS SRAM cell manufacturing method according to an embodiment of the present invention will be described with reference to the accompanying drawings.

2A to 2D are layouts of a full CMOS SRAM cell according to an embodiment of the present invention, and FIGS. 3A to 3G are full CMOS SRAM cells along a line XX ′ of FIGS. 2A to 2D. It is a manufacturing process cross section.

First, as shown in FIGS. 2A and 3A, n-well and p-well are formed in a silicon substrate, and an isolation process is performed to form a field oxide film 11.

Next, as shown in FIGS. 2B and 3B, the gate oxide layer 13 and the first polysilicon layer are formed on the silicon substrate, and the gate polysilicon layer is selectively etched to form the gate Q3 and the word line of the transistor. After forming the first polysilicon layer pattern, an ion implantation process for forming a source and a drain is performed.

Next, as shown in FIG. 3C, an insulating film spacer 14 is formed on the sidewalls of the first polysilicon film pattern, and an ion implantation process for forming a high concentration source and drain 12 is performed.

Next, as shown in FIG. 3D, the nitride film 15 is formed on the entire structure to be used as an etch stop film for etching the contact hole, and the first interlayer insulating film 16 is formed on the nitride film 15. Form.

Next, as illustrated in FIGS. 2B and 3E, the first interlayer insulating film 16 and the nitride film 15 are selectively etched to form a local connection contact hole 17A, and the first interlayer insulating film 16 and the nitride film are formed. 15 and the gate oxide film 13 are selectively etched to form a first metal contact hole 17B. At this time, the etching is stopped by the nitride film 15 under the first interlayer insulating film 16, and the insulating film spacer 14 is not damaged. If the first interlayer insulating film is etched to form the local connection contact hole 17A and the first metal contact hole 17B without forming the nitride film 15, the insulating layer spacer 13 is also etched to form the local connection contact hole ( 17A) and the first metal contact hole 17B are exposed to the silicon substrate instead of the active region to cause contact leakage. In order to reduce such contact leakage, a high concentration impurity ion implantation process is separately performed. In the case of forming a nitride film etch stop layer, the ion implantation process for reducing contact leakage in the active region can be omitted, thereby simplifying the process. .

Next, as shown in FIGS. 2C and 3F, a tungsten film is formed of the first metal film on the entire structure, and the supply power supply line, the ground power supply line and the word line strapping and the global word line are formed on the first metal film. Defining a photoresist pattern (not shown), and etching the first metal film using the photoresist pattern as an etch mask to form a supply power supply line 18B, a ground power supply line and a word line strapping, and a global word line. The first metal film is left in the connection contact hole 17A to form a local connection wiring 18A. Next, the photosensitive film pattern is removed.

Next, as shown in Figs. 2D and 3G, the second interlayer insulating film 19 is formed over the entire structure, and the bit lines are formed of the second metal film 20. Figs.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

The present invention as described above is a first metal film forming a supply power supply line and a ground power supply line, a local connection contact for locally connecting a gate and an active region (node) of a transistor, which is a key element in the SRAM cell configuration. By forming, the number of metal layers can be reduced, process steps can be reduced, and the possibility of various defects can be reduced.

In addition, an insulating layer spacer formed on the sidewalls of the first polysilicon layer pattern may be damaged in the first interlayer dielectric layer etching process to form a nitride layer, which is an etch stop layer, under the first interlayer dielectric layer. This can prevent the increase in contact leakage.

Claims (4)

A method of manufacturing a full CMOS SRAM cell, Forming a n well and a p well in the semiconductor substrate and forming an isolation layer; A second step of forming a gate oxide film and a polysilicon film on the semiconductor substrate on which the first step is completed, and selectively etching the polysilicon film to form a polysilicon film pattern forming a gate and a word line of the transistor; A third step of forming a first interlayer insulating film on the entire structure of which the second step is completed; Selectively etching the first interlayer insulating layer to form a local connection contact hole and a first metal contact hole exposing a gate and an active region of a transistor; Forming a first metal film on the entire structure where the fourth step is completed, selectively etching the first metal film to form a supply power supply line and a ground power supply line, and at the same time, retaining the first metal film in the local connection contact hole. A fifth step of forming a local connection wiring; and A sixth step of forming a second interlayer insulating film and a second metal film forming a bit line on the entire structure in which the fifth step is completed; Full CMOS SRAM cell manufacturing method comprising a. In the method of manufacturing a Paul CMOS SRAM cell (full CMOS SRAM cell), Forming a n well and a p well in the semiconductor substrate and forming an isolation layer; A gate oxide film and a polysilicon film are formed on the semiconductor substrate on which the first step is completed, and the polysilicon film is selectively etched to form a polysilicon film pattern forming a gate and a word line of the transistor, and ions for forming a low concentration source and drain are formed. A second step of performing an injection process; Forming an insulating film spacer on the sidewalls of the polysilicon film pattern, and performing an ion implantation process for forming a high concentration source and a drain; A fourth step of forming an etch stop film and a first interlayer insulating film on the entire structure in which the third step is completed; A fifth step of selectively etching the first interlayer insulating layer and the etch stop layer to form a local connection contact hole and a first metal contact hole exposing a gate and an active region of a transistor; Forming a first metal film on the entire structure of the fifth step is completed, selectively etching the first metal film to form a supply power supply line and a ground power supply line, and at the same time to leave a first metal film in the local connection contact hole A sixth step of forming a local connection wiring; And A seventh step of forming a second interlayer insulating film and a second metal film forming a bit line on the entire structure in which the sixth step is completed; Full CMOS SRAM cell manufacturing method comprising a. The method of claim 2, In the sixth step A full CMOS SRAM cell manufacturing method comprising forming word line strapping and a global word line. The method of claim 2 or 3, And forming the first metal film into a tungsten film.