KR100287164B1 - Semiconductor device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a fabrication method thereof are provided to reduce a dimension per a cell, to prevent a counter diffusion of an N+/P+ impurity using an inherent property and to obtain a low contact resistance. CONSTITUTION: A gate oxide layer and a lower conductive layer are formed on a substrate. A contact hole is formed by patterning the gate oxide layer and the lower conductive layer to form an impurity region. An N+ impurity region(5) and a P+ impurity region(6) are formed by implanting an impurity ion at the impurity region. A diffusion preventing layer is formed on a side and top surface of the contact hole and the lower conductive layer, thereby connecting N+ impurity region and P+ impurity region. An upper conductive layer is formed onto the diffusion layer. The lower conductive layer, the diffusion preventing layer and the upper conductive layer are patterned at simultaneously.

Description

Semiconductor device and manufacturing method thereof

1 is a circuit diagram of a typical SRAM (Stactic Radom Access Memory) cell to which the prior art and the present invention are applied.

2 and 3 are plan views showing the layout of the SRAM cell according to the conventional method.

4 is a cross-sectional view of the SRAM cell according to ⓐ-ⓐ ′ in FIG. 2.

5 is a cross-sectional view of the SRAM cell taken along line ⓐ-ⓐ 'of FIG.

6 is a plan view showing the layout of the SRAM cell according to the present invention.

7 is a cross-sectional view taken along line ⓐ-ⓐ 'of FIG. 6 showing the structure of the SRAM cell fabricated by the present invention.

8a to 8d are manufacturing process diagrams according to the process sequence showing an embodiment according to the present invention.

9 is a cross-sectional view showing another structure of an embodiment according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a local interconnect structure of a semiconductor device and a method of manufacturing the same.

Local interconnect structures are increasingly becoming a major limitation in the manufacture of highly integrated circuits. In particular, the interconnection between a multi-layer polysilicon layer or a metal layer and a source or drain region of a semiconductor substrate has become very difficult due to problems such as etching of contact holes, damage and contamination during etching of contact holes, and planarization of an intermediate insulating layer. Techniques for modifying buried contact processes have been attempted with respect to the above local connection structures. The investment contact process related to the MOS gate structure includes a process of separating a polysilicon or polyside layer from a gate oxide film to form a MOS gate electrode or directly connecting to a contact region of a MOS transistor. In connection with the above-mentioned investment contact process, there are the following problems.

First of all, in order to form a conductive gate electrode, a semiconductor device may dope a gate electrode with a second conductive impurity (for example, P or As), and there is a problem of contamination and reliability of the gate oxide layer due to the doped impurity.

Second, as the degree of integration of semiconductor devices increases, semiconductor devices are likely to cause leakage current and contact resistance (e.g. source, surface of drain region, gate electrode) due to outward diffusion of impurities doped into the gate electrode. There is a problem of increasing and adjusting the contact resistance of the surface.

Third, in the use of CMOS (Complimentary Metal Oxide Semiconductor) technology, in particular, semiconductor devices have a problem of increasing contact resistance of P + impurity regions due to diffusion of impurities when N + impurity regions and P + impurity regions of a semiconductor substrate are interconnected.

The problem of interdiffusion contact resistance is described in "Dual N + / P + polycide interconnect technology using poly-silicon / Wsi ₂ / poly-silicon and post B + implantion" international ELECTRON DEVICE meeting (idem), 1992, p845-848. Is disclosed.

On the other hand, a technique for reducing contact resistance in local interconnection is known a self-aligned titanium silicide (TiSi ₂ ) process. The self-aligned titanium silicide (TiSi ₂ ) process is disclosed in ("Titanium Nitride Local interconnect Technology for VLSI" IEEE transaction on Electron Device Vol.ED-34, Martch, 1987, p682-687). It is.

The self-aligned titanium silicide (TiSi ₂ ) process deposits metallic titanium on the entire surface of the semiconductor substrate and reacts with the silicon surface in a nitrogen atmosphere to form TiSi ₂ to reduce contact resistance. In addition, the technique of partially modifying the titanium silicide (TiSi ₂ ) process forms a titanium nitride (TiN) film when titanium (Ti), which is not in contact with the silicon surface, is formed. The formed TiN film is patterned and used as an interconnect layer. Reduce resistance. The TiN is a conductive material and is known as a diffusion barrier upon contact.

Hereinafter, a conventional technique for reducing contact resistance and interdiffusion between the N + impurity region and the P + impurity region in local interconnection will be described.

On the other hand, SRAM (static radom acess memory), which is one of the current semiconductor high-density devices, has a cell structure that connects the N + impurity region and the P + impurity region in local interconnection. Therefore, the prior art description uses the SRAM cell, and the description of the present invention described later also uses the SRAM cell.

In general, SRAM cells include four-transistor NMOS method using high-resistance polysilicon as a load and six-transistor CMOS method using a PMOS transistor as a load.

The four-transistor method is advantageous in device integration, while the six-transistor CMOS method has many advantages, such as low standby power, noise immunity, and operation over a wide temperature range, which are very important in highly integrated semiconductor devices. However, the six-transistor method requires a large area to separate the NMOS transistor and the PMOS transistor, and the same design rule has a problem that the cell area is more than twice the cell area of the high-resistance polysilicon. In addition, since polysilicon is directly interconnected to the N + / P + impurity region, there is a problem that it is difficult to form a low contact resistance of the P + contact region. Therefore, in order to take advantage of the six-transistor method, it is necessary to solve the problem of the six-transistor method.

Here, the local interconnection method of the PMOS load element and the NMOS driving transistor of the conventional SRAM will be described.

1 is a circuit diagram of a typical flip-flop type SRAM (Stactic Radom Access Memory) cell applied to the prior art or the present invention.

In FIG. 1, two loads and four N-channel MOS transistors are shown. The loads P1 and P2, the NMOS driving transistors N1 and N2, and the NMOS transfer transistors N3 and N4 are shown. The loads P1 and P2 use PMOS transistors which flow less current than resistors. The power supply voltage VDD is connected to the PMOS load transistors P1 and P2, and the ground voltage VSS is connected to the NMOS driving transistors N1 and N2. The NMOS transfer transistors N3 and N4 are connected to the word line WL and the bit lines BL and BL (bar). The six-transistor SRAM cell is a flip-flop circuit that is composed of a first inverter (including P1 and N1) and a second inverter (including P2 and N2).

2 is a plan view showing the layout of the SRAM cell according to the prior art.

As shown in FIG. 2 to FIG. 1, PMOS load transistors P1 and P2, NMOS driving transistors N1 and N2, and NMOS transfer transistors N3 and N4 are shown. The power supply voltage VDD is connected to the PMOS load transistors P1 and P2, and the ground voltage VSS is connected to the NMOS driving transistors N1 and N2. NMOS transfer transistors N3 and N4 are connected to word lines and bit lines.

In particular, the prior art of FIG. 2 uses a metal or polysilicon jumper (indicated by jumbers, MJ1, MJ2) when connecting the load transistor and the driving transistor of each inverter, so that a certain space is required, so that the distance between the polysilicon gates It becomes larger and becomes an obstacle to the high integration of a semiconductor device. The layout of FIG. 2 is disclosed in the above-mentioned document (IEEE).

4 is a cross-sectional view briefly showing a cross section taken along line ⓐ-ⓐ ′ in FIG. 2.

In FIG. 4, the N + impurity region 3 and the P + impurity region 4 are connected to each other using polysilicon 5, 6 with the gate oxide film 2 interposed therebetween on the semiconductor substrate 1. In addition, the polysilicon layers 7 and 8 used as the gate electrode and the insulating film 9 are formed.

In particular, the local interconnection between the N + impurity region 3 and the P + impurity region 4 has a problem in that the lateral diffusion of impurities B in the P + impurity region occurs to increase the contact resistance of the P + impurity region. have. In the above-mentioned document (IEDM), three layers of polysilicon are used to prevent the interdiffusion of the P + impurity region and the N + impurity region, and a technique for preventing mutual diffusion by ion implantation of boron in a post-process is proposed. It does not prevent.

3 is a plan view showing the layout of an SRAM cell according to the prior art using titanium nitride.

As shown in FIG. 3 to FIG. 1, PMOS load transistors P1 and P2, NMOS driving transistors N1 and N2, and NMOS transfer transistors N3 and N4 are shown. The power supply voltage VDD is connected to the PMOS load transistors P1 and P2, and the ground voltage VSS is connected to the NMOS driving transistors N1 and N2. NMOS transfer transistors N3 and N4 are connected to word lines and bit lines.

In particular, the prior art of FIG. 3 includes a layer of titanium nitride (denoted as TiN, L1) used as a local interconnect between polysilicon (used as a gate electrode, 1). The titanium nitride is known as a diffusion barrier.

As described above, when the TiN layer is formed, a sufficient distance (b) must be provided to prevent electrical connection between the TiN layers, thereby increasing the area per unit cell, which causes a problem of high integration.

5 is a cross-sectional view taken along line ⓐ-ⓐ 'of FIG.

In FIG. 5, the TiN layer 7 includes an N + impurity region 3 and a P + impurity region 4 with the gate oxide film 2 and the gate electrode 5 formed of polysilicon on the semiconductor substrate 1 interposed therebetween. Was in direct contact with. In addition, an interlayer insulating film 6 is formed to prevent damage during etching of TiN.

TiN used in FIG. 5 is used as a method of N + / P + interconnection because of its low resistance and good diffusion barrier. However, since TiN cannot be used as a gate electrode in the local interconnection of TiN, a manufacturing process according to the following procedure is required.

Iv) Masking and etching to pattern the gate electrode ii) Interlayer insulating film forming to insulate the TiN layer (6) 마스크) Masking and etching at the contact area for contacting TiN iv) Deposition of TiN and TiN Masking and etching are required for patterning.

In the manufacturing process, the formation of the interlayer insulating film, the masking and etching of the contact portion of the TiN can be eliminated. In this case, since the etching selectivity of the TiN and the oxide film is not high when the TiN is etched, the surface of the silicon substrate is damaged and used. I never do that. In addition, since three masks and etching operations must be performed in the manufacturing process sequence, it is necessary to reduce the number of masks and etching processes associated with the gate electrode in accordance with the high integration of the semiconductor devices. It can improve the quality and reliability and reduce the cost and time of semiconductor devices.

Accordingly, an object of the present invention is to provide a semiconductor device having a connection structure capable of reducing the area per unit cell of an SRAM.

Another object of the present invention is to provide a suitable manufacturing method of a semiconductor device having the above connection structure.

In order to achieve the above object, the present invention includes a first impurity region formed on the first portion on the semiconductor substrate; A second impurity region formed in a second portion on the semiconductor substrate; An insulating film formed between the first impurity region and the second impurity region; A lower conductive film formed on the insulating film and having contact holes on the first impurity region and the second impurity region; A diffusion barrier layer formed on a side surface, an upper surface of the contact hole, and the lower conductive layer to connect the first impurity region and the second impurity region; It characterized in that it comprises an upper conductive film formed on the diffusion barrier.

In another aspect, the present invention is the first and second inverter of the SRAM cell formed on the surface of the semiconductor substrate; Each inverter includes a driving transistor having a load element and a semiconductor region; The driving transistor of the first inverter and the load element of the second inverter may include first connection means connected to a diffusion barrier layer; The driving transistor of the second inverter and the load device of the first inverter may include second connection means connected to the diffusion barrier.

In order to achieve the above object, the present invention is a process for forming a gate oxide film and a lower conductive film on a semiconductor substrate; Patterning a portion where an impurity region is to be formed in the gate oxide layer and the lower conductive layer to form a contact hole; Implanting impurities into the impurity region to form an N + impurity region and a P + impurity region; Forming a diffusion barrier layer on the side surface, the upper surface and the lower conductive layer of the contact hole to connect the N + impurity region and the P + impurity region; Forming an upper conductive film on the diffusion barrier film; And patterning the lower conductive film, the diffusion barrier, and the upper conductive film at the same time.

According to the present invention, there is no diffusion barrier used as an interconnect between polysilicon (used as a gate electrode) in local interconnection on a layout. Therefore, the cell area is reduced, which is advantageous for high integration of semiconductor devices.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

6 is a plan view showing the layout of the SRAM according to the present invention.

As shown in FIG. 6 to FIG. 1, two PMOS transistors P1 and P2 and four NMOS transistors N1, N2, N3 and N4 are formed. One gate of one pair of MOS transistors N1 (a first driving MOS transistor and a first PULL-DOWN transistor) and N2 (a second driving MOS transistor and a second PULL-DOWN transistor) PMOS load transistors (first PULL-UP transistor P1, second PULL-UP transistor P2) are used for each drain. The sources of N1 and N2 are fixed to a predetermined potential (ground voltage VSS), and the power supply voltage VDD is applied to the other ends of the PMOS load transistors P1 and P2. The six-transistor SRAM cell consists of a flip-flop circuit that is composed of a first inverter (including P1 and N1) and a second inverter (including P2 and N2). A transfer MOS transistor N3 (first transfer transistor) and N4 (second transfer transistor) are connected to the flip-flop circuit and are connected to the word line WL. The transmission transistor is connected to a pair of bit lines BL and BL (bar) at the output terminal of the inverter.

In particular, the present invention does not have a layer of titanium nitride (denoted as TiN, L1) used as a local interconnect between polysilicon (used as a gate electrode, 1). In addition, the polysilicon layer is divided into a polysilicon layer, a polysilicon-TiN layer, and a TiN layer around the contact area of the prior art (FIG. 3) on the polysilicon. The above and TiN rayout give about 30% of cell area from 0.5 Um design rule to 19.76 Um ² (2.6 × 7.6) of 13.78 Um ² (2.6 × 5.3) of the prior art (Fig. 3 Rayout). Therefore, the TiN reduces the area per unit cell, which is advantageous for high integration of semiconductor devices.

FIG. 7 is a cross-sectional view taken along line ⓐ-ⓐ 'of FIG. 6 showing the structure of the SRAM manufactured by the present invention.

The TiN 6 directly contacts the N + impurity region 3 and the P + impurity region 4 with the gate oxide film 2 and the lower gate electrode 5 formed of polysilicon on the semiconductor substrate 1 interposed therebetween. Cover the lower gate electrode. In addition, an upper gate electrode 7 is formed on the TiN layer. TiN is a material used as a method of N + / P + interconnection in the prior art because of the role of low resistance and good diffusion barrier.

In FIG. 7, the structure of the present invention is the structure of the N + / P + impurity region (region connected to the gate electrode) of the semiconductor substrate (N + / P + impurity region) / TiN layer / gate electrode (TiN / polysilicon). The gate electrode region has a structure of a semiconductor substrate / oxide film / lower conductive film / TiN / top conductive film. The interconnect uses TiN as part of the gate electrode and also utilizes the above described TiN diffusion barrier.

The local interconnection using TiN of the present invention is performed according to the following procedure.

(Ii) polysilicon deposition process to form gate electrode; ii) masking and etching of contact region for contacting TiN; iii) deposition of polysilicon to be deposited as TiN and patterning of gate electrode; Etching is required.

Therefore, the fabrication process of the present invention can reduce the number of mask and etching operations compared to the fabrication process of the prior art (FIG. 5) and achieve a small cell area.

Hereinafter, the embodiment for forming the connection structure of the semiconductor device of the present invention will be described in more detail.

8A to 8F are sectional views showing the manufacturing method of the embodiment of the present invention in the order of a process.

FIG. 8A is a cross-sectional view illustrating the steps of forming and patterning a gate oxide film and a lower gate electrode (lower conductive film) used as gate means.

First, the gate oxide film 1 is formed on the semiconductor substrate (not shown) to a thickness of about 160 kPa by a thermal oxidation method or another conventional method, and then polysilicon is deposited to a thickness of about 1000 kPa by low pressure chemical vapor deposition (LPCVD). The polysilicon is used as a lower gate electrode (lower conductive film 2).

Next, a contact hole is formed in the region to be used as the N + impurity region and the P + impurity region through a predetermined photolithography process. The contact hole is about 0.4 Um in size.

8B is a cross-sectional view illustrating the steps of the ion implantation process for forming the N + impurity region and the P + impurity region.

First, a photoresist is applied through a conventional photolithography process, and the region where the N + impurity region 5 is to be formed is patterned. Next, N-type conductive materials 3 such as As and P are ion-implanted on the entire surface of the semiconductor substrate. The photoresist is applied again through a photographic process to pattern the region where the P + impurity region 6 is to be formed. Next, P-type conductive materials 4 such as BF ₂ and B are ion-implanted on the entire surface of the semiconductor substrate.

Another method for forming the P + / N + impurity region is as follows.

First, P-type or N-type impurities are implanted into the entire surface of the semiconductor substrate. Next, a photoresist is applied through a predetermined photo process, and the N + impurity region 5 or the P + impurity region 6 is patterned, and then only one region of the N + impurity region or the P + impurity region is formed of P-type or N-type impurities. Counter-doping.

In the ion implantation process, in the case of a conventional investment contact, impurities of polysilicon used as interconnects diffuse into the lower portion of the semiconductor substrate during heat treatment in a subsequent process to form N + / P + impurity regions. However, in the present invention, ion implantation is first performed due to TiN formed in a later process and acting as a diffusion barrier.

8C is a cross-sectional view illustrating a step of forming titanium nitride (TiN) serving as a diffusion barrier film and polysilicon used as an upper gate electrode (upper conductive film).

The TiN layer 7 is formed to a thickness of about 6000 kPa by chemical vapor deposition, and then the polysilicon 8 is formed to a thickness of about 1000 kPa by low pressure chemical vapor deposition. The polysilicon is used as an upper gate electrode.

8D is a cross-sectional view illustrating a step of patterning a gate electrode.

The gate electrode is patterned through a predetermined photolithography process, and the patterning of the gate electrode patterns the TiN layer and the second gate electrode on the semiconductor substrate. When formed as described above, the N + / P + impurity region (the region connected with the gate electrode) has the structure of the semiconductor substrate (N + / P + impurity region) / TiN (9) / gate electrode 10. The gate electrode region has a structure of a semiconductor substrate / bottom gate electrode / TiN / top gate electrode. A refractory metal may be further deposited on the upper gate electrode to be used as a gate electrode.

9 is a cross-sectional view showing another structure of the present invention.

9 shows the lower gate electrode 2 and the TiN 3 formed on the impurity regions 4 and 5 and the gate oxide film 1. In FIG. 9, the lower gate electrode 2 and the TiN 3 can be used as the gate electrode without forming the upper gate electrode of FIG. 8d.

As described above, while reducing the area per cell, it is possible to prevent interdiffusion of impurities of N + / P + by using the unique property of TiN and to obtain a low contact resistance.

It is apparent that the present invention is not limited to the above embodiments, and many modifications are possible by those skilled in the art within the technical spirit of the present invention.

Claims (15)

A first impurity region formed in a first portion on the semiconductor substrate; A second impurity region formed in a second portion on the semiconductor substrate; An insulating film formed between the first impurity region and the second impurity region; A lower conductive film formed on the insulating film and having contact holes on the first impurity region and the second impurity region; A diffusion barrier layer formed on a side surface, an upper surface of the contact hole, and the lower conductive layer to connect the first impurity region and the second impurity region; And an upper conductive film formed on the diffusion barrier film. The semiconductor device according to claim 1, wherein the first impurity region is formed of an N-type impurity. The semiconductor device according to claim 1, wherein said second impurity region is formed of a P-type impurity. The semiconductor device according to claim 1, wherein the lower conductive film is made of polysilicon. The semiconductor device according to claim 1, wherein the upper conductive film is made of polysilicon. The semiconductor device according to claim 1, wherein the upper conductive film is made of a polyside composed of polysilicon and refractory metal. The semiconductor device according to claim 1, wherein the diffusion barrier is formed of titanium silicide (TiN). The semiconductor device according to claim 1, wherein said insulating film is formed of an oxide film. First and second inverters of the SRAM cell formed on the surface of the semiconductor substrate; Each of the inverters includes a driving transistor having a load element and a semiconductor region; The driving transistor of the first inverter and the load element of the second inverter may include first connection means connected to a diffusion barrier layer; And a second connecting means connected to the driving transistor of the second inverter and the load element of the first inverter by a diffusion barrier. The semiconductor device according to claim 9, wherein the load element is formed of a PMOS transistor. The semiconductor device according to claim 9, wherein the driving transistor is formed of an NMOS transistor having a semiconductor region doped with an N-type impurity. Forming a gate oxide film and a lower conductive film on the semiconductor substrate; Patterning a portion where an impurity region is to be formed in the gate oxide layer and the lower conductive layer to form a contact hole; Implanting impurities into the impurity region to form an N + impurity region and a P + impurity region; Forming a diffusion barrier layer on the side surface, the upper surface and the lower conductive layer of the contact hole to connect the N + impurity region and the P + impurity region; Forming an upper conductive film on the diffusion barrier film; And simultaneously patterning the lower conductive film, the diffusion barrier film, and the upper conductive film. The method of claim 12, wherein the lower conductive film, the diffusion barrier film, and the upper conductive film are used as gate electrodes. Forming a gate oxide film and a lower conductive film on the semiconductor substrate; Patterning a portion where an impurity region is to be formed in the gate oxide layer and the lower conductive layer to form a contact hole; Implanting impurities into the impurity region to form an N + impurity region and a P + impurity region; Forming a diffusion barrier layer on the side surface, the upper surface and the lower conductive layer of the contact hole to connect the N + impurity region and the P + impurity region; And patterning the lower conductive film and the diffusion barrier film. 15. The method of claim 14, wherein the lower conductive film and the diffusion barrier film are used as gate electrodes.