KR20000041297A - Flip flop - Google Patents

Abstract

PURPOSE: A flip flop is provided to reduce a power consumption by reducing the number of transistors which get transient according to a clock signal. CONSTITUTION: A flip flop comprises first to fourth CMOS inverter circuits. The first inverter circuit inverts an input data signal(D), and consists of two PMOS transistors(MP7,MP8) and an NMOS transistor(MN8) which are connected in series between a power supply voltage(VDD) and a reference voltage(Vss). An input data signal(D) is applied in common to the gates of the transistors(MP7,MN8), and a clock signal(CK) is applied to the gate of the transistor(MP8). The second inverter circuit inverts an output of the first inverter circuit, and consists of two PMOS transistors(MP9,MP10) and two NMOS transistors(MN9,MN10) which are connected in series between the power supply voltage(VDD) and the reference voltage(Vss). The gates of the transistors(MP10,MN10) are connected to receive the clock signal(CK), and the gates of the transistors(MP10,MN9) are connected to receive a reset signal(RS) and the output of the first inverter circuit, respectively. The third inverter circuit consists of a PMOS transistor(MP11) and two NMOS transistors(MN12,MN13) which are connected in series between the power supply voltage(VDD) and the reference voltage(Vss). The gates of the transistors(MP11,MP12) are connected to receive an output of the second inverter circuit, and the gate of the transistor(MN13) is connected to receive the clock signal(CK). An NMOS transistor(MN11) is connected between the output of the second inverter circuit and the reference voltage(Vss), and is turned on and off by the reset signal(RS).

Description

Low Power Consumption Flip-Flops

TECHNICAL FIELD The present invention relates to flip-flops, and more particularly, to low power consumption flip-flops that consume low power.

Various latches or flip-flops used in current integrated circuit designs are designed according to their purpose. That is, a latch or flip-flop can be designed in two aspects, the first of which is a functional aspect of designing a latch or flip-flop to perform a desired operation, and the second of which design a latch or flip-flop in consideration of characteristics. At this time, the main concern is how much power is consumed in the latch or flip-flop, or how fast it operates. In particular, low power consumption is a very important requirement in chargers and batteries used in communication products.

As a result, the need for reducing the power consumption of the latch or flip-flop that can be applied to the above-described products, for example, is more urgently needed, and research on this is being actively conducted.

An object of the present invention is to provide a low power consumption flip-flop that reduces the number of transistors transitioned in response to a clock signal.

1 is a circuit diagram of one preferred embodiment of a low power consumption T flip-flop according to the present invention.

2 (a) to 2 (c) are waveform diagrams for explaining the operation of the flip-flop shown in FIG.

3 is a circuit diagram of a preferred embodiment of a low power consumption D flip-flop according to the present invention.

4 is a graph for comparing the power dissipation of the conventional flip-flop and the flip-flop according to the present invention.

The low power consumption flip-flop according to the present invention for achieving the above object, the first complementary MOS transistor (CMOS) transistor inverted and outputs the input data, and is connected between the power supply and the reference potential, the clock signal A first MOS transistor forming a current path of the first CMOS transistor, a second CMOS transistor inverted and outputting the clock signal, connected between the supply power supply and the reference potential, and responding to the inverted data. A second MOS transistor forming a current path of the second CMOS transistor, a third CMOS transistor inverting the inverted clock signal and outputting it as a negative output, and a current path of the third CMOS transistor in response to the clock signal. It is preferable that it is comprised with the 3rd MOS transistor which forms the structure.

In general, power consumed in a digital integrated circuit (POWER) can be expressed as Equation 1 below.

POWER = CURRENT * VDD

Here, CURRENT represents current and VDD represents supply power. In this case, the charge amount Q may be expressed as CURRENT / FREQUENCY or CAPACITANCE * VDD, and Equation 1 is expressed as Equation 2 using this.

POWER = FREQUENCY * CAPACITANCE * VDD ²

At this time, assuming that the power supply VDD and the frequency FREQUENCY are given under the same condition, the power is determined according to the remaining factor, the capacitance (CAPACITANCE). Here, the capacitance refers to the capacitance at a node to which a transistor used when implementing a latch or flip-flop transitions.

In general, the most power-consuming portion of a latch or flip-flop is transistors that transition in response to a clock signal rather than data. That is, a transistor that transitions in response to a clock signal consumes 3 to 4 times more power than a transistor that transitions in response to data. This is because, in general, data is given an irregular value in comparison to a clock signal. As such, the amount of power consumed by transistors that transition in response to a clock signal accounts for approximately 20-40% of the power consumption of the system in which the flip-flop is used.

Hereinafter, the configuration and operation of a low power consumption flip-flop according to the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of a preferred embodiment of a low power consumption T flip-flop according to the present invention, and includes a first CMOS transistor and a second PMOS transistor including a first PMOS transistor MP1 and a first NMOS transistor MN1. The second CMOS transistor, the second NMOS transistor MN2, the fourth NMOS transistor MN4 including the MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the third NMOS transistor MN3. A third CMOS transistor including a fifth PMOS transistor MP5 and a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a sixth PMOS transistor MP6, and a seventh NMOS transistor MN7. 4 CMOS transistors.

The flop flop according to the present invention shown in FIG. 1 has a gate connected to the previously outputted negative output QB (t), a source and a drain connected between the supply power supply VDD and the first node N1. A second PMOS transistor MP2 having a first PMOS transistor MP1, a gate connected to the clock signal CK, a source and a drain connected between the first node N1 and the second node N2, A first NMOS transistor MN1 having a gate connected to the previous negative output QB (t), a drain and a source connected between the second node N2 and the reference potential VSS, and a clock signal CK. A fourth PMOS transistor MP4 having a gate connected to the gate, a source and a drain connected between the supply power supply VDD and the third node N3, a gate connected to the second node N2, and a third node ( A second NMOS transistor MN2 having a drain and a source connected between N3 and the fourth node N4, a gate connected to the clock signal CK, and a fourth node N4. The third NMOS transistor MN3 having a drain and a source connected between the reference potential VSS, the gate connected to the third node N3, the supply power supply VDD, and the current negative output QB (t + 1). )] Fifth PMOS transistor MP5 having a source and a drain connected therebetween, a gate connected to the third node N3, a current negative output QB (t + 1) and a fifth node N5 A fifth NMOS transistor MN5 having a drain and a source connected therebetween and a gate connected to the clock signal CK, a sixth having a drain and a source connected between the fifth node N5 and the reference potential VSS It consists of an NMOS transistor MN6. At this time, CMOS transistors MP6 and MN7 may be further provided to obtain the positive output Q (t + 1) from the current negative output QB (t + 1).

In this case, when the reset signal RS is applied to the flip flop illustrated in FIG. 1, the flip flop illustrated in FIG. 1 may include a gate, a supply power supply VDD, and a fourth PMOS transistor connected to the reset signal RS. A third PMOS transistor MP3 having a source and a drain connected between the sources of MP4 and a gate connected to the reset signal RS, a drain connected between the third node N3 and the reference potential VSS, and A fourth NMOS transistor MN4 having a source may be further provided.

Looking at the operation of the flip-flop shown in Figure 1 through the above configuration, as follows.

2 (a) to 2 (c) are waveform diagrams for explaining the operation of the flip-flop shown in FIG. 1, FIG. 2 (a) shows a waveform diagram of the clock signal CK, and FIG. The waveform diagram of the present positive output Q (t + 1) is shown, and FIG.2 (c) shows the waveform diagram of the current negative output QB (t + 1), respectively.

The first CMOS transistor composed of the transistors MP1 and MN1 inverts the negative output QB (t) previously output from the third CMOS transistor, and outputs the inverted result to the gate of the transistor MN2. At this time, the transistor MP2 inserted between the transistors MP1 and MN1 forms a current path of the first CMOS transistor in response to the clock signal CK shown in FIG.

Similarly, the second CMOS transistor composed of the transistors MP4 and MN3 inverts the clock signal CK shown in FIG. 2 (a) and converts the inverted clock signal to the gates of the transistors MP5 and MN5. Will output At this time, the transistor MN2 inserted between the transistors MP4 and MN3 serves to form a current path of the second CMOS transistor in response to the inverted previous negative output output from the first CMOS transistor.

In addition, the third CMOS transistor including the transistors MP5 and MN5 inverts the clock signal inverted in the second CMOS transistor and outputs the inverted result to the gates of the transistors MP6 and MN6. At this time, the transistor MN6 inserted between the source of the transistor MP5 and the reference potential VSS forms a current path of the third CMOS transistor in response to the clock signal CK shown in FIG. Play a role.

As a result, the current negative output QB (t + 1) shown in FIG. 2 (c) is output from the third CMOS transistor, and from FIG. 2 (b) from the fourth CMOS transistor composed of transistors MP6 and MN7. The current positive output Q (t + 1) shown in Fig. 9) is output. That is, the truth table of the flip-flop shown in FIG. 1 is shown in Table 1 below.

Q (t) CK Q (t + 1) 0 0 0 0 One One One 0 One One One 0

In Table 1, '0' represents a "low" logic level and '1' represents a "high" logic level, respectively.

FIG. 3 is a circuit diagram of a preferred embodiment of a low power consumption D flip-flop according to the present invention, and includes a fifth CMOS transistor and an eighth PMOS transistor including a seventh PMOS transistor MP7 and an eighth NMOS transistor MN8. MP8, a ninth PMOS transistor MP9, a sixth CMOS transistor comprising a tenth PMOS transistor MP10 and a tenth NMOS transistor MN10, a ninth NMOS transistor MN9, an eleventh NMOS transistor MN11, A seventh CMOS transistor comprising an eleventh PMOS transistor MP11 and a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a twelfth PMOS transistor MP12, and a fourteenth NMOS transistor MN14. It consists of 8 CMOS transistors.

The D flip-flop shown in FIG. 2 has the same configuration as the T flip-flop shown in FIG. 1 except for inputting data D from the outside instead of the previous sub output QB (t). That is, the gates of each of the seventh PMOS transistor MP7 and the eighth NMOS transistor MN8 are fed back from each other by a negative output QB (which is different from that of each of the first PMOS transistor MP1 and the first NMOS transistor MN1). t)] is instead connected to the data (D) from the outside. In addition, the transistors MP8, MP9, MP10, MN9, MN10, MN11, MP11, MN12, MN13, MP12, and MN14 illustrated in FIG. 3 may include the transistors MP2, MP3, MP4, MN2, and MN3 illustrated in FIG. 1. , MN4, MP5, MN5, MN6, MP6 and MN7) and perform the same operations, and thus descriptions of their operations will be omitted. As a result, the D flip-flop shown in FIG. 3 operates according to the truth table shown in Table 2 below.

Q (t) D Q (t + 1) 0 0 0 0 One One One 0 0 One One 0

Where Q (t) denotes a positive output previously output from the drain of transistor MP12, Q (t + 1) denotes a positive output currently output from the drain of transistor MP12, and D denotes data respectively. Indicates.

4 is a graph for comparing the power dissipation of the conventional flip-flop and the flip-flop according to the present invention.

Referring to FIG. 4, it can be seen that the power dissipation 10 of the conventional flip-flop is about 84.8 kW, whereas the power dissipation 20 of the flip-flop according to the present invention is 29.2 kW. That is, the low power consumption flip-flop according to the present invention can save about three times as much power as the conventional flip-flop.

The flip-flop according to the present invention described above was limited to T flip-flops and D flip-flops as shown in FIGS. 1 and 3, respectively. However, the low power consumption flip-flop according to the present invention is not limited to T or D flip-flop, and can be applied to other types of flip-flops by the above-described principle.

As described above, the low power consumption flip-flop according to the present invention has an effect of significantly reducing the total power consumption of the system in which the flip-flop is used by reducing the number of transistors that are transitioned in response to the clock signal.

Claims (3)

A first complementary MOS transistor, inverting and outputting the input data and connected between a supply power supply and a reference potential; A first MOS transistor forming a current path of the first CMOS transistor in response to a clock signal; A second CMOS transistor inverting and outputting the clock signal and connected between the supply power supply and the reference potential; A second MOS transistor forming a current path of the second CMOS transistor in response to the inverted data; A third CMOS transistor inverting the inverted clock signal and outputting the inverted clock signal as a negative output; And And a third MOS transistor forming a current path of the third CMOS transistor in response to the clock signal. The low power consumption flip-flop of claim 1, wherein the data corresponds to a previously outputted positive output. The method of claim 1, wherein the low power consumption flip-flop A fourth MOS transistor coupling the supply power supply to the second CMOS transistor in response to a reset signal; And And a fifth MOS transistor coupling an input of the third CMOS transistor to the reference potential in response to the reset signal.