KR20000039633A - Shift circuit for gate driver of liquid crystal display - Google Patents

Abstract

PURPOSE: A shift circuit for a gate driver of a liquid crystal display is provided to reduce the size of all gate drivers by using a latch array without using a flip-flop array. CONSTITUTION: A shift circuit for a gate driver of a liquid crystal display includes a divider(410), shifter(400), a logic combination unit(420) and a drive buffer(440). The divider divides an external main clock signal by a predetermined ratio, and outputs the divided result as a latch clock signal. The shifter comprises N numbers of latches connected serially, latches predetermined input data, and shifts the latched result in response to the latch clock signal. The logic combination unit comprises N numbers of logic gates, logically combines the latch clock signal and each output of the N numbers of latches, and outputs the combined result as a liquid crystal drive voltage. The drive buffer comprises N numbers of buffers, and generates N channels of channel voltages by buffering the N numbers of liquid crystal drive voltages.

Description

Shift circuit of liquid crystal display gate driver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate driver of a liquid crystal display, and more particularly, to a shift circuit of an LCD gate driver capable of reducing the size of the entire driver by converting a shift register of the gate driver into a latch.

In general, an LCD driver for driving a thin film transistor (TFT) LCD panel may be divided into a source driver for supplying a signal to each vertical line of the LCD panel and a gate driver for supplying a signal to each horizontal line. . That is, a gate driver for driving a TFT LCD panel applies a start pulse through a scan line to drive pixels corresponding to the same horizontal line, and a source driver applies display data to a TFT turned on through a predetermined signal line. do. In other words, the gate driver sequentially supplies a turn-on voltage to the horizontal line for turning on the transistors present in each TFT panel so that display data supplied by the source driver can be simultaneously supplied to the panel. In addition, the gate driver sequentially outputs high-level turn-on voltage to shift in the horizontal direction. However, in order to shift the turn-on voltage sequentially, a shift register including flip-flops equal to the number of channels must exist in the gate driver.

FIG. 1 is a circuit diagram illustrating a shift circuit of a conventional LCD gate driver and includes a shift register unit 100 and a driving buffer unit 150. Here, the shift register unit 100 includes flip-flops 10a to 10n connected in series, and the driving buffer unit 150 includes driving buffers 15a to 15n. Although not shown in detail, several shift registers 100 may exist.

The shift register unit 100 of the LCD gate driver shown in FIG. 1 clocks the main clock signal M_CLK, inputs a start pulse ST_PUL applied from an external timing controller (not shown), and then supplies the main clock signal. In response to (M_CLK), the input data is shifted to the next flip-flop. In addition, the data output from the flip-flops 10a to 10n are input to the respective driving buffers 15a to 15n.

Each of the driving buffers 15a to 15n of the driving buffer unit 150 inputs and buffers the output of each of the flip-flops 10a to 10n, and generates a buffered result as each channel voltage CH0 to CHn to TFT. Is applied.

2 (a) to 2 (d) are waveform diagrams for explaining the sequential shift operation of the shift circuit shown in FIG. 1, where 2 (a) represents the main clock signal M_CLK, and 2 (b) represents The output data of the first flip-flop 10a is shown, 2 (c) shows the output data of the second flip-flop 10b, and 2 (d) shows the output data of the third flip-flop 10c.

Referring to FIG. 2, the LCD gate driver shifts the output data horizontally while flip-flops of the shift register 100 sequentially generate outputs whenever the main clock signal M_CLK is applied.

In addition, the gate driver tests high-voltage direct-current stress capability to improve drive capability, leakage current, and reliability. To do this, the gate driver's outputs are either all high-level or locked to a low-level state. In other words, the leakage current can be checked or other tests can be performed in this state.

3 (a) to 3 (e) are waveform diagrams for explaining the operation during the test of the shift circuit shown in FIG. 1, where 3 (a) shows the main clock signal M_CLK and 3 (b) shows the The output data of one flip-flop 10a is shown, 3 (c) represents the output data of the second flip-flop 10b, 3 (d) represents the output data of the third flip-flop 10c, and 3 ( e) shows output data of the nth flip-flop 10n.

Referring to FIG. 3, the period T31 represents a state in which all channel voltages are turned on to a high level. As shown in FIG. 3, in order to change the output state again when the outputs of each of the flip-flops 10a to 10n are fixed at the high level or the low level by the main clock signal M_CLK, The output needs to change sequentially, requiring as much clocking time as the number of channels. In addition, since the above test is not repeated at one time but is repeatedly performed many times, the clocking time required to change the output state of the channel is very large in the entire test time.

As a result, the shift circuit of the conventional LCD gate driver has a large size as the flip-flops constituting the shift register occupy a large area, and the test takes a considerable time to change the output state of the channel. There is this.

An object of the present invention is to provide a shift circuit of an LCD gate driver that can reduce the size of the entire gate driver by using a latch array instead of a flip-flop array in the shift circuit of the LCD gate driver.

1 is a circuit diagram illustrating a shift circuit of a conventional liquid crystal device (LCD) gate driver.

2 (a) to 2 (d) are waveform diagrams for explaining a sequential shift operation of the shift circuit shown in FIG.

3A to 3E are waveform diagrams for explaining the operation during the test of the shift circuit shown in FIG.

4 is a circuit diagram of a preferred embodiment for explaining the shift circuit of the LCD gate driver according to the present invention.

5 (a) to 5 (d) are waveform diagrams for explaining an operation when a flip-flop is replaced with a latch in the shift circuit of the LCD gate driver.

6A to 6H are waveform diagrams for describing the operation of the shift circuit shown in FIG. 4.

In order to achieve the above object, the shift circuit of the LCD gate driver according to the present invention divides the main clock signal applied from the outside at a predetermined rate, and divides the division means for outputting the divided result as a latch clock signal. Shifting means for latching predetermined input data and shifting the latched result in response to a latch clock signal, consisting of N logic gates, each output of the N latches, and a latch clock signal. Logical combination means for outputting the logically combined result as a liquid crystal drive voltage, and N buffers, and drive buffer means for buffering the N liquid crystal drive voltages to generate N channel voltages. It is preferable.

Hereinafter, a shift circuit of an LCD gate driver according to the present invention will be described with reference to the accompanying drawings.

4 is a circuit diagram of a preferred embodiment for explaining a shift circuit of an LCD gate driver according to the present invention, which includes a flip-flop 410, a shifting unit 400, a logic combination unit 420, and a driving buffer unit 440. do. Here, the shifting unit 400 is composed of inverters 41a to 41n and latches 40a to 40n, the logic combination unit 420 is composed of end gates 42a to 42n, and a driving buffer unit. 440 is composed of drive buffers 44a through 44n.

The flip-flop 410 is implemented as a toggle flip-flop. The flip-flop 410 divides the main clock signal M_CLK, which is applied from the outside by one clock for one horizontal period, and outputs the divided signal as the latch clock signal L_CLK. In addition, the flip-flop 410 has a reset signal, and the reset signal is a logic combination of a start pulse ST_PUL supplied by an external timing controller, that is, a start pulse circuit (not shown), and a main clock signal M_CLK. Can be formed.

The shifting unit 400 clocks the latch clock signal L_CLK output from the flip-flop 410, latches the start pulse ST_PUL output from an external timing controller (not shown), and latches the latch clock signal L_CLK. Shifts the latched data in response to Here, the latch clock signal input to odd-numbered latches such as the first latch 40a, the third latch 40c, the fifth latch 40e, and the like is inverted in each of the inverters 41a, 41c ... After that, the clock signal inputted to the even-numbered latch is applied without being inverted. At this time, the latch clock signal L_CLK is inverted and applied to the first input of the even-numbered AND gates 42b, 42d,... 42n of the subsequent logic combination unit 420. Carry output from the shifting unit 400 is input to the next shifting unit (not shown) and used as a start pulse.

The logic combiner 420 is composed of n logic gates, preferably AND gates 42a to 42n, and applies each output of the n latches to the second input, and latches the latch clock signal L_CLK or inverts it. The latched clock signal is applied to the first input and then logically multiplied to output the result of the logical multiplication as a liquid crystal driving voltage.

The driving buffer unit 440 inputs and buffers n liquid crystal driving voltages, and generates the buffered result as an output voltage of n channels, that is, each channel voltage CH1 to CHn. At this time, each channel voltage is applied to the gate of the TFT to become a driving voltage for driving each pass transistor.

That is, in the present invention, unlike the conventional shift circuit, the latch circuit instead of the flip-flop array can be used to reduce the overall circuit size by 1/2.

5 (a) to 5 (d) are waveform diagrams for explaining an operation when the flip-flop is replaced with a latch in the shift circuit of the LCD gate driver, and 5 (a) shows the main clock signal M_CLK. 5 (b) indicates the output signal of the first latch 40a, 5 (c) indicates the output signal of the second latch 40b, and 5 (d) indicates the output signal of the third latch 40c. Indicates.

Referring to FIG. 5, when the flip-flop is changed to only a latch in the conventional shift circuit shown in FIG. 1, portions overlapping by half periods occur as shown in FIGS. 5 (b) to 5 (d). . Specifically, compared to the conventional LCD gate driver, in the case of the shift register composed of flip-flops, one output is generated for one clock signal and shifted. However, when the shift latch is implemented, one main clock signal ( The output occurs once for M_CLK), but the output data shifts for the clock half cycle, causing overlapping portions between adjacent channels. Referring to FIG. 5B, the section T51 represents a portion where the output of the first latch 40a and the output of the second latch 40b overlap. As a result, the gate line of the LCD panel is turned on twice at the time when the gate line of the LCD panel needs to be turned on once, so that it is not synchronized with the data output supplied by the source driver, and thus the display of the LCD panel becomes impossible. May occur.

6 (a) to 6 (h) are waveform diagrams showing the output of the shift circuit of the gate driver shown in FIG. 4, where 6 (a) represents the main clock signal M_CLK and 6 (b) represents the main clock. The latch clock signal L_CLK divided into two signals is shown, 6 (c) to 6 (e) represent outputs of the first to third latches, and 6 (f) to 6 (h) represent logic combination units 420. It represents the liquid crystal drive voltage of the first to third channels output through ().

Referring to FIG. 6, since the latches 40a to 40n shift data every half cycle of the main clock signal M_CLK, the main clock signal M_CLK is divided into two and used as the latch clock signal L_CLK. do. In addition, in order to prevent the outputs of the latches from overlapping each other between adjacent channels, each latch output is logically multiplied with the latch clock signal L_CLK or the inverted latch clock signal, so that only the interval where both signals become high levels is used for the actual channel. Consider output.

Hereinafter, an operation of the shift circuit of the LCD gate driver according to the present invention will be described with reference to FIGS. 4 and 6.

First, when the main clock signal M_CLK shown in FIG. 6A is divided into two, a divided clock signal such as 6 (b), that is, a latch clock signal L_CLK is generated, and the latch clock signal L_CLK is generated. The inverters 41a, 41c, ... 41n-1 connected to the inputs of the odd-numbered latches of the shifting unit 400 are inverted and applied to the odd-numbered latches 40a, 40c, 40n-1. On the other hand, the latch clock signal L_CLK is not inverted and is applied as a clock signal of even-numbered latches 40b, 40d, .. 40n. Each latch 40a to 40n latches the applied data and shifts the latched data in response to the latch clock signal L_CLK or the inverted latch clock signal. Therefore, since the divided clock signal is used as the latch clock signal L_CLK, the data shift is performed once every half period of the latch clock signal L_CLK, that is, every one period of the main clock signal M_CLK. However, as shown in FIGS. 6C to 6E, the interval in which the latch output is enabled at the high level is one period of the latch clock signal L_CLK, that is, two periods of the main clock signal M_CLK. Since it persists, the overlap between adjacent channels should be removed in the following way.

Specifically, the logic combination unit 420 logically multiplies the output of the odd-numbered latches 40a, 40c, .. 40n-1 by the latch clock signal L_CLK, and even-numbered latches 40b, 40d, .. 40n. ) Output is ANDed with the inverted latch clock signal to eliminate half of the overlap. Thus, the outputs of each latch block the overlapping half-cycle through the AND gate. 6 (f) to 6 (h), the sections T61, T62, and T63 represent portions of the output of the latch that are logically removed by a latch clock signal or an inverted latch clock signal.

By the above-described process, the start pulse ST_PUL is output as a high level ON pulse, that is, a liquid crystal driving voltage, by one channel according to the main clock signal M_CLK through the shifting unit 400 and the logic combination unit 420. For each clock signal, sequential shifts are made.

In the high voltage DC stress test, if the start pulse ST_PUL is supplied to the high level at the same time after the data output by one sequential shift is completed, all the main clock signals M_CLK after the number of channels have passed. The output is turned on. After that, the output voltage is turned off every one cycle of the main clock signal M_CLK, and then the test is performed while switching to the on voltage and off voltage again. In the present invention, when all outputs must be kept on and off when performing an IC test, time setting and test condition setting are very advantageous only by toggling a clock signal. That is, as in the conventional case, it is possible to easily change the output channel voltage by reducing the clocking time required to apply as many clocks as the number of channels per test item and simply changing the clock state, thus making it very effective when writing a test program. This can be called.

According to the present invention, not only can the total gate driver size be reduced by replacing each flip-flop of the shift register with a latch, but also a clocking operation for turning on / off the output data during the high voltage test of the gate driver. This has the effect of reducing the time.

Claims (3)

A division means for dividing the externally applied main clock signal at a predetermined rate and outputting the divided result as a latch clock signal; Shifting means, comprised of N (0) latches connected in series, for latching predetermined input data and shifting the latched result in response to the latch clock signal; Logic combining means composed of N logic gates, for logically combining each output of the N latches and the latch clock signal to output the logical combined result as a liquid crystal driving voltage; And And a driving buffer means for buffering the N liquid crystal driving voltages to generate N channel voltages. The method of claim 1, wherein the shifting means, Inverts the latch clock signals input to second K + 1 (K = 0,1,2 ..., N-1 / 2) th latches of the N latches, and returns the inverted result to the second K + N / 2 inverters for applying to the first latches; And And an N / 2 inverters for inverting the latch clock signal and applying the inverted result to a first input of a second K-th logic gate among the N logic gates. Shift circuit. The method of claim 1, wherein the logical combining means, And a plurality of N gates for ANDing the output of the N latches and the latch clock signal or the inverted latch clock signal, and outputting the AND product as the liquid crystal driving voltage. Shift circuit of the gate driver.