KR20050001790A - Apparatus and method for driving of liquid crystal display device - Google Patents

Abstract

PURPOSE: A driver apparatus of a liquid crystal display device and its driving method are provided to perform multi-driving of resolution of the liquid crystal display device using a MOS thin film transistor and also to reduce power consumption by changing output waveform of a gate driver according to the resolution of video data. CONSTITUTION: A liquid crystal panel(110) has gate lines and data lines formed in a matrix. A timing controller(108) generates a mode change signal to change resolution of data displayed on the liquid crystal panel and generates a start pulse. A clock generator(112) generates a number of clock signals according to the mode change signal. A shift register array includes shift registers generating a gate signal by shifting the start pulse according to the clock signals and then supplying the gate signal to the gate lines. And a switching array supplies one of the start pulse and an output signal of the front shift register to the other shift registers according to the clock signals.

Description

Driving apparatus and driving method of liquid crystal display device {APPARATUS AND METHOD FOR DRIVING OF LIQUID CRYSTAL DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate driving device of a liquid crystal display device, and more particularly, to a driving device of a liquid crystal display device capable of driving multiple resolutions of a liquid crystal display device using only a P or N type metal oxide semiconductor (MOS) thin film transistor; It relates to a driving method. In addition, the present invention relates to a driving apparatus and a driving method of a liquid crystal display device which can reduce power consumption by changing an output waveform of a gate driver according to the resolution of video data.

BACKGROUND ART Liquid crystal displays (hereinafter referred to as "LCDs") are becoming increasingly wider in application range due to features such as light weight, thinness, and low power consumption. According to this trend, LCDs are used for office automation equipment, audio / video equipment, and the like.

Such a conventional LCD displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the LCD includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area where the gate lines and the data lines cross each other. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to any one of the data lines via source and drain terminals of a thin film transistor which is a switching element. The gate terminal of the thin film transistor is connected to any one of the gate lines.

The driving circuit includes a gate driver for driving the gate lines and a data driver for driving the data lines. The gate driver sequentially supplies scan signals to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal panel by one line. The data driver supplies a video signal to each of the data lines whenever a gate signal is supplied to any one of the gate lines. Accordingly, the liquid crystal display displays an image by adjusting light transmittance by an electric field applied between the pixel electrode and the common electrode according to the video signal for each liquid crystal cell.

Thin film transistors used in such LCDs are classified into amorphous silicon and polysilicon types depending on whether amorphous silicon and polysilicon are used as semiconductor layers.

Amorphous silicon type thin film transistors have the advantage that the characteristics of the amorphous silicon film are relatively good and the characteristics are stable. However, the application of the amorphous silicon thin film transistor is difficult in the case of improving the pixel density due to the relatively low charge mobility. In addition, in the case of using an amorphous silicon type thin film transistor, peripheral driving circuits such as the gate driver and the data driver have to be manufactured separately and mounted in a liquid crystal panel.

On the other hand, the polysilicon thin film transistor has the advantage of not only difficulty in increasing pixel density due to the high charge mobility, but also lowering the manufacturing cost by allowing peripheral driving circuits to be embedded in the liquid crystal panel. Accordingly, LCDs using polysilicon thin film transistors have emerged.

In addition, the driving device of the general LCD changes the gate signal supplied to the gate lines from the gate driver according to the resolution of the data displayed on the liquid crystal panel. In other words, when high resolution data is displayed as low resolution data, gate signals are simultaneously output to adjacent gate lines which are gate drivers. As such, in order to drive the liquid crystal panel in multi-resolution according to the resolution of data displayed on the liquid crystal panel, a low power mobile active matrix liquid crystal display contained in "K.Maeda et al. SID'02 Digest, pp 794-797." Multi-Resolution for Low Power Mobile AMLCD has been proposed.

1 and 2, a conventional multi-resolution gate driver for a low power mobile active matrix liquid crystal display level shifts the voltage level of the clock generator 10 and the gate start pulse GSP supplied from the LCD controller. Level shifter (30), RS flip-flop (40) configured with CMOS transistors, and transmission gate (50) to use four clock signals (GCK1, GCK2, GCK3, GCK4) supplied from clock generator 10. And a shift register 20 and a buffer 60 for varying the output timing of the level shifted gate start pulse GSP from the level shift 30.

The clock generator 10 generates four clock signals GCK1, GCK2, GCK3, and GCK4 from an external input signal. The clock generator 10 sequentially supplies the first to fourth clock signals GCK1, GCK2, GCK3, and GCK4 to the shift register 20 according to a mode change control signal MC that is variable to a user's operation. The same first and second clocks GCK1 and GCK2 and the same third and fourth clocks GCK3 and GCK4 are supplied to the shift register 20.

The shift register 20 generates gate pulses supplied to the gate lines by using the first to fourth clock signals GCK1, GCK2, GCK3, and GCK4 supplied from the clock generator 10. The buffer 60 buffers the gate signal supplied from the shift register 20 to supply the gate lines.

In the multi-resolution for the low power mobile active matrix liquid crystal display, when the mode change control signal MC of the high state HIGH is supplied to the clock generator 10 according to a user's operation, the clock generator 10 may be configured to be first. To fourth clock signals GCK1, GCK2, GCK3, and GCK4 are sequentially supplied to the shift register 20. As shown in FIG. Accordingly, the gate signal output from the gate driver is sequentially supplied to the gate lines. Thus, data displayed on the liquid crystal panel is displayed in full color high resolution.

On the other hand, when the mode change control signal MC in the low state LOW is supplied to the clock generator 10 according to the user's operation, the clock generator 10 may have the same first and second clocks GCK1 and GCK2 and the same. The same third and fourth clocks GCK3 and GCK4 are supplied to the shift register 20. Accordingly, as illustrated in FIG. 2, the same gate signal is sequentially supplied to the gate lines in units of two gate lines from two gate lines adjacent to the gate driver. Thus, data displayed on the liquid crystal panel is displayed at full color low resolution.

Such a conventional multi-resolution for low power mobile active matrix liquid crystal display device has a wide range of driving voltage because the shift register 20 is composed of CMOS transistors connecting an N-channel MOS-FET and a P-channel MOS-FET. It is easy to integrate the circuit and has excellent characteristics such as power consumption and noise margin, but there are disadvantages in that the manufacturing cost is high and reliability is low due to the large number of processes.

In addition, the conventional multi-resolution for low power mobile active matrix liquid crystal display device further includes a separate general shift register circuit, which includes a shift register for outputting an odd shift register and a shift register 2 for outputting an even shift register. It is possible to selectively drive the above-described multi resolution, that is, high resolution and low resolution by applying independent gate start pulses (GSP) and the first to fourth clocks by completely separating them. As a result, the waveform of the input clock becomes complicated.

Accordingly, it is an object of the present invention to provide a driving device and a driving method of a liquid crystal display device capable of driving the resolution of the liquid crystal display device in multiple using only P or N type metal oxide semiconductor (MOS) thin film transistors.

Another object of the present invention is to provide a driving device and a driving method of a liquid crystal display device which can reduce power consumption by changing an output waveform of a gate driver according to the resolution of video data.

1 illustrates a multi-resolution gate driver for a conventional low power mobile active matrix liquid crystal display.

FIG. 2 is a waveform diagram illustrating a gate signal for displaying data in multiple resolutions on the liquid crystal panel shown in FIG. 1.

3 is a block diagram illustrating a driving device of a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a waveform diagram illustrating a clock signal and a gate signal for displaying data at a high resolution on the liquid crystal panel shown in FIG.

FIG. 5 is a waveform diagram illustrating a clock signal and a gate signal for displaying data at a low resolution on the liquid crystal panel shown in FIG.

FIG. 6 is a block diagram illustrating the gate driver shown in FIG. 3. FIG.

FIG. 7A is a block diagram showing a boost circuit for boosting a gate start pulse from the timing controller shown in FIG. 3 to supply it to the gate driver. FIG.

FIG. 7B is a block diagram illustrating a level shifter for level shifting a gate signal from the gate driver shown in FIG. 3 and supplying it to gate lines; FIG.

FIG. 8 is a diagram illustrating a start pulse transfer path in a shift register array for displaying data at high resolution on the liquid crystal panel shown in FIG. 3; FIG.

FIG. 9 is a diagram showing a start pulse transfer path in a shift register array for displaying data at a low resolution on the liquid crystal panel shown in FIG. 3; FIG.

<Description of Symbols for Main Parts of Drawings>

10, 112: clock generator shift register: 10, SR1 to SR4

30, 200: level shifter 40: RS flip-flop

50: transmission gate 60: buffer

102: image display section 104; Data driver

106: gate driver 108: timing controller

110: liquid crystal panel 114: switching array

116: signal supply line group 190: boost circuit

120: shift register array 1141, 1142: switching circuit

In order to achieve the above object, a driving apparatus of a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel in which gate lines and data lines are formed in a matrix form, and a mode for changing the resolution of data displayed on the liquid crystal panel. A timing controller for generating a change signal and generating a start pulse, a clock generator for generating a plurality of clock signals according to the mode change signal, and shifting the start pulse according to the plurality of clock signals to generate a gate signal; Any one of a shift register array including first to Nth (where N is a positive integer) shift registers for supplying gate lines, and an output signal of the start pulse and the front end shift register according to the plurality of clock signals; A switching word for selectively supplying to the second to Nth shift registers And a ray.

In the driving device, the timing controller detects an operation signal by a user's operation and supplies one of a first mode change signal and a second mode change signal to the clock generator.

In the driving device, the clock generator includes a first clock signal having a predetermined period in response to the first mode change signal, a second clock signal inverted from the first clock signal, and a third clock signal identical to the first clock signal. A clock signal and a fourth clock signal identical to the second clock signal are generated.

In the driving device, the clock generator inverts the third clock signal to be equal to the second clock signal in response to the second mode change signal, and inverts the fourth clock signal to be equal to the first clock signal. It is characterized by.

In the driving device, the shift register array is configured to shift an external supply voltage and a signal line group to which each of the first to fourth clock signals is supplied, and to shift the start pulse input according to the first and second clock signals. 4N (where N is a positive integer greater than or equal to 1) a shift register and one of an output signal of the start pulse and the 4N shift register supplied through the switching array according to the third and fourth clock signals A fourth N + 1 shift register for shifting; a fourth N + 2 shift register for shifting an output signal from the fourth N + 1 shift register according to the third and fourth clock signals; One of an output signal of a 4N + 1 shift register and an output signal of a 4N + 2 shift register is shifted according to the first and second clock signals. It characterized in that it comprises a first shift register for bit 4N + 3.

In the driving device, the switching array is connected between a first switching circuit connected between the 4N shift register and the 4N + 1 shift register, and between the 4N + 2 shift register and the 4N + 3 shift register. A second switching circuit is provided.

In the driving device, the first switching circuit is connected between an input terminal of the 4N shift register and an input terminal of the 4N + 1 shift register, the first switch being driven by the first clock signal, and the first switch. A third switch connected between a switch and an input terminal of the fourth N + 1 shift register and driven by the third clock signal, a first node between the first switch and the third switch and the fourth node; A second switch connected between an output terminal and driven by the first clock signal, a second node between the third switch and an input terminal of the fourth N + 1 shift register and the external supply voltage among the signal line group And a fourth switch connected between the lines and driven by the fourth clock signal.

In the driving device, the first to fourth switches may be any one of PMOS and NMOS transistors.

In the driving device, the second switching circuit is connected between an input terminal of the 4N shift register and an input terminal of the 4N + 1 shift register to be driven by the fourth clock signal, and the fifth switch. A seventh switch connected between a switch and an input terminal of the fourth N + 1 shift register and driven by the first clock signal, a third node between the fifth switch and the seventh switch and the fourth N shift register; A sixth switch connected between an output terminal and driven by the third clock signal, a fourth node between the seventh switch and an input terminal of the fourth N + 1 shift register, and the external supply voltage among the signal line group And an eighth switch connected between the lines and driven by the first clock signal.

In the driving device, the fifth to eighth switches may be any one of a PMOS and an NMOS transistor.

In the driving device, the first switching circuit shifts the start pulse supplied to the input terminal of the fourth N shift register in response to the first through fourth clock signals by the first mode change signal. It is characterized in that the supply to the register is cut off, and the output signal from the output terminal of the 4N shift register is switched to the input terminal of the 4N + 1 shift register.

In the driving device, the second switching circuit is provided from a fourth N + 1 shift register input to an input terminal of the fourth N + 2 shift register in response to the first to fourth clock signals caused by the first mode change signal. It is characterized in that the output signal is blocked from being supplied to the fourth N + 3 shift register, and the output signal output from the output terminal of the fourth N + 2 shift register is switched to the input terminal of the fourth N + 3 shift register. .

In the driving device, the first switching circuit shifts the start pulse supplied to an input terminal of the fourth N shift register in response to the first to fourth clock signals by the second mode change signal to the fourth N + 1 shift. Switching to the input terminal of the register, it characterized in that the output signal output from the output terminal of the 4N shift register is blocked from being supplied to the input terminal of the 4N + 1 shift register.

In the driving device, the second switching circuit is configured to output from the fourth N + 1 shift register input to an input terminal of the fourth N + 2 shift register in response to the first to fourth clock signals caused by the second mode change signal. Switching the output signal of the input signal to the input terminal of the fourth N + 3 shift register, and preventing the output signal output from the output terminal of the fourth N + 2 shift register to be supplied to the input terminal of the fourth N + 3 shift register. It is characterized by.

In the driving apparatus, the shift register array may sequentially supply the gate signals to the gate lines according to the first to fourth clock signals generated by the first mode change signal.

In the driving apparatus, the shift register array may sequentially supply the same gate signal in units of two adjacent gate lines according to the first to fourth clock signals generated by the second mode change signal.

According to an exemplary embodiment of the present invention, a driving method of a liquid crystal display device includes a liquid crystal panel in which gate lines and data lines are formed in a matrix form, and first to Nth to supply gate signals to the gate lines. A second step of providing a shift register array including a shift register, generating a mode change signal for changing a resolution of data displayed on the liquid crystal panel, and generating a start pulse; Generating a plurality of clock signals according to the mode change signal by using a clock generator; and receiving the start pulse selectively supplied according to the plurality of clock signals using the first to Nth shift registers. Shifting according to a plurality of clock signals to generate a gate signal and supplying the gate signals to the gate lines It is characterized by including.

In the driving method, the second step includes detecting an operation signal by a user's operation, generating a first mode change signal, and supplying the first mode change signal to the clock generator, and detecting a operation signal by a user's operation to change the second mode. Generating and supplying a signal to the clock generator.

In the driving method, the clock generator includes a first clock signal having a predetermined period in response to the first mode change signal, a second clock signal inverted from the first clock signal, and a third clock signal identical to the first clock signal. A clock signal and a fourth clock signal identical to the second clock signal are generated.

In the driving method, the clock generator inverts the third clock signal to be equal to the second clock signal in response to the second mode change signal, and inverts the fourth clock signal to be equal to the first clock signal. It is characterized by.

In the driving method, the fourth step includes the start pulse supplied to the input terminal of the fourth N shift register in response to the first through fourth clock signals by the first mode change signal. Interrupting supply to the output signal; switching an output signal output from an output terminal of the fourth N shift register to an input terminal of the fourth N + 1 shift register; and responsive to the first to fourth clock signals Blocking the output signal of the 4N + 1 shift register input to the input terminal of the fourth N + 2 shift register from being supplied to the fourth N + 3 shift register, and from the output terminal of the fourth N + 2 shift register; And switching the output signal to an input terminal of the fourth N + 3 shift register.

In the driving method, the fourth step may include the start pulse supplied to an input terminal of the fourth N shift register in response to the first through fourth clock signals generated by the second mode change signal. Switching to an input terminal of a block; blocking output of an output signal output from an output terminal of the 4N shift register to an input terminal of the 4N + 1 shift register; and first to fourth clock signals In response to switching the output signal of the 4N + 1 shift register input to the input terminal of the fourth N + 2 shift register to the input terminal of the fourth N + 3 shift register; Blocking the output signal output from the output terminal from being supplied to the input terminal of the fourth N + 3 shift register. It is done.

In the driving method, the shift register array may sequentially supply the gate signals to the gate lines according to the first to fourth clock signals generated by the first mode change signal.

In the driving method, the shift register array may sequentially supply the same gate signal in units of two adjacent gate lines according to the first to fourth clock signals generated by the second mode change signal.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 9.

3 schematically illustrates a configuration of an LCD driving apparatus using a polysilicon thin film transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a liquid crystal display (hereinafter referred to as "LCD") according to an exemplary embodiment of the present invention includes an image display unit 102 in which liquid crystal cells Clc are arranged in a matrix form, and an image display unit. The gate driver 106 is connected to the gate lines GL of the 102 to supply the gate signal to the gate lines GL, and the video data is supplied to the data lines DL of the image display unit 102. A liquid crystal panel 110 having a data driver 104 therein; A timing controller 108 for controlling the gate driver 106 and the data driver 104 is provided.

The image display unit 102 displays an image through a matrix of liquid crystal cells LC. Each of the liquid crystal cells LC includes a thin film transistor TFT using polysilicon as a switching element connected to an intersection of the gate line GL and the data line DL. As polysilicon is 100 times faster than amorphous silicon, since the response speed of the TFT is fast, the liquid crystal cells LC are usually driven in a point-sequential manner. The data lines DL receive a video signal from the data driver 104. The gate lines GL receive a gate signal from the gate driver 106.

The timing controller 108 rearranges the digital video data supplied from the digital video card (not shown) by red (R), green (G), and blue (B). Video data R, G, B rearranged by the timing controller 108 is supplied to the data driver 104. In addition, the timing controller 108 generates a data control signal and a gate control signal using the horizontal / vertical synchronization signals H and V input thereto. The data control signal includes a dot clock Dclk, a source shift clock SSC, a source enable signal SOE, a polarity inversion signal POL, and the like, and is supplied to the data driver 104. The gate control signal includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable GOE, and the like, and is supplied to each of the gate drivers 106.

In addition, the timing controller 108 may sequentially generate the first to fourth clocks according to the mode change signal MC by a user's operation for changing the resolution of data displayed on the image display unit 102. Built-in clock generator 112 for generating signals CLK1, CLK2, CLK3, CLK4.

The clock generator 112 has a predetermined period as shown in FIG. 4 when the mode change signal MC of the high state HIGH for displaying data on the image display unit 102 at high resolution is supplied by a user's manipulation. The first clock signal CLK1 having the?, The second clock signal CLK2 in which the first clock signal CLK2 is inverted, the third clock signal CLK3 identical to the first clock signal CLK1, and the second The fourth clock signal CLK4, which is the same as the clock signal CLK, is generated and supplied to the gate driver 106. In addition, the clock generator 112 is supplied with a mode change signal MC in a low state LOW for displaying data on the image display unit 102 at a low resolution by a user's manipulation, as shown in FIG. 5. A first clock signal CLK1 having a predetermined period, a second clock signal CLK2 in which the first clock signal CLK1 is inverted, a third clock signal CLK3 identical to the second clock signal CLK2, The fourth clock signal CLK4, which is the same as the first clock signal CLK1, is generated and supplied to the gate driver 106.

The data driver 104 outputs one pixel signal for one line per horizontal period H1, H2, ... in response to the data control signals SSP, SSC, SOE, and POL from the timing controller 108. Feed to the field (DL). In particular, the data driver 104 converts and supplies the digital video data R, G, and B from the timing controller 108 into an analog video signal using a gamma voltage from a gamma voltage generator not shown. The data driver 104 is composed of a plurality of data drive ICs for separately driving the data lines DL.

As shown in FIG. 6, the gate driver 106 receives the first to fourth clock signals CLK1, CLK2, CLK3, and CLK4 from the clock generator 112 of the timing controller 108 according to the mode change signal MC. Among the signal supply line group 116 to which the driving voltage VSS is supplied from a power supply device (not shown) and the first to fourth clock signals CLK1, CLK2, CLK3, and CLK4 supplied to the signal supply line group 116. A shift register array 120 including a plurality of shift registers SR for generating a gate signal by sequentially shifting a gate start pulse GSP supplied from the timing controller 108 using two clock signals; Between the radix (2N + 1, where N is a positive integer of 0 or greater) shift registers SR1, SR3 to SRn-1 and even-numbered (2N) shift registers SR2, SR4 to SRn of shift register array 120. A gate signal output from the previous shift register and a gate output from the next shift register using the first to fourth clock signals CLK1, CLK2, CLK3 and CLK4 connected to the signal supply line group 116. And a switching array 114 for overlapping or non-overlapping the signals. Here, the gate start pulse GSP supplied from the timing controller 108 to the gate driver 106 may be boosted and supplied by the boost circuit 190 as shown in FIG. 7A. In addition, the gate signal output from the shift register array 120 may be level shifted by the level shift array 200 and supplied to each gate line as illustrated in FIG. 7B.

The shift register array 120 of the first to fourth clock signals CLK1, CLK2, CLK3, and CLK4 supplied from the clock generator 112 according to the mode change signal MC via the signal supply line group 116. The gate start pulse GSP supplied from the timing controller 108 is shifted and supplied to the gate lines GL using two clock signals. At this time, the plurality of shift registers SR of the shift register array 120 is composed of a plurality of transistors not shown, and the plurality of transistors are composed of a P-type MOS or an N-type MOS.

Specifically, the gate start pulse GSP from the timing controller 108 to the input terminal IN of the fourth shift register SR, that is, the first shift register SR1 among the plurality of shift registers SR of the shift register array 120. Is supplied to the first and second clock input terminals CK1 and CK2 through the first and second signal supply lines 1161 and 1162 of the signal supply line group 116, respectively. CLK1 and CLK2 are supplied, and the supply voltage VSS is supplied to the voltage supply terminal VSS through the fifth signal supply line 1165 of the signal supply line group 116. The output terminal OUT of the first shift register SR1 is connected to the first gate line GL1 of the image display unit 102 and to the first switching circuit 1141 of the switching array 114. The first shift register SR1 generates a gate signal by shifting the gate start pulse GSP using the first and second clock signals CLK1 and CLK2 supplied according to the mode change signal MC. The first gate line GL1 is supplied to the first gate line GL1 through the terminal OUT.

The first switching circuit 1141 of the switching array 114 is provided at the input terminal IN of the fourth shift register SR, that is, the second shift register SR2, among the plurality of shift registers SR of the shift register array 120. ), One of the output signals output from the gate start pulse GSP and the first shift register SR1 is supplied from the timing controller 108, and the first and second clock input terminals CK1, Each of CK2 is supplied with fourth and third clock signals CLK4 and CLK3 through fourth and third signal supply lines 1164 and 1163 of the signal supply line group 116, and is supplied to the voltage supply terminal VSS. The supply voltage VSS is supplied through the fifth signal supply line 1165 of the signal supply line group 116. The output terminal of the second shift register SR2 is connected to the second gate line GL2 of the image display unit 102 and to the second switching circuit 1142 of the switching array 114. The second shift register SR2 uses the fourth and third clock signals CLK4 and CLK3 supplied in response to the mode change signal MC to the gate start pulse GSP and the first from the timing controller 108. One of the output signals output from the shift register SR1 is shifted and supplied to the second gate line GL2 through the output terminal OUT.

An output signal output from the second shift register SR2 to the input terminal IN of the fourth shift register SR, that is, the third shift register SR3 among the plurality of shift registers SR of the shift register array 120. Is supplied to the first and second clock input terminals CK1 and CK2, respectively, through the third and fourth clock signal lines 1163 and 1164 of the signal supply line group 116. CLK3 and CLK4 are supplied, and the supply voltage VSS is supplied to the voltage supply terminal VSS through the fifth signal supply line 1165 of the signal supply line group 116. The output terminal of the third shift register SR3 is connected to the third gate line GL3 of the image display unit 102. The third shift register SR3 shifts the output signal output from the second shift register SR2 by using the third and fourth clock signals CLK3 and CLK4 supplied according to the mode change signal MC. The third gate line GL2 is supplied to the third gate line GL2 through the output terminal OUT.

The second switching circuit 1142 of the switching array 114 is provided at the input terminal IN of the fourth shift register SR, that is, the fourth shift register SR4, among the plurality of shift registers SR of the shift register array 120. According to the driving of any one of the output signal output from the second shift register (SR2) and the output signal output from the third shift register (SR3) is supplied, the first and second clock input terminal (CK1, CK2) ) Are supplied to the second and first clock signals CLK2 and CLK1 through the second and first signal supply lines 1162 and 1161 of the signal supply line group 116, and to the voltage supply terminal VSS. The supply voltage VSS is supplied through the fifth signal supply line 1165 of the supply line group 116. The output terminal of the fourth shift register SR4 is connected to the fourth gate line GL4 of the image display unit 102. The fourth shift register SR4 is the second shift register in response to the driving of the second switching circuit 1142 using the second and first clock signals CLK2 and CLK1 supplied according to the mode change signal MC. One of the output signal output from the SR2 and the output signal output from the third shift register SR3 is shifted and supplied to the fourth gate line GL4 through the output terminal OUT.

The first to fourth shift registers SR1, SR2, SR3, and SR4 are repeatedly arranged to form the shift register array 120 of the gate driver 106.

The switching circuit array 114 includes a first switching circuit 1141 connected between the fourth Nth shift register SR1 and the fourth N + 1th shift register SR2 of the shift register array 120, and the fourth N + 2. The second switching circuit 1142 is connected between the first shift register SR3 and the fourth N + 3th shift register SR4, and the first and second switching circuits 1141 and 1142 are alternately disposed. .

The first switching circuit 1141 of the switching circuit array 114 is a first connected between the input terminal IN of the 4N th shift register SR1 and the input terminal IN of the 4N + 1 th shift register SR2. The third thin film transistor T3 connected between the thin film transistor T1, the first thin film transistor T1, and the input terminal IN of the 4N + 1th shift register SR2, and the first and third thin film transistors. The second thin film transistor T2 and the third thin film transistor T3 connected between the first node N1 between the T1 and T3 and the output terminal OUT of the 4N + 1th shift register SR1. The second node N2 is connected between the second node N2 between the input terminal IN of the 4N + 1th shift register SR2 and the fifth signal supply line 1165 of the signal supply line group 116 and is connected to the second node N2. And a fourth thin film transistor T4 for discharging the voltage of the phase to the supply voltage VSS. Here, each of the first to fourth thin film transistors T1 to T4 may be formed of a P-type MOS or an N-type MOS, and each of the first to fourth thin film transistors T1 to T4 may be a P-type MOS. Let's explain.

In the first switching circuit 1141, the first thin film transistor T1 is driven by the second clock signal CLK2 supplied through the second signal supply line 1162 of the signal supply line group 116. The second thin film transistor T2 is driven by the first clock signal CLK1 supplied through the first signal supply line 1161 of the signal supply line group 116. In addition, in the first switching circuit 1141 of the switching array 114, the third thin film transistor T3 is supplied to the third clock signal CLK3 supplied through the third signal supply line 1163 of the signal supply line group 116. The fourth thin film transistor T4 is driven by the fourth clock signal CLK4 supplied through the fourth signal supply line 1164 of the signal supply line group 116.

On the other hand, the second switching circuit 1142 of the switching circuit array 114 is disposed between the input terminal IN of the 4N + 2th shift register SR3 and the input terminal IN of the 4N + 3rd shift register SR4. A fifth thin film transistor T5 connected between the fifth thin film transistor T5 and the fifth thin film transistor T7 connected between the fifth thin film transistor T5 and the input terminal IN of the 4N + 3th shift register SR4, and the fifth and A fifth thin film transistor T5 connected between the third node N3 between the seventh thin film transistors T5 and T7 and the output terminal OUT of the 4N + 2th shift register SR3, and a sixth thin film transistor Connected between the fourth node N4 and the fifth signal supply line 1165 of the signal supply line group 116 between the T6 and the input terminal IN of the 4N + 3th shift register SR4, and the fourth An eighth thin film transistor T8 for discharging the voltage on the node N4 to the supply voltage VSS is provided. Here, each of the fifth to eighth thin film transistors T5 to T8 may be formed of a P-type MOS or an N-type MOS, and each of the fifth to eighth thin film transistors T5 to T8 may be a P-type MOS. Let's explain.

In the second switching circuit 1142 of the switching array 114, the fifth thin film transistor T5 is connected to the fourth clock signal CLK4 supplied through the fourth signal supply line 1164 of the signal supply line group 116. The sixth thin film transistor T6 is driven by the third clock signal CLK3 supplied through the third signal supply line 1163 of the signal supply line group 116. In addition, in the second switching circuit 1142 of the switching array 114, the seventh thin film transistor T7 is provided with the first clock signal CLK1 supplied through the first signal supply line 1161 of the signal supply line group 116. The eighth thin film transistor T8 is driven by the second clock signal CLK2 supplied through the second signal supply line 1162 of the signal supply line group 116.

As described above, the driving device and the driving method of the liquid crystal display according to the exemplary embodiment of the present invention are generated according to the mode change signal MC by a user's operation to generate the first to fourth shift registers SR1, SR2, SR3, SR4. ) Are sequentially arranged so that the gate signals are non-overlapping between adjacent gate lines using the first to fourth clock signals CLK1, CLK2, CLK3, CLK4 and the switching circuit array 114 which are supplied to the shift register arrays that are repeatedly arranged. Or sequentially supply gate signals that overlap between adjacent gate lines.

Referring to FIG. 8 and FIG. 4, the driving device and the driving method of the liquid crystal display according to the exemplary embodiment of the present invention when the data is displayed on the image display unit 102 at high resolution will be described in detail. First, the mode change signal MC in the high state is supplied to the timing controller 108 by a user's button operation or a command signal corresponding thereto for displaying data on the image display unit 102 at high resolution. The timing controller 108 controls the clock generator 112 in response to the mode change signal MC in the high state. Accordingly, the clock generator 112 generates the first to fourth clock signals CLK1, CLK2, CLK3, and CLK4 as shown in FIG. 4 to the signal supply line group 116 of the shift register array 120. Supply.

The gate start pulse GSP supplied from the timing controller 108 is input to the first shift register SR1 and the second shift register SR2 in the ST0 section. However, the third thin film of the first switching circuit 1141 in which the gate start pulse GSP from the timing controller 108 supplied to the second shift register SR2 is turned off by the third clock signal CLK3. It is cut off by the transistor T3. That is, the gate start pulse GSP supplied to the input terminal IN of the second shift register SR2 is the first thin film transistor T1 of the first switching circuit 1141 that is turned on by the second clock signal CLK2. ) And the first thin film transistor T3 via the first node N1. In the ST0 period, the first shift register SR1 shifts the gate start pulse GSP supplied from the timing controller 108 according to the first and second clock signals CLK1 and CLK2.

In the ST1 period, the first shift register SR1 supplies the gate signal generated by shifting the gate start pulse GSP according to the first and second clock signals CLK1 and CLK2 to the first gate line GL1. do. In the ST1 section, the first thin film transistor T1 of the first switching circuit 1141 is turned off by the second clock signal CLK2, and the second thin film transistor T2 is connected to the first clock signal CLK1. The third thin film transistor T3 is turned on by the third clock signal CLK3 and the fourth thin film transistor T4 is turned off by the fourth clock signal CLK4. Accordingly, an output signal output from the first shift register SR1 to the first gate line GL1 is input to the input terminal IN of the second shift register SR2 and the first node (T2). It is supplied via the first pass 1P1 leading to N1, the third thin film transistor T3 and the second node N2. At this time, the gate start pulse GSP supplied from the timing controller 108 to the input terminal IN of the second shift register SR2 is blocked by the first thin film transistor T1.

In the ST2 period, the second shift register SR2 is output from the first shift register SR1 according to the fourth and third clock signals CLK4 and CLK3 to supply the gate signal supplied through the first pass 1P1. The shift is supplied to the second gate line GL2. The output signal output from the second shift register SR2 is supplied to the second gate line GL2 and simultaneously supplied to the third shift register SR3. Meanwhile, in the ST2 period, the fourth thin film transistor T4 of the first switching circuit 1141 discharges the voltage on the second node N2 to the supply voltage VSS in response to the fourth clock signal CLK4.

In the ST3 period, the third shift register SR3 shifts the output signal from the second shift register SR2 in response to the third and fourth clock signals CLK3 and CLK4, and thus the third gate line through the output terminal OUT. The signal is supplied to the GL3 and input to the fourth shift register SR4. In the ST3 section, the fifth thin film transistor T5 of the second switching circuit 1142 is turned off by the fourth clock signal CLK4, and the sixth thin film transistor T6 is turned off by the third clock signal CLK3. In the on state, the seventh thin film transistor T7 is turned on by the first clock signal CLK1 and the eighth thin film transistor T8 is turned off by the second clock signal CLK2. Therefore, an output signal output from the third shift register SR3 to the third gate line GL3 is input to the input terminal IN of the fourth shift register SR4 and the sixth thin film transistor T6 and the third node ( N3), the seventh thin film transistor T7 and the fourth node N4 are supplied via the second pass 1P2. At this time, the output signal supplied from the output terminal OUT of the second shift register SR2 to the input terminal of the fourth shift register SR4 is interrupted by the fifth thin film transistor T5.

In the ST4 period, the fourth shift register SR4 shifts the gate signal supplied from the output terminal OUT of the third shift register SR3 in response to the first and second clock signals CLK1 and CLK2 to form a fourth gate line. Supply to GL4. The output signal output from the fourth shift register SR4 is supplied to the input terminal of the next stage shift register.

As described above, the gate signals are sequentially supplied to the gate lines by repeating the ST1 to ST4 sections. As a result, when the data is displayed on the image display unit 102 by a user's operation at high resolution, the plurality of shift registers SR are set by the mode change signal MC corresponding to the timing controller 108 as described above. Gate start pulses GSP are sequentially shifted and supplied to the gate lines. Therefore, since the gate signals supplied to the adjacent gate lines do not overlap because the gate signals are sequentially supplied to the gate lines, the data is displayed at high resolution in the image display unit.

Meanwhile, the driving apparatus and the driving method of the liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to FIG. 9 when the data is displayed on the image display unit 102 at low resolution.

First, the mode change signal MC in a low state is supplied to the timing controller 108 by a user's button operation or a command signal corresponding thereto to display data on the image display unit 102 at low resolution. The timing controller 108 controls the clock generator 112 in response to the mode change signal MC in the low state. Accordingly, the clock generator 112 generates the first to fourth clock signals CLK1, CLK2, CLK3, and CLK4 as shown in FIG. 5 to the signal supply line group 116 of the shift register array 120. Supply.

In the ST0 period, the first thin film transistor T1 of the first switching circuit 1141 is turned on by the second clock signal CLK2, and the second thin film transistor T2 is turned on by the first clock signal CLK1. The third thin film transistor T3 is turned off by the third clock signal CLK3 and the fourth thin film transistor T4 is turned off by the fourth clock signal CLK4. Accordingly, the gate start pulse GSP supplied from the timing controller 108 is input to the first shift register SR1 and the second shift register SR2 in this ST0 period. In the ST0 period, the first shift register SR1 shifts the gate start pulse GSP supplied from the timing controller 108 according to the first and second clock signals CLK1 and CLK2, and the second shift register SR1. SR2 shifts the gate start pulse GSP supplied from the timing controller 108 according to the fourth and third clock signals CLK4 and CLK3.

In the ST1 period, the first shift register SR1 supplies the gate signal generated by shifting the gate start pulse GSP according to the first and second clock signals CLK1 and CLK2 to the first gate line GL1. . At the same time, the second shift register SR2 also supplies the gate signal shifted in the STO period to the second gate line GL2 according to the third and fourth clock signals CLK3 and CLK4, and also the third shift register SR3. Supply to the input terminal (IN) of. That is, the gate signal is simultaneously supplied to the first and second gate lines GL1 and GL2 in the ST1 section. In other words, the gate signals supplied to two adjacent gate lines are overlapped and supplied to each of the two gate lines in the ST1 section. In the ST1 section, the first thin film transistor T1 of the first switching circuit 1141 is turned off by the second clock signal CLK2, and the second thin film transistor T2 is connected to the first clock signal CLK1. The third thin film transistor T3 is turned off by the third clock signal CLK3 and the fourth thin film transistor T4 is turned on by the fourth clock signal CLK4. Therefore, the gate signal output from the output terminal OUT of the first shift register SR1 and output to the input terminal IN of the second shift register SR2 is blocked by the third thin film transistor T3. The voltage on the second node N2 is discharged to the supply voltage VSS via the fourth thin film transistor T4.

In the ST1 period, the second switching circuit 1142 of the second shift register SR2 is turned on by the fifth and seventh thin film transistors T5 and T7 turned on by the first and fourth clock signals CLK1 and CLK4. The gate signal output from the output terminal OUT is supplied to the fourth shift register SR4. Accordingly, each of the third and fourth shift registers SR3 and SR4 receives the gate signal supplied from the output terminal OUT of the second shift register SR2 in the ST1 section and shifts them.

In the ST2 period, the third shift register SR3 shifts the output signal from the second shift register SR2 in response to the third and fourth clock signals CLK3 and CLK4, and thus the third gate line through the output terminal OUT. At the same time as the GL3, it is supplied to the sixth thin film transistor T6 of the second switching circuit 1142. In addition, in the ST2 period, the fourth shift register SR4 supplies the gate signal generated in the ST1 period to the fourth gate line GL4 according to the first and second clock signals, and inputs IN of the next shift register. Supplies). At this time, the fifth thin film transistor T5 of the second switching circuit 1142 is turned off by the fourth clock signal CLK4 during the ST2 section, and the sixth thin film transistor T6 is turned off by the third clock signal CLK3. ), The seventh thin film transistor T7 is turned off by the first clock signal CLK1 and the eighth thin film transistor T8 is turned on by the second clock signal CLK2. do. Thus, the gate signal supplied from the output terminal OUT of the third shift register SR3 to the input terminal IN of the fourth shift register SR4 is blocked by the seventh thin film transistor T7, and the second The voltage on the node N2 is discharged to the supply voltage VSS via the eighth thin film transistor T8.

As described above, by repeating the ST0 to ST2 sections, the 4N shift register SR1 and the 4N + 1 shift register SR2 output the same gate signal. Therefore, data is displayed at low resolution in the image display part because it is sequentially supplied to two gate lines adjacent to the overlapping gate signal.

As described above, the driving device and the driving method of the liquid crystal display according to the embodiment of the present invention generate the first to fourth clock signals according to the mode change signal by the user's operation, and the fourth N according to the mode change signal. By changing the start pulse supplied from the shift register to the 4N + 1 shift register, the gate signal is sequentially supplied to the gate lines, or the same gate signal is sequentially supplied to two adjacent gate lines. Therefore, the present invention can reduce the power consumption of the liquid crystal display by changing the resolution of the data displayed on the image display unit to high resolution and low resolution according to the user's operation.

In addition, the present invention can simplify the process by configuring the transistors constituting the shift register array as PMOS or NMOS instead of CMOS.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (24)

A liquid crystal panel in which gate lines and data lines are formed in a matrix form; A timing controller generating a mode change signal for changing the resolution of data displayed on the liquid crystal panel and generating a start pulse; A clock generator for generating a plurality of clock signals according to the mode change signal; A shift register array including first to Nth shift shift signals for generating gate signals by shifting the start pulses according to the plurality of clock signals, wherein N is a positive integer; And a switching array for selectively supplying any one of an output signal of the start pulse and a front end shift register to the second to Nth shift registers according to the plurality of clock signals. . The method of claim 1, And the timing controller detects an operation signal by a user's operation and supplies one of a first mode change signal and a second mode change signal to the clock generator. The method of claim 2, The clock generator, A first clock signal having a predetermined period in response to the first mode change signal; A second clock signal inverted from the first clock signal; A third clock signal identical to the first clock signal; And a fourth clock signal identical to the second clock signal. The method of claim 3, wherein The clock generator, Inverting the third clock signal to be equal to the second clock signal in response to the second mode change signal, And inverting the fourth clock signal to be the same as the first clock signal. The method of claim 4, wherein The shift register array, A signal line group to which an external supply voltage and each of the first to fourth clock signals are supplied; A fourth N shift register, wherein N is a positive integer greater than or equal to one for shifting the input start pulse according to the first and second clock signals; A fourth N + 1 shift register configured to shift any one of the start pulse supplied through the switching array and an output signal of the fourth N shift register according to the third and fourth clock signals; A fourth N + 2 shift register for shifting the output signal from the fourth N + 1 shift register according to the third and fourth clock signals; A fourth N + 3 shift register configured to shift one of an output signal of a fourth N + 1 shift register and an output signal of a fourth N + 2 shift register according to the first and second clock signals through the switching array; A drive device for a liquid crystal display device, characterized in that provided. The method of claim 5, wherein The switching array, A first switching circuit connected between the fourth N shift register and the fourth N + 1 shift register; And a second switching circuit connected between the fourth N + 2 shift register and the fourth N + 3 shift register. The method of claim 6, The first switching circuit, A first switch connected between an input terminal of the 4N shift register and an input terminal of the 4N + 1 shift register and driven by the first clock signal; A third switch connected between the first switch and an input terminal of the fourth N + 1 shift register and driven by the third clock signal; A second switch connected between a first node between the first switch and a third switch and an output terminal of the 4N shift register and driven by the first clock signal; And a fourth switch connected between the second node between the third switch and the input terminal of the fourth N + 1 shift register and the external supply voltage line among the signal line group, and driven by the fourth clock signal. A drive device for a liquid crystal display device, characterized in that. The method of claim 7, wherein The first to fourth switches are driving devices of any one of a PMOS and an NMOS. The method of claim 6, The second switching circuit, A fifth switch connected between the input terminal of the 4N shift register and the input terminal of the 4N + 1 shift register and driven by the fourth clock signal; A seventh switch connected between the fifth switch and an input terminal of the fourth N + 1 shift register and driven by the first clock signal; A sixth switch connected between the third node between the fifth switch and the seventh switch and an output terminal of the fourth N shift register, and driven by the third clock signal; A fourth node connected between the seventh switch and an input terminal of the fourth N + 1 shift register and an eighth switch connected between the external supply voltage line of the signal line group and driven by the first clock signal; A drive device for a liquid crystal display device, characterized in that. The method of claim 8, The fifth to eighth switches are driving devices of any one of a PMOS and an NMOS. The method of claim 7, wherein The first switching circuit, Blocking the start pulse supplied to the input terminal of the fourth N shift register from being supplied to the fourth N + 1 shift register in response to the first to fourth clock signals by the first mode change signal, And an output signal from the output terminal of the fourth N shift register to an input terminal of the fourth N + 1 shift register. The method of claim 9, The second switching circuit, The output signal from the fourth N + 1 shift register input to the input terminal of the fourth N + 2 shift register in response to the first to fourth clock signals by the first mode change signal is the fourth N + 3 shift register. Cut off the supply to And an output signal output from the output terminal of the fourth N + 2 shift register to an input terminal of the fourth N + 3 shift register. The method of claim 7, wherein The first switching circuit, Switching the start pulse supplied to the input terminal of the fourth N shift register to the input terminal of the fourth N + 1 shift register in response to the first to fourth clock signals by the second mode change signal, And an output signal output from an output terminal of the fourth N shift register is blocked from being supplied to an input terminal of the fourth N + 1 shift register. The method of claim 9, The second switching circuit, Shifting the output signal from the fourth N + 1 shift register input to the input terminal of the fourth N + 2 shift register in response to the first to fourth clock signals by the second mode change signal; Switch to the input terminal of the register, And an output signal output from an output terminal of the fourth N + 2 shift register is blocked from being supplied to an input terminal of the fourth N + 3 shift register. The method of claim 5, wherein And the shift register array sequentially supplies the gate signals to the gate lines according to the first to fourth clock signals generated by the first mode change signal. The method of claim 5, wherein The shift register array supplies the same gate signal sequentially in units of two adjacent gate lines according to the first to fourth clock signals generated by the second mode change signal. Device. A shift register array including a liquid crystal panel in which gate lines and data lines are formed in a matrix form, and first to N th shift registers for supplying a gate signal to the gate lines, wherein N is a positive integer. With the first step, Generating a mode change signal for changing a resolution of data displayed on the liquid crystal panel and generating a start pulse; Generating a plurality of clock signals according to the mode change signal by using a clock generator; A fourth step of generating a gate signal by shifting the start pulse selectively supplied according to the plurality of clock signals using the first to Nth shift registers according to the plurality of clock signals, and supplying the gate signal to the gate lines; Method of driving a liquid crystal display device comprising a. The method of claim 17, The second step, Detecting an operation signal by a user's operation, generating a first mode change signal, and supplying the first mode change signal to the clock generator; Detecting a manipulation signal generated by a user's manipulation to generate a second mode change signal and supplying the second mode change signal to the clock generator; The method of claim 18, The clock generator, A first clock signal having a predetermined period in response to the first mode change signal; A second clock signal inverted from the first clock signal; A third clock signal identical to the first clock signal; And generating a fourth clock signal identical to the second clock signal. The method of claim 19, The clock generator, Inverting the third clock signal to be equal to the second clock signal in response to the second mode change signal, And inverting the fourth clock signal to be equal to the first clock signal. The method of claim 20, The fourth step, Blocking the start pulse supplied to the input terminal of the fourth N shift register from being supplied to the fourth N + 1 shift register in response to the first to fourth clock signals by the first mode change signal; Switching an output signal output from an output terminal of the fourth N shift register to an input terminal of the fourth N + 1 shift register; Blocking an output signal of the 4N + 1 shift register from being input to the input terminal of the fourth N + 2 shift register in response to the first to fourth clock signals; And switching an output signal output from an output terminal of the fourth N + 2 shift register to an input terminal of the fourth N + 3 shift register. The method of claim 20, The fourth step, Switching the start pulse supplied to an input terminal of the fourth N shift register to an input terminal of the fourth N + 1 shift register in response to the first to fourth clock signals by the second mode change signal; Blocking an output signal output from an output terminal of the fourth N shift register from being supplied to an input terminal of the fourth N + 1 shift register; Switching an output signal of the 4N + 1 shift register input to an input terminal of the fourth N + 2 shift register to an input terminal of the fourth N + 3 shift register in response to the first to fourth clock signals; And blocking an output signal output from the output terminal of the fourth N + 2 shift register from being supplied to the input terminal of the fourth N + 3 shift register. The method of claim 19, And the shift register array sequentially supplies the gate signals to the gate lines according to the first to fourth clock signals generated by the first mode change signal. The method of claim 17, The shift register array supplies the same gate signal sequentially in units of two adjacent gate lines according to the first to fourth clock signals generated by the second mode change signal. Way.