CN111696471A

CN111696471A - Driving circuit, display panel and display driving method

Info

Publication number: CN111696471A
Application number: CN202010668511.6A
Authority: CN
Inventors: 宗少雷; 孙继刚; 孙伟
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2020-07-13
Filing date: 2020-07-13
Publication date: 2020-09-22

Abstract

The invention discloses a driving circuit, a display panel and a display driving method. By providing the frequency conversion circuit, when a small number of sub-drive circuits output scanning signals, the sub-drive circuits of other groups can also output scanning signals. By arranging a group of sub-driving circuits corresponding to a reset signal terminal, when a plurality of groups of sub-driving circuits output scanning signals, part of the sub-driving circuits can be controlled to stop outputting the scanning signals. And then according to the display area watched by the user at present, the shift register of the plurality of sub-drive circuits is controlled to output the scanning signals only by the drive circuit corresponding to the user watching area, and the shift register of the less sub-drive circuits is controlled to output the scanning signals by the drive circuit corresponding to the non-user watching area, so that the high refresh frequency is realized in the user watching area, and the data transmission bandwidth, the equipment power consumption and the like are greatly reduced.

Description

Driving circuit, display panel and display driving method

Technical Field

The invention relates to the technical field of display, in particular to a driving circuit, a display panel and a display driving method.

Background

With the rapid development of display technology, display panels are increasingly developed toward high integration and low cost. The Array substrate line driving (GOA) technology integrates a Thin Film Transistor (TFT) Gate switch Circuit on an Array substrate of a display panel to form a scan driving of the display panel, so that a wiring space of a binding (binding) region and a Fan-out (Fan-out) region of an Integrated Circuit (IC) can be omitted, and not only can the product cost be reduced in two aspects of material cost and preparation process, but also the display panel can be designed to be symmetrical at two sides and beautiful with a narrow frame; moreover, the integration process can also omit the Bonding process in the direction of a grid scanning line, thereby improving the productivity and the yield.

Disclosure of Invention

The embodiment of the invention provides a driving circuit and a driving method thereof, a display panel and a display driving method, and a display device, which can change the signal refreshing frequency.

Therefore, the embodiment of the invention provides a driving circuit, which comprises a frequency conversion circuit and N groups of sub-driving circuits, wherein N is a positive integer and is more than or equal to 2;

wherein: the driving circuit comprises a plurality of shift registers, and two stages of shift registers which are every N-1 stages of shift registers belong to a group of sub-driving circuits;

in one group of the sub-drive circuits, for two adjacent stages of shift registers, the output signal end of the first stage shift register is electrically connected with the input signal end of the second stage shift register, and the output signal end of the second stage shift register is electrically connected with the cascade reset signal end of the first stage shift register;

the N groups of sub-driving circuits are correspondingly and electrically connected with N reset signal ends, and in one group of sub-driving circuits, all the shift registers are electrically connected with one reset signal end;

the N groups of sub-driving circuits are correspondingly and electrically connected with N triggering signal ends; the input signal end of the first stage shift register in the group of the sub-driving circuits is electrically connected with a trigger signal end;

the frequency conversion circuit is configured to provide a scanning trigger signal to a shift register in another group of the sub-drive circuits according to a signal of a frequency conversion control signal terminal and a signal of an output signal terminal of the sub-drive circuits.

Optionally, the frequency conversion circuit provides a scan trigger signal to a shift register in another group of the sub-driving circuits according to a signal at a frequency conversion control signal end and a signal at an output signal end of the group of the sub-driving circuits, and specifically includes:

the frequency conversion circuit provides the signal of the output signal end of the shift register of one group of the sub-drive circuits to the input signal end of the shift register of the other group of the sub-drive circuits under the control of the signal of the frequency conversion control signal end, or provides the signal of the first reference signal end to the first node of the shift register of the other group of the sub-drive circuits under the control of the signal of the frequency conversion control signal end and the signal of the output signal end of the shift register of one group of the sub-drive circuits.

Optionally, N is 2, the N groups of driving circuits include odd and even sub-driving circuits; wherein:

the odd sub-driving circuit comprises all odd-level shift registers in the driving circuit, and the even sub-driving circuit comprises all even-level shift registers in the driving circuit;

the N reset signal ends comprise odd reset signal ends and even reset signal ends;

all the shift registers in the odd sub-drive circuit are electrically connected with the odd reset signal end;

all the shift registers in the even number sub-driving circuits are electrically connected with the even number reset signal end.

Optionally, the frequency conversion circuit includes N groups of sub-frequency conversion circuits, one group of the sub-frequency conversion circuits corresponds to one group of the sub-driving circuits, and one group of the sub-frequency conversion circuits corresponds to one frequency conversion control signal terminal; the sub-frequency conversion circuit is configured to conduct the output signal terminal of the shift register of the corresponding group of sub-drive circuits with the input signal terminal of the shift register of the other group of sub-drive circuits under the signal control of the corresponding frequency conversion control signal terminal.

Optionally, the N groups of sub-frequency conversion circuits include an odd-numbered sub-frequency conversion circuit and an even-numbered sub-frequency conversion circuit, the odd-numbered sub-frequency conversion circuit includes a plurality of odd-numbered frequency conversion transistors, and the even-numbered sub-frequency conversion circuit includes a plurality of even-numbered frequency conversion transistors;

in the drive circuit, for two adjacent stages of shift registers, the output signal end of an odd-numbered stage shift register is electrically connected with the first end of one odd-numbered frequency conversion transistor, the input signal end of the shift register is electrically connected with the second end of an even-numbered frequency conversion transistor, when the first stage shift register is the odd-numbered stage shift register, the second end of the odd-numbered frequency conversion transistor is electrically connected with the input signal end of the second stage shift register, and when the first stage shift register is the even-numbered stage shift register, the second end of the even-numbered frequency conversion transistor is electrically connected with the input signal end of the second stage shift register;

the control end of the odd-number frequency conversion transistor is electrically connected with the odd-number frequency conversion control signal end, and the control end of the even-number frequency conversion transistor is electrically connected with the even-number frequency conversion control signal end.

Optionally, the frequency conversion circuit includes a plurality of first frequency conversion transistors and a plurality of second frequency conversion transistors, a control end of each of the first frequency conversion transistors is electrically connected to one of the frequency conversion control signal ends, and a second end of each of the second frequency conversion transistors is electrically connected to the first reference signal end;

in the driving circuit, for two adjacent stages of shift registers, an output signal end of a first stage of shift register is electrically connected with a first end of one first frequency conversion transistor, a second end of the first frequency conversion transistor is electrically connected with a control end of one second frequency conversion transistor, and a second end of the second frequency conversion transistor is electrically connected with a first node of a second stage of shift register.

Optionally, the shift register includes: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, an eighth switching transistor, a ninth switching transistor, a first capacitor, and a second capacitor; wherein:

a first end of the first switching transistor is electrically connected with the first reference signal end, a control end of the first switching transistor is electrically connected with the input signal end, and a second end of the first switching transistor is electrically connected with the first node;

a first end of the second switching transistor is electrically connected with a second reference signal end, a control end of the second switching transistor is electrically connected with the cascade reset signal end, and a second end of the second switching transistor is electrically connected with the first node;

a first end of the third switching transistor is electrically connected with a first clock signal end, a control end of the third switching transistor is electrically connected with the first node, and a second end of the third switching transistor is electrically connected with the output signal end;

a first end of the fourth switching transistor is electrically connected with a third reference signal end, a control end of the fourth switching transistor is electrically connected with a second node, and a second end of the fourth switching transistor is electrically connected with the output signal end;

a first end of the fifth switching transistor is electrically connected with the third reference signal end, a control end of the fifth switching transistor is electrically connected with the second node, and a second end of the fifth switching transistor is electrically connected with the first node;

a first end of the sixth switching transistor is electrically connected with the third reference signal end, a control end of the sixth switching transistor is electrically connected with the first node, and a second end of the sixth switching transistor is electrically connected with the second node;

a first end of the seventh switching transistor is electrically connected with a second clock signal end, a control end of the seventh switching transistor is electrically connected with the second clock signal end, and a second end of the seventh switching transistor is electrically connected with the second node;

a first end of the eighth switching transistor is electrically connected with the third reference signal end, a control end of the eighth switching transistor is electrically connected with the output signal end, and a second end of the eighth switching transistor is electrically connected with the second node;

a first end of the ninth switching transistor is electrically connected to the third reference signal end, a control end of the ninth switching transistor is electrically connected to the reset signal end, and a second end of the ninth switching transistor is electrically connected to the first node;

a first end of the first capacitor is electrically connected with the first node, and a second end of the first capacitor is electrically connected with the output signal end;

the first end of the second capacitor is electrically connected with the third reference signal end, and the second end of the second capacitor is electrically connected with the second node.

Correspondingly, the embodiment of the invention also provides a display panel, which comprises any one of the driving circuits, a plurality of scanning lines and a plurality of sub-pixels; the output signal end of one shift register in the driving circuit is correspondingly and electrically connected with one scanning line, and one scanning line is correspondingly and electrically connected with one row of sub-pixels.

Correspondingly, an embodiment of the present invention further provides a display driving method of the display panel, including:

determining a user gaze area and a non-user gaze area;

when the driving circuit corresponding to the non-user watching area is driven, the shifting register of the A group of sub-driving circuits is controlled to output scanning signals;

when the driving circuit corresponding to the non-user watching area is converted into the driving circuit corresponding to the user watching area, a variable frequency signal is loaded on a variable frequency control signal end so as to provide a scanning trigger signal to a shift register in the other group of sub-driving circuits;

when driving the driving circuit corresponding to the user watching area, controlling the shift register of the B group of sub-driving circuits to output scanning signals; wherein A and B are integers, and A is more than or equal to1 and B is more than or equal to N;

when the driving circuit corresponding to the user watching area is converted into the driving circuit corresponding to the non-user watching area, the reset signal ends corresponding to the A group of sub-driving circuits are loaded with signals of a first level, and the reset signal ends corresponding to the other groups of sub-driving circuits are loaded with signals of a second level.

Optionally, N is 2, and in the driving circuit corresponding to the user gazing area, when the first-stage shift register outputs a scanning signal, a signal of a second level is loaded to the variable frequency control signal terminal.

Optionally, for N adjacent display frames, in different display frames, in the driving circuit corresponding to the non-user-gazing region, the shift registers of the different groups of sub-driving circuits are controlled to output the scanning signals.

The invention has the following beneficial effects:

the display device comprises a frequency conversion circuit and N groups of sub drive circuits which can output scanning signals independently, in one display frame, a plurality of groups of sub drive circuits can output the scanning signals to realize high refresh frequency, only a few groups of sub drive circuits can output the scanning signals, and other groups of sub drive circuits do not output the scanning signals, thereby realizing low refresh frequency. By providing the frequency conversion circuit, when a small number of sub-drive circuits output scanning signals, the sub-drive circuits of other groups can also output scanning signals. By arranging a group of sub-driving circuits corresponding to a reset signal terminal, when a plurality of groups of sub-driving circuits output scanning signals, part of the sub-driving circuits can be controlled to stop outputting the scanning signals. And then according to the display area watched by the user at present, the driving circuit corresponding to the user watching area only controls the shift registers of the plurality of sub-driving circuits to output scanning signals, and the driving circuit corresponding to the non-user watching area only controls the shift registers of the plurality of sub-driving circuits to output scanning signals, so that the high refreshing frequency of the user watching area is realized, and the data transmission bandwidth, the equipment power consumption and the like are greatly reduced.

Drawings

Fig. 1 is a schematic structural diagram of a driving circuit according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of another driving circuit according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a driving circuit according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of another driving circuit according to an embodiment of the present invention;

FIG. 6 is a timing diagram of an odd frame signal of the driving circuit shown in FIG. 4;

FIG. 7 is a timing diagram of an even frame signal of the driving circuit shown in FIG. 4;

FIG. 8 is a timing diagram of an odd frame signal of the driving circuit shown in FIG. 5;

fig. 9 is a timing diagram of an even frame signal of the driving circuit shown in fig. 5.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connect" or "electrically connect," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

The display panel is generally provided with a gate driving circuit, the gate driving circuit includes a plurality of shift registers, and an output end of one shift register is electrically connected to one gate scanning line, so as to sequentially provide scanning signals to each gate scanning line. Generally, a second-stage shift register in two adjacent stages of shift registers in the gate driving circuit is electrically connected with an output end of a first-stage shift register, the first-stage shift register in the gate driving circuit receives a trigger signal and outputs a scanning signal according to the trigger signal, and the second-stage shift register in the two adjacent stages of shift registers receives the scanning signal output by the first-stage shift register, so that signal shift output is realized. However, the gate driving circuit can only output the scanning signals to the gate scanning lines of each row in sequence through the first stage shift register to the last stage shift register at a fixed signal refresh frequency, and cannot change the signal refresh frequency of some gate scanning lines of each row.

The driving circuit provided by the embodiment of the invention comprises a frequency conversion circuit and N groups of sub-driving circuits, wherein N is a positive integer and is more than or equal to 2;

wherein: the driving circuit comprises a plurality of shift registers, wherein every two-stage shift register which is separated by N-1 stages of shift registers belongs to a group of sub-driving circuits;

as a specific embodiment, taking N ═ 2 as an example, as shown in fig. 1 and fig. 2, the display device includes a

frequency converter circuit

100 and 2 groups of sub-driver circuits, where the 2 groups of sub-driver circuits are respectively an odd sub-driver circuit and an even sub-driver circuit, the odd sub-driver circuit includes all odd-stage shift registers SR (1), SR (3), and SR (2N-1) … … in the driver circuit, and the even sub-driver circuit includes all even-stage shift registers SR (2), SR (4), and SR (2N) … … in the driver circuit. Each two-stage shift register separated by one-stage shift register belongs to the same group of sub-drive circuits;

in a group of sub-drive circuits, for adjacent two stages of shift registers, an Output signal end Output of a first stage shift register is electrically connected with an Input signal end Input of a second stage shift register, and an Output signal end Output of the second stage shift register is electrically connected with a cascade reset signal end CR of the first stage shift register;

taking N as an example, as shown in fig. 1 and 2, in the odd-numbered sub-driving circuit, the shift register SR (1) and the shift register SR (3) are two adjacent stages of shift registers, the Output signal terminal Output of the shift register SR (1) is electrically connected to the Input signal terminal Input of the shift register SR (3), and the Output signal terminal Output of the shift register SR (3) is electrically connected to the cascade reset signal terminal CR of the shift register SR (1); in the even-numbered sub-drive circuit, the shift register SR (2) and the shift register SR (4) are two adjacent stages of shift registers, an Output signal end Output of the shift register SR (2) is electrically connected with an Input signal end Input of the shift register SR (4), and an Output signal end Output of the shift register SR (4) is electrically connected with a cascade reset signal end CR of the shift register SR (2); the shift register behind the shift register SR (4) has the same structure, and is not described herein;

taking N as an example, as shown in fig. 1 and 2, all shift registers in the odd sub-driving circuit are electrically connected to the odd reset signal terminal R1, and all shift registers in the even sub-driving circuit are electrically connected to the even reset signal terminal R2;

the N groups of sub-driving circuits are correspondingly and electrically connected with N triggering signal ends; an Input signal end of a first-stage shift register in the group of sub-driving circuits is electrically connected with a trigger signal end;

taking N as an example, as shown in fig. 1 and 2, the Input signal terminal Input of the first stage shift register SR (1) in the odd-numbered sub-driving circuit is electrically connected to the odd-numbered trigger signal terminal STV1, and the Input signal terminal Input of the first stage shift register SR (2) in the even-numbered sub-driving circuit is electrically connected to the even-numbered trigger signal terminal STV 2;

the frequency conversion circuit is configured to provide the scan trigger signal to the shift register in the other group of sub-drive circuits according to a signal of the frequency conversion control signal terminal and a signal of the output signal terminal of the group of sub-drive circuits.

Specifically, the frequency conversion circuit may be configured to supply the signal of the output signal terminal of the shift register of one group of the sub drive circuits to the input signal terminal of the shift register of the other group of the sub drive circuits under the signal control of the frequency conversion control signal terminal.

Taking N as an example, as shown in fig. 1, the frequency converter circuit can provide the signal of the Output signal terminal Output of the shift register in the odd-numbered sub-driver circuit to the Input signal terminal Input of the shift register in the even-numbered sub-driver circuit under the control of the signal of the odd-numbered frequency conversion control signal terminal SWO, and the frequency converter circuit can provide the signal of the Output signal terminal Output of the shift register in the even-numbered sub-driver circuit to the Input signal terminal Input of the shift register in the odd-numbered sub-driver circuit under the control of the signal of the even-numbered frequency conversion control signal terminal SWE.

Alternatively, the frequency conversion circuit is configured to supply the signal of the first reference signal terminal to the first node of the shift register of the other group of sub drive circuits under control of the signal of the frequency conversion control signal terminal and the signal of the output signal terminal of the shift register of the one group of sub drive circuits.

Taking N as an example, as shown in fig. 2, the frequency converter circuit may provide a signal of the first reference signal terminal to the first node of the shift register of the even-numbered sub-driver circuit under the control of a signal of the frequency conversion control signal terminal SW and a signal of the Output signal terminal Output of the shift register of the odd-numbered sub-driver circuit; alternatively, the frequency conversion circuit may provide the signal of the first reference signal terminal to the first node of the shift register of the odd-numbered sub-driver circuit under the control of the signal of the frequency conversion control signal terminal SW and the signal of the Output signal terminal Output of the shift register of the even-numbered sub-driver circuit.

The driving circuit provided by the embodiment of the invention comprises N groups of sub-driving circuits, in one group of sub-driving circuits, for adjacent two stages of shift registers, an Output signal end Output of a first stage shift register is electrically connected with an Input signal end Input of a second stage shift register, an Output signal end Output of the second stage shift register is electrically connected with a cascade reset signal end CR of the first stage shift register, and an Input signal end Input of the first stage shift register in one group of sub-driving circuits is electrically connected with a trigger signal end, so that each group of sub-driving circuits can independently Output scanning signals. In one display frame, a plurality of groups of sub-driving circuits may be caused to output scanning signals to achieve a high refresh frequency, for example, all groups of sub-driving circuits may be caused to output scanning signals; for example, only one sub-driver circuit may output the scan signal, thereby realizing a low refresh frequency. By arranging the frequency conversion circuit, when a small number of groups of sub-driving circuits output scanning signals in one display frame, the scanning signals currently output by one group of sub-driving circuits can be provided for the shift registers in other groups of sub-driving circuits, so that the other groups of sub-driving circuits also output the scanning signals, and the refreshing frequency is further improved. By setting all the shift registers in one group of the sub-driving circuits to be electrically connected with one reset signal end, when a plurality of groups of the sub-driving circuits output scanning signals in one display frame, part of the sub-driving circuits can be controlled to stop outputting the scanning signals, so that the refreshing frequency is reduced.

In a specific implementation, in the embodiment of the present invention, the frequency conversion circuit 100 may include N groups of sub-frequency conversion circuits, where one group of sub-frequency conversion circuits corresponds to one group of sub-driving circuits, and one group of sub-frequency conversion circuits corresponds to one frequency conversion control signal terminal; the sub-frequency conversion circuit is configured to conduct the output signal terminal of the shift register of the corresponding group of sub-drive circuits with the input signal terminal of the shift register of the other group of sub-drive circuits under the signal control of the corresponding frequency conversion control signal terminal.

In a specific implementation, when only one group of sub-driving circuits outputs a scanning signal in one display frame, all the frequency conversion transistors in the corresponding sub-frequency conversion circuits can be turned on under the control of a signal at the corresponding frequency conversion control signal terminal. When one shift register in the driving circuit outputs a scanning signal, other shift registers in the driving circuit do not output the scanning signal. The turned-on inverter transistor will provide the scan signal outputted by the current shift register to the input terminal of the first stage shift register in the other group of sub-driving circuits, so that the other group of sub-driving circuits also starts to output the scan signal.

In specific implementation, taking N ═ 2 as an example, as shown in fig. 1, the N groups of sub-frequency conversion circuits include an odd-numbered sub-frequency conversion circuit and an even-numbered sub-frequency conversion circuit, the odd-numbered sub-frequency conversion circuit includes a plurality of odd-numbered frequency conversion transistors TSO, and the even-numbered sub-frequency conversion circuit includes a plurality of even-numbered frequency conversion transistors TSE;

in the drive circuit, for two adjacent stages of shift registers, the output signal end of an odd-numbered stage shift register is electrically connected with the first end of an odd-numbered frequency conversion transistor TSO, the input signal end of the shift register is electrically connected with the second end of an even-numbered frequency conversion transistor TSE, when the first stage shift register is the odd-numbered stage shift register, the second end of the odd-numbered frequency conversion transistor TSO is electrically connected with the input signal end of the second stage shift register, and when the first stage shift register is the even-numbered stage shift register, the second end of the even-numbered frequency conversion transistor TSE is electrically connected with the input signal end of the second stage shift register;

the control end of the odd-number frequency conversion transistor is electrically connected with an odd-number frequency conversion control signal end SWO, and the control end of the even-number frequency conversion transistor is electrically connected with an even-number frequency conversion control signal end SWE.

In a display frame, only the odd sub-driving circuit outputs a scanning signal, and all odd frequency conversion transistors TSO in the odd sub-frequency conversion circuit can be conducted under the signal control of an odd frequency conversion control signal end SWO; assuming that when all the odd frequency conversion transistors TSO in the odd frequency conversion sub-circuit are turned on, the shift register SR (2n-1) in the odd frequency conversion sub-circuit outputs the scan signal, the odd frequency conversion transistor TS electrically connected to the output terminal of the shift register SR (2n-1) provides the scan signal output by the shift register SR (2n-1) to the Input signal terminal Input of the shift register SR (2n) in the even frequency conversion sub-circuit, and the even frequency conversion sub-circuit also starts outputting the scan signal. It should be noted that, in a set of sub-driving circuits, for two adjacent stages of shift registers, the Output signal terminal Output of the shift register of the first stage is electrically connected to the Input signal terminal Input of the shift register of the second stage, and the Input signal terminal Input of the shift register SR (2n) in the even-numbered sub-driving circuit is electrically connected to the Output signal terminal Output of the shift register SR (2n-2) in the even-numbered sub-driving circuit, so that the scan signal Output by the shift register SR (2n-1) when the frequency conversion transistor TS is turned on is also provided to the Output signal terminal Output of the shift register SR (2n-2), that is, the scan signal is Output by both the shift register SR (2n-1) and the shift register SR (2n-2) when the frequency conversion transistor TS is turned on, and the same data signal is written into the two rows of sub-pixels corresponding to the shift registers SR (2n-1) and SR (2n-2), however, the same data signals can be written into the two rows of sub-pixels only when the odd frequency conversion transistors are turned on, and the influence on the display effect is small. In a display frame, only even sub-driving circuits output scanning signals, which is the same as the above, and the description thereof is omitted here.

In practical implementation, in the embodiment of the present invention, as shown in fig. 2, the frequency conversion circuit 100 may include a plurality of first frequency conversion transistors TS1 and a plurality of second frequency conversion transistors TS2, wherein the control terminals of all the first frequency conversion transistors TS1 are electrically connected to a frequency conversion control signal terminal SW, and the second terminal of the second frequency conversion transistor TS2 is electrically connected to a first reference signal terminal CN;

in the driving circuit, for two adjacent stages of shift registers, the output signal terminal of the first stage shift register is electrically connected to the first terminal of a first frequency conversion transistor TS1, the second terminal of the first frequency conversion transistor TS1 is electrically connected to the control terminal of a second frequency conversion transistor TS2, and the second terminal of the second frequency conversion transistor TS2 is electrically connected to the first node N1 of the second stage shift register.

Still taking N as an example, in a display frame, if only the odd sub-driving circuits output the scan signals, all the first frequency conversion transistors TS1 in the frequency conversion circuit 100 can be turned on under the control of the signal of the frequency conversion control signal terminal SW; when the shift register SR (2N-1) in the odd-numbered sub-driving circuit outputs the scan signal, the turned-on first frequency-converting transistor TS1 provides the scan signal to the control terminal of the electrically connected second frequency-converting transistor TS2, so that the second frequency-converting transistor TS2 is turned on, the signal of the first reference signal terminal CN is provided to the first node N1 of the even-numbered sub-driving circuit SR (2N), and the even-numbered sub-driving circuit also starts outputting the scan signal. In a display frame, only even sub-driving circuits output scanning signals, which is the same as the above, and the description thereof is omitted here.

In practical implementation, in the embodiment of the present invention, as shown in fig. 3 to5, the shift register may include: a first switching transistor T1, a second switching transistor T2, a third switching transistor T3, a fourth switching transistor T4, a fifth switching transistor T5, a sixth switching transistor T6, a seventh switching transistor T7, an eighth switching transistor T8, a ninth switching transistor T9, a first capacitor C1, and a second capacitor C2; wherein:

a first terminal of the first switching transistor T1 is electrically connected to the first reference signal terminal CN, a control terminal of the first switching transistor T1 is electrically connected to the Input signal terminal Input, and a second terminal of the first switching transistor T1 is electrically connected to the first node N1;

a first terminal of the second switching transistor T2 is electrically connected to the second reference signal terminal CNB, a control terminal of the second switching transistor T2 is electrically connected to the cascade reset signal terminal CR, and a second terminal of the second switching transistor T2 is electrically connected to the first node N1;

a first terminal of the third switching transistor T3 is electrically connected to the first clock signal terminal CLK1, a control terminal of the third switching transistor T3 is electrically connected to the first node N1, and a second terminal of the third switching transistor T3 is electrically connected to the Output signal terminal Output;

a first end of the fourth switching transistor T4 is electrically connected to the third reference signal terminal VGL, a control end of the fourth switching transistor T4 is electrically connected to the second node N2, and a second end of the fourth switching transistor T4 is electrically connected to the Output signal terminal Output;

a first terminal of the fifth switching transistor T5 is electrically connected to the third reference signal terminal VGL, a control terminal of the fifth switching transistor T5 is electrically connected to the second node N2, and a second terminal of the fifth switching transistor T5 is electrically connected to the first node N1;

a first terminal of the sixth switching transistor T6 is electrically connected to the third reference signal terminal VGL, a control terminal of the sixth switching transistor T6 is electrically connected to the first node N1, and a second terminal of the sixth switching transistor T6 is electrically connected to the second node N2;

a first terminal of the seventh switching transistor T7 is electrically connected to the second clock signal terminal CLK2, a control terminal of the seventh switching transistor T7 is electrically connected to the second clock signal terminal CLK2, and a second terminal of the seventh switching transistor T7 is electrically connected to the second node N2;

a first terminal of the eighth switching transistor T8 is electrically connected to the third reference signal terminal VGL, a control terminal of the eighth switching transistor T8 is electrically connected to the Output signal terminal Output, and a second terminal of the eighth switching transistor T8 is electrically connected to the second node N2;

a first terminal of the ninth switching transistor T9 is electrically connected to the third reference signal terminal VGL, a control terminal of the ninth switching transistor T9 is electrically connected to the reset signal terminal, and a second terminal of the ninth switching transistor T9 is electrically connected to the first node N1;

a first end of the first capacitor C1 is electrically connected to the first node N1, and a second end of the first capacitor C1 is electrically connected to the Output signal end Output;

a first terminal of the second capacitor C2 is electrically connected to the third reference signal terminal VGL, and a second terminal of the second capacitor C2 is electrically connected to the second node N2.

The above is merely an example of the specific structure of the shift register provided in the embodiment of the present invention, and in the specific implementation, the specific structure of the shift register is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.

Specifically, in order to make the manufacturing process uniform, in the driving circuit provided in the embodiment of the present invention, as shown in fig. 3 to5, all the transistors may be N-type transistors, and of course, all the transistors may also be P-type transistors, which is not limited herein.

Specifically, in the driving circuit provided by the embodiment of the present invention, the P-type transistor is turned on by a low level signal and turned off by a high level signal; the N-type transistor is turned on under the action of a high-level signal and is turned off under the action of a low-level signal.

Specifically, in the driving circuit provided in the embodiment of the present invention, the odd frequency conversion Transistor TSO, the even frequency conversion Transistor TSE, the first frequency conversion Transistor TS1, the second frequency conversion Transistor TS2, and the first to ninth switching transistors T1 to T9 may be Thin Film Transistors (TFTs) or Metal Oxide semiconductor field effect transistors (MOS), and are not limited herein. The control terminal of each transistor is used as a gate, the first terminal of each transistor is used as a source, and the second terminal of each transistor is used as a drain, or the first terminal of each transistor is used as a drain and the second terminal of each transistor is used as a source, according to the type of each transistor and the signal of the control terminal of each transistor, which is not particularly distinguished herein.

Based on the same inventive concept, the embodiment of the invention further provides a display panel, which comprises any one of the driving circuits, a plurality of scanning lines and a plurality of sub-pixels; an Output signal end Output of one shift register in the driving circuit is correspondingly and electrically connected with one scanning line, and one scanning line is correspondingly and electrically connected with one row of sub-pixels.

The embodiment of the invention also provides a display driving method of the display panel, which comprises the following steps:

determining a user gaze area and a non-user gaze area;

when driving a driving circuit corresponding to a non-user watching area, controlling a shift register of the A group of sub-driving circuits to output a scanning signal;

when the driving circuit corresponding to the non-user watching area is converted into the driving circuit corresponding to the user watching area, the variable frequency control signal end is loaded with the variable frequency signal so as to provide the scanning trigger signal to the shift register in the other group of sub-driving circuits;

when driving a driving circuit corresponding to a user watching area, controlling a shift register of the B group of sub-driving circuits to output a scanning signal; wherein A and B are integers, and A is more than or equal to1 and B is more than or equal to N;

when the driving circuit corresponding to the driving user watching area is converted into the driving circuit corresponding to the non-user watching area, the reset signal ends corresponding to the A group of sub-driving circuits are loaded with signals of a first level, and the reset signal ends corresponding to the other groups of sub-driving circuits are loaded with signals of a second level.

According to the display driving method of the display panel provided by the embodiment of the invention, according to the display area watched by the user at present, the shift register of the plurality of sets of sub-driving circuits is controlled to output the scanning signals only by the driving circuit corresponding to the user watching area, and the shift register of the less sets of sub-driving circuits is controlled to output the scanning signals by the driving circuit corresponding to the non-user watching area, so that the high refreshing frequency is realized in the user watching area, and the data transmission bandwidth, the equipment power consumption and the like are greatly reduced.

In a specific implementation, when N is 2, a is 1, and B is 2, the shift registers of all the sub-driver circuits in the group are controlled to output the scan signals by the driver circuit corresponding to the user attention area, and the shift registers of only one of the sub-driver circuits in the non-user attention area are controlled to output the scan signals by the driver circuit corresponding to the non-user attention area. When N is greater than 2, taking N as 4 as an example, a may be 2, and B may be 3, the driving circuit corresponding to the user watching area controls the shift registers of the three groups of sub-driving circuits to output the scanning signals, and the driving circuit corresponding to the non-user watching area controls the shift registers of the two groups of sub-driving circuits to output the scanning signals; or A may be 1 and B may be 4; in practical application, when N is greater than 2, the numerical values of A and B can be designed and determined according to actual needs as long as 1 is greater than or equal to A and B is less than or equal to N, and the numerical values are not limited herein.

In a specific implementation, when N is 2, in the driving circuit corresponding to the user watching area, when the first-stage shift register outputs the scanning signal, the signal of the second level is loaded to the frequency conversion control signal end.

As shown in fig. 3 to5, when all the transistors in the driving circuit are N-type transistors, the signal of the first level may be a low level signal, and the signal of the second level may be a high level signal.

In specific implementation, for N adjacent display frames, in different display frames, in the driving circuit corresponding to the non-user watching area, the shift registers of the sub-driving circuits in different groups are controlled to output scanning signals.

Taking N as an example, dividing 2 adjacent display frames into odd frames and even frames, in the odd frames, in the driving circuit corresponding to the non-user watching area, only controlling the shift register of the odd sub-driving circuit to output the scanning signal; in the even-numbered frame, in the drive circuit corresponding to the non-user gaze region, only the shift register of the even-numbered sub-drive circuit may be controlled to output the scan signal.

In an implementation, a sensor such as a pupil tracking camera may be used to determine the user-gazing area and the non-user-gazing area, which is not limited herein.

The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is intended to better explain the present invention, but not to limit the present invention.

The first embodiment,

A user gaze area and a non-user gaze area are determined.

And determining a driving circuit corresponding to the user watching area, wherein a shift register contained in the driving circuit corresponding to the user watching area is a shift register SR (P) -SR (M), and P is more than or equal to1 and less than M. The shift registers included in the driving circuit corresponding to the non-user watching region are shift registers SR (1) -SR (P-1) and shift registers SR (M +1) -SR (T), where T is the total number of shift registers in the driving circuit.

When driving a driving circuit corresponding to a non-user watching area, only controlling the shift register of one group of sub-driving circuits to output scanning signals; when driving the driving circuits corresponding to the user watching area, the shift registers of all the sub-driving circuits are controlled to output scanning signals, and the following description will take two adjacent display frames, an odd frame and an even frame as an example.

The following describes the operation of the driving circuit provided by the embodiment of the present invention with reference to the signal timing diagrams shown in fig. 6 and 7 by taking the structure of the driving circuit shown in fig. 4 as an example, where 1 denotes a high level and 0 denotes a low level in the following description. It should be noted that 1 and 0 are logic levels, which are only used to better explain the specific operation of the embodiment of the present invention, and not specific voltage values. Fig. 6 is a timing diagram of signals in an odd frame To, and fig. 7 is a timing diagram of signals in an even frame Te. The signal of the first reference signal terminal CN is a high level signal, the signal of the second reference signal terminal CNB is a low level signal, and the signal of the third reference signal terminal VGL is a low level signal. In fig. 6 and fig. 7, G (1), G (2), G (p), G (m), etc. are signals Output by the Output signal terminal Output of each stage of the shift register, for example, G (1) is a signal Output by the shift register SR (1), G (p) is a signal Output by the shift register SR (p), G (m) is a signal Output by the shift register SR (m), and the rest of the same is omitted for brevity. In the driving circuit shown in fig. 4, the first clock signal terminal CLK1 of the odd-numbered stage shift register is electrically connected to one of the clock terminals CK1 and CK2, and the second clock signal terminal CLK2 is electrically connected to the other clock terminal. The first clock signal terminal CLK1 of the even-numbered stage shift register is electrically connected to one of the clock terminal CK3 and the clock terminal CK4, and the second clock signal terminal CLK2 is electrically connected to the other clock terminal.

Specifically, the odd first low frequency display period To-1, the odd high frequency display period To-2, and the odd second low frequency display period To-3 in the signal timing diagram shown in fig. 6 are selected, and the even first low frequency display period Te-1, the even high frequency display period Te-2, and the even second low frequency display period Te-3 in the signal timing diagram shown in fig. 7 are selected for explanation.

When a driving circuit comprising shift registers SR (1) -SR (P-1) is driven in an odd first low-frequency display stage To-1, only the shift registers of the odd sub-driving circuits are controlled To output scanning signals; in the odd high-frequency display stage To-2, when driving a driving circuit comprising shift registers SR (P) -SR (M), controlling the shift registers of the odd sub-driving circuit and the even sub-driving circuit To output scanning signals; in the odd-numbered second low-frequency display stage To-3, when driving circuits comprising the shift registers SR (M +1) -SR (T), only the shift registers of the odd-numbered sub-driving circuits are controlled To output scanning signals; when a driving circuit comprising shift registers SR (1) -SR (P-1) is converted into a driving circuit comprising shift registers SR (P) -SR (M), loading a high-level signal to an odd-number frequency conversion control signal end SWO so as to provide the high-level signal output by the shift register in the odd-number sub-driving circuit as a scanning trigger signal to an Input signal end Input of the shift register in an even-number sub-driving circuit; when the driving circuit including the shift registers SR (P) -SR (M) is driven to drive the driving circuit including the shift registers SR (M +1) -SR (T), a high level signal is loaded to the even reset signal end R2 corresponding to the even sub-driving circuit, and a low level signal is loaded to the odd reset signal end R1 corresponding to the odd sub-driving circuit.

When the driving circuit comprising the shift registers SR (1) -SR (P-1) is driven in the even-numbered first low-frequency display stage Te-1, only the shift registers of the even-numbered sub-driving circuits are controlled to output scanning signals; when the driving circuit comprising the shift registers SR (P) -SR (M) is driven in the even high-frequency display stage Te-2, the shift registers of the odd sub-driving circuit and the even sub-driving circuit are controlled to output scanning signals; when the driving circuit comprising the shift registers SR (M +1) -SR (T) is driven in the even second low-frequency display stage Te-3, only the shift registers of the even sub-driving circuits are controlled to output scanning signals; when a driving circuit comprising shift registers SR (1) -SR (P-1) is converted into a driving circuit comprising shift registers SR (P) -SR (M), a high-level signal is loaded on an even frequency conversion control signal end SWE, so that the high-level signal output by the shift registers in the even sub-driving circuit is used as a scanning trigger signal to be supplied to an Input signal end Input of the shift register in the odd sub-driving circuit; when the driving circuit including the shift registers SR (P) -SR (M) is driven to drive the driving circuit including the shift registers SR (M +1) -SR (T), a high level signal is loaded to the odd reset signal end R1 corresponding to the odd sub-driving circuit, and a low level signal is loaded to the even reset signal end R2 corresponding to the even sub-driving circuit.

For any stage of the shift register, when the first node N1 is at a high level, the third switching transistor T3 and the sixth switching transistor T6 are turned on. The turned-on sixth switching transistor T6 provides a low level signal to the second node N2, making the second node N2 low, and the fourth and fifth switching transistors T4 and T5 are turned off. The turned-on third switching transistor T3 supplies the signal of the first clock signal terminal CLK1 to the Output signal terminal Output and the control terminal of the eighth switching transistor T8. When the signal of the first clock signal terminal CLK1 is at a high level, the eighth switching transistor T8 is turned on to supply a low level signal to the second node N2. When the signal of the first clock signal terminal CLK1 is a low level signal, the eighth switching transistor T8 is turned off. When the first node N1 is at a low level, the third and sixth switching transistors T3 and T6 are turned off.

For any stage of shift register, when the second node N2 is at a high level, the fourth switching transistor T4 and the fifth switching transistor T5 are turned on, the turned-on fourth switching transistor T4 provides a low level signal to the Output signal terminal Output, so that the shift register outputs the low level signal, and the eighth switching transistor T8 is turned off. The turned-on fifth switching transistor T5 provides a low level signal to the first node N1, making the first node N1 low. When the second node N2 is at a low level, the fourth switching transistor T4 and the fifth switching transistor T5 are turned off.

Hereinafter, only the signals of the first node N1 and the second node N2 in the shift register are at a high level or a low level, and the description of turning on or off the third switching transistor T3, the fourth switching transistor T4, the fifth switching transistor T5, the sixth switching transistor T6, and the eighth switching transistor T8 in the shift register is omitted.

As shown in fig. 6 and 7, before the odd frame To and the even frame Te start, when R1 is equal To1 and R2 is equal To1, the ninth switching transistors T9 of all the shift registers in the driving circuit are turned on, and a low level signal is supplied To the first node N1 To reset all the shift registers.

In the odd frame To, SWE is 0, and all the even frequency conversion transistors TSE in the driving circuit are turned off.

In the odd first low-frequency display period To-1, when R1 is equal To 0, the ninth switching transistor T9 in the odd shift register stage is turned off; when R2 is equal to 0, the ninth switching transistor T9 in the even-numbered stage shift register is turned off; when SWO is equal to 0, the odd frequency conversion transistors TSO are all cut off; when STV2 is 0, CK3 is 0, and CK4 is 0, no scan signal is output from the even-numbered stage shift register.

The working process of the odd-numbered shift registers is described below by taking the shift register SR (1) and the shift register SR (3) as an example, and in the odd-numbered first low-frequency display stage To-1, the odd-numbered high-frequency display stage To-2, and the odd-numbered second low-frequency display stage To-3, the working process of the other adjacent two-stage odd-numbered shift registers can refer To the working process of the shift register SR (1) and the shift register SR (3).

In the odd first phase to1, STV1 is 1, CK1 is 0 and CK2 is 0.

When STV1 is equal to1, the first switching transistor T1 of the shift register SR (1) is turned on, a high level signal is supplied to the first node N1, the first node N1 is set to a high level, and the second node N2 is set to a low level. When CK1 is equal to 0, the shift register SR (1) outputs a low level signal. CK2 is 0, and the seventh switching transistor T7 of the shift register SR (1) is turned off.

When the Input signal terminal Input of the shift register SR (3) receives the low level signal output from the shift register SR (1), the first node N1 remains at the low level, and the shift register SR (3) does not output the scan signal, the second switching transistor T2 of the shift register SR (1) is turned off.

In the odd second stage to2, STV1 is 0, CK1 is 1, and CK2 is 0.

When STV1 is equal to 0, the first switching transistor T1 of the shift register SR (1) is turned off. The first node N1 is kept at a high level, and the second node N2 is kept at a low level. When CK1 is equal to1, the Output signal terminal Output of the shift register SR (1) outputs a high level signal. CK2 is 0, and the seventh switching transistor T7 of the shift register SR (1) is turned off.

The Input signal terminal Input of the shift register SR (3) receives the high level signal output from the shift register SR (1), the first switching transistor T1 of the shift register SR (3) is turned on, the high level signal is supplied to the first node N1, the first node N1 is at a high level, and the second node N2 is at a low level. When CK2 is equal to 0, and the shift register SR (3) outputs a low level signal, the second switching transistor T2 of the shift register SR (1) is turned off.

In the odd third stage to3, STV1 is 0, CK1 is 0, and CK2 is 0.

When STV1 is equal to 0, the first switching transistor T1 of the shift register SR (1) is turned off. The first node N1 is kept high, and the second node N2 is low. When CK1 is equal to 0, the Output signal terminal Output of the shift register SR (1) outputs a low level signal. CK2 is 0, and the seventh switching transistor T7 of the shift register SR (1) is turned off.

The Input signal terminal Input of the shift register SR (3) receives the low level signal output from the shift register SR (1), and the first switching transistor T1 of the shift register SR (3) is turned off. The first node N1 is kept high, and the second node N2 is low. CK2 is equal to 0, the shift register SR (3) outputs a low level signal, and the second switching transistor T2 of the shift register SR (1) is turned off. When CK1 is equal to 0, the seventh switching transistor T7 of the shift register SR (3) is turned off.

In the odd fourth stage to4, STV1 is 0, CK1 is 0, and CK2 is 1.

The first node N1 of the shift register SR (3) is kept at a high level, and the second node N2 is at a low level. When CK2 is equal to1, the shift register SR (3) outputs a high level signal, and the second switching transistor T2 of the shift register SR (1) is turned on. When CK1 is equal to 0, the seventh switching transistor T7 of the shift register SR (3) is turned off.

The second switching transistor T2, in which the shift register SR (1) is turned on, supplies a low level signal to the first node N1, making the first node N1 low. When STV1 is equal to 0, the first switching transistor T1 of the shift register SR (1) is turned off. When CK2 is equal to1, the seventh switching transistor T7 is turned on, a high level signal is supplied to the second node N2, the second node N2 is set to a high level, and the shift register SR (1) outputs a low level.

After the odd-numbered fourth stage to4, the first node N1 of the shift register SR (1) is maintained at a low level, the second node N2 is maintained at a high level, and the shift register SR (1) maintains outputting a low level signal.

In the odd high frequency display stage To-2, the operation process of the even-numbered stage shift register in the odd high frequency display stage To-2 is described below by taking the shift register SR (P +1) and the shift register SR (P +3) as examples. The first clock signal terminal CLK1 of the shift register SR (P +1) is electrically connected to the clock terminal CK3, and the second clock signal terminal CLK2 is electrically connected to the clock terminal CK 4; the first clock signal terminal CLK1 of the shift register SR (P +3) is electrically connected to the clock terminal CK4, and the second clock signal terminal CLK2 is electrically connected to the clock terminal CK 3.

In the odd fifth phase to5, SWO is 1, CK3 is 0, and CK4 is 0. The odd-numbered stage shift register sr (p) outputs a high level signal.

When SWO is equal to1, the odd frequency conversion transistor TSO is turned on, the high level signal output from the odd shift register SR (P) is supplied to the Input signal terminal Input of the even shift register SR (P +1), the first switching transistor T1 of the shift register SR (P +1) is turned on, the high level signal is supplied to the first node N1, the first node N1 is at a high level, and the second node N2 is at a low level. CK3 is 0, and shift register SR (P +1) outputs a low level signal. CK4 is equal to 0, and the seventh switching transistor T7 is turned off.

After the odd fifth phase to5, SW is equal to 0 and the odd frequency conversion transistors TSO are all turned off.

In the odd sixth phase to6, CK3 is 1 and CK4 is 0. The first node N1 of the shift register SR (P +1) is kept at a high level, and the second node N2 is at a low level. CK3 is equal to1, and the shift register SR (P +1) outputs a high level signal. CK4 is equal to 0, and the seventh switching transistor T7 is turned off.

The Input signal terminal Input of the shift register SR (P +3) receives the high level signal output from the shift register SR (P +1), the first switching transistor T1 of the shift register SR (P +3) is turned on, the first node N1 is kept at a high level, and the second node N2 is kept at a low level. CK4 is equal to 0, the shift register SR (P +3) keeps outputting the low level signal, and the second switching transistor T2 of the shift register SR (P +1) is turned off.

In the odd seventh phase to7, CK3 is 0 and CK4 is 0.

The first node N1 of the shift register SR (P +1) is kept at a high level, and the second node N2 is at a low level. CK3 is 0, and shift register SR (P +1) outputs a low level signal. CK4 is equal to 0, and the seventh switching transistor T7 is turned off.

The first switching transistor T1 of the shift register SR (P +3) is turned off, the first node N1 is maintained at a high level, and the second node N2 is at a low level. CK4 is equal to 0, the shift register SR (P +3) outputs a low level signal, and the second switching transistor T2 of the shift register SR (P +1) is turned off.

In the odd eighth phase to8, CK3 is 0 and CK4 is 1.

The first node N1 of the shift register SR (P +3) is kept at a high level, and the second node N2 is at a low level. When CK4 is equal to1, the shift register SR (P +3) outputs a high level signal, and the second switching transistor T2 of the shift register SR (P +1) is turned on.

The second switching transistor T2, in which the shift register SR (P +1) is turned on, provides a low level signal to the first node N1, making the first node N1 low. When CK4 is equal to1, the seventh switching transistor T7 is turned on, a high level signal is supplied to the second node N2, the second node N2 is set to a high level, and the shift register SR (P +1) outputs a low level signal.

After the odd eighth phase to8, the second node N2 of the shift register SR (P +1) is maintained at a high level, the first node N1 is maintained at a low level, and the shift register SR (P +1) maintains outputting a low level signal.

In the odd second low-frequency display stage To-3, the even-numbered shift registers SR (M +1) -SR (t) are controlled not To output the scan signal, and the operation process of the even-numbered shift register SR (M +1) is taken as an example for explanation.

In the odd ninth stage to9, CK3 is 1, CK4 is 0, and the even stage shift register SR (M-1) outputs a high level signal. The Input signal terminal Input of the even-numbered stage shift register SR (M +1) receives the high level signal, the first switching transistor T1 is turned on, the high level signal is supplied to the first node N1, the first node N1 is set to the high level, the second node N2 is set to the low level, CK4 is 0, and the shift register SR (M +1) outputs the low level signal.

In the odd tenth phase to10, R2 equals 1, CK3 equals 0, and CK4 equals 0. When R2 is equal to1, the ninth switching transistors T9 in the even-numbered stage shift register are all turned on, and a low level signal is supplied to the first node N1, the first node N1 of the shift register SR (M +1) becomes low, and the second node N2 remains low, so that the shift register SR (M +1) does not output a scan signal. The first switching transistor T1 of the even-numbered stage shift register SR (M +3) is turned off and does not output the scan signal.

In the even frame Te, SWO is 0, and the odd inverter transistors TSO in the driving circuit are all turned off.

And in the even first low-frequency display stage Te-1, the even shift registers in the shift registers SR (1) -SR (P-1) are controlled to output scanning signals in sequence, and the odd shift registers in the shift registers SR (1) -SR (P-1) do not output scanning signals.

The working process of the shift register of the even level is described below by taking the shift register SR (2) and the shift register SR (4) as an example, and in the even first low-frequency display stage Te-1, the even high-frequency display stage Te-2, and the even second low-frequency display stage Te-3, the working process of the shift register of the two adjacent even levels can refer to the working process of the shift register SR (2) and the shift register SR (4).

In the even first stage te1, STV2 is 1, CK3 is 0, and CK4 is 0.

When STV2 is 1, the first switching transistor T1 of the shift register SR (2) is turned on, a high level signal is supplied to the first node N1, the first node N1 is set to a high level, and the second node N2 is set to a low level. When CK3 is equal to 0, the shift register SR (1) outputs a low level signal. CK4 is 0, and the seventh switching transistor T7 of the shift register SR (2) is turned off.

When the Input signal terminal Input of the shift register SR (4) receives the low level signal output from the shift register SR (2), the first node N1 remains at the low level, and the shift register SR (4) does not output the scan signal, the second switching transistor T2 of the shift register SR (2) is turned off.

In the even second stage te2, STV2 is 0, CK3 is 1, and CK4 is 0.

When STV2 is equal to 0, the first switching transistor T1 of the shift register SR (2) is turned off. The first node N1 is kept at a high level, and the second node N2 is kept at a low level. When CK3 is equal to1, the Output signal terminal Output of the shift register SR (2) outputs a high level signal. CK4 is 0, and the seventh switching transistor T7 of the shift register SR (2) is turned off.

The Input signal terminal Input of the shift register SR (4) receives the high level signal output from the shift register SR (2), the first switching transistor T1 of the shift register SR (4) is turned on, the high level signal is supplied to the first node N1, the first node N1 is at a high level, and the second node N2 is at a low level. When CK4 is equal to 0, and the shift register SR (4) outputs a low level signal, the second switching transistor T2 of the shift register SR (2) is turned off.

In the even third stage te3, STV2 is 0, CK3 is 0, and CK4 is 0.

When STV2 is equal to 0, the first switching transistor T1 of the shift register SR (2) is turned off. The first node N1 is kept high, and the second node N2 is low. When CK3 is equal to 0, the Output signal terminal Output of the shift register SR (2) outputs a low level signal. CK4 is 0, and the seventh switching transistor T7 of the shift register SR (2) is turned off.

The Input signal terminal Input of the shift register SR (4) receives the low level signal output from the shift register SR (2), and the first switching transistor T1 of the shift register SR (4) is turned off. The first node N1 is kept high, and the second node N2 is low. CK4 is equal to 0, the shift register SR (3) outputs a low level signal, and the second switching transistor T2 of the shift register SR (2) is turned off. When CK3 is equal to 0, the seventh switching transistor T7 of the shift register SR (4) is turned off.

In the even fourth stage te4, STV2 is 0, CK1 is 0, and CK2 is 1.

The first node N1 of the shift register SR (4) is kept at a high level, and the second node N2 is at a low level. When CK4 is equal to1, the shift register SR (4) outputs a high level signal, and the second switching transistor T2 of the shift register SR (2) is turned on. When CK2 is equal to 0, the seventh switching transistor T7 of the shift register SR (4) is turned off.

The second switching transistor T2, in which the shift register SR (2) is turned on, supplies a low level signal to the first node N1, making the first node N1 low. When STV2 is equal to 0, the first switching transistor T1 of the shift register SR (2) is turned off. When CK4 is equal to1, the seventh switching transistor T7 is turned on, a high level signal is supplied to the second node N2, the second node N2 is set to a high level, and the shift register SR (2) outputs a low level.

After the even fourth stage te4, the first node N1 of the shift register SR (2) is kept at the low level, the second node N2 is kept at the high level, and the shift register SR (2) keeps outputting the low level signal.

In the even high frequency display stage Te-2, the operation process of the odd shift register in the even high frequency display stage Te-2 is described below by taking the shift register SR (P) and the shift register SR (P +2) as examples. The first clock signal terminal CLK1 of the shift register SR (P) is electrically connected to the clock terminal CK1, and the second clock signal terminal CLK2 is electrically connected to the clock terminal CK 2; the first clock signal terminal CLK1 of the shift register SR (P +2) is electrically connected to the clock terminal CK2, and the second clock signal terminal CLK2 is electrically connected to the clock terminal CK 1.

In the even fifth stage te5, SWE is 1, CK1 is 0, and CK2 is 0. The even-numbered stage shift register SR (P-1) outputs a high level signal.

When SWE is 1, the even inverter transistor TSE is turned on, the high level signal output from the even stage shift register SR (P-1) is supplied to the Input signal terminal Input of the odd stage shift register SR (P), the first switching transistor T1 of the shift register SR (P) is turned on, the high level signal is supplied to the first node N1, the first node N1 is at a high level, and the second node N2 is at a low level. CK3 is 0, and shift register sr (p) outputs a low level signal. CK4 is equal to 0, and the seventh switching transistor T7 is turned off.

After the even fifth stage te5, SWE is 0 and the even inverter transistors TSE are all turned off.

In the even sixth stage te6, CK1 is 1 and CK2 is 0. The first node N1 of the shift register sr (p) is kept at a high level, and the second node N2 is at a low level. CK1 is equal to1, and the shift register sr (p) outputs a high level signal. CK2 is equal to 0, and the seventh switching transistor T7 is turned off.

The Input signal terminal Input of the shift register SR (P +2) receives the high level signal output by the shift register SR (P), and the first switch transistor T1 of the shift register SR (P +2) is turned on, so that the first node N1 is at a high level and the second node N2 is at a low level. CK2 is equal to 0, the shift register SR (P +2) outputs a low level signal, and the second switching transistor T2 of the shift register SR (P) is turned off.

In the even seventh stage te7, CK1 is 0 and CK2 is 0.

The first node N1 of the shift register sr (p) is kept at a high level, and the second node N2 is at a low level. CK1 is 0, and shift register sr (p) outputs a low level signal. CK1 is equal to 0, and the seventh switching transistor T7 is turned off.

The first switching transistor T1 of the shift register SR (P +2) is turned off, the first node N1 is maintained at a high level, and the second node N2 is at a low level. CK2 is equal to 0, the shift register SR (P +2) outputs a low level signal, and the second switching transistor T2 of the shift register SR (P) is turned off.

In the even eighth stage te8, CK1 is 0 and CK2 is 1.

The first node N1 of the shift register SR (P +2) is kept at a high level, and the second node N2 is at a low level. When CK2 is equal to1, the shift register SR (P +2) outputs a high level signal, and the second switching transistor T2 of the shift register SR (P) is turned on.

The turned-on second switching transistor T2 of the shift register sr (p) provides a low level signal to the first node N1, which makes the first node N1 low. When CK2 is equal to1, the seventh switching transistor T7 is turned on, a high level signal is supplied to the second node N2, the second node N2 is set to a high level, and the shift register sr (p) outputs a low level signal.

After the even eighth stage te8, the second node N2 of the shift register sr (p) remains at the high level, the first node N1 remains at the low level, and the shift register sr (p) remains outputting the low level signal.

In the even second low-frequency display stage Te-2, the odd shift registers SR (M +1) -SR (t) are controlled not to output the scan signal, and the operation process of the odd shift register SR (M +2) is taken as an example for explanation.

In the even ninth stage te9, CK1 is 0, CK2 is 1, and the odd shift register sr (m) outputs a high level signal. The Input signal terminal Input of the odd-numbered shift register SR (M +2) receives the high level signal, the first switching transistor T1 is turned on, the high level signal is supplied to the first node N1, the first node N1 is set to the high level, the second node N2 is set to the low level, CK1 is 0, and the shift register SR (M +2) outputs the low level signal.

In the even tenth stage te10, R1 is 1, CK1 is 0, and CK2 is 0. When R1 is equal to1, the ninth switching transistors T9 in the odd-numbered shift registers are all turned on, and a low level signal is supplied to the first node N1, the first node N1 of the shift register SR (M +2) becomes low, and the second node N2 remains low, so that the shift register SR (M +2) does not output a scan signal. The first switching transistor T1 of the even-numbered stage shift register SR (M +4) is turned off and does not output the scan signal.

Example II,

The present embodiment is modified with respect to some embodiments in the first embodiment. Only the differences between the present embodiment and the first embodiment will be described below, and the descriptions of the same parts are omitted here.

The following describes the operation of the driving circuit provided in the embodiment of the present invention with reference to the signal timing diagrams shown in fig. 8 and 9, taking the structure of the driving circuit shown in fig. 5 as an example, where 1 denotes a high level and 0 denotes a low level in the following description. It should be noted that 1 and 0 are logic levels, which are only used to better explain the specific operation of the embodiment of the present invention, and not specific voltage values. Fig. 8 is a timing chart of signals in the odd-numbered frame To, and fig. 9 is a timing chart of signals in the even-numbered frame Te. The signal of the first reference signal terminal CN is a high level signal, the signal of the second reference signal terminal CNB is a low level signal, and the signal of the third reference signal terminal VGL is a low level signal. In fig. 8 and fig. 9, G (1), G (2), G (p), G (m), etc. are signals Output by the Output signal terminal Output of each stage of the shift register, for example, G (1) is a signal Output by the shift register SR (1), G (p) is a signal Output by the shift register SR (p), G (m) is a signal Output by the shift register SR (m), and the rest of the same is omitted. In the driving circuit shown in fig. 5, the first clock signal terminal CLK1 of the odd-numbered stage shift register is electrically connected to one of the clock terminals CK1 and CK2, and the second clock signal terminal CLK2 is electrically connected to the other clock terminal. The first clock signal terminal CLK1 of the even-numbered stage shift register is electrically connected to one of the clock terminal CK3 and the clock terminal CK4, and the second clock signal terminal CLK2 is electrically connected to the other clock terminal.

Specifically, the odd first low frequency display period To-1, the odd high frequency display period To-2, and the odd second low frequency display period To-3 in the signal timing diagram shown in fig. 8 are selected, and the even first low frequency display period Te-1, the even high frequency display period Te-2, and the even second low frequency display period Te-3 in the signal timing diagram shown in fig. 9 are selected for explanation.

When the driving circuit driving the shift registers SR (1) -SR (P-1) is switched to drive the driving circuit including the shift registers SR (P) -SR (m), the frequency conversion control signal terminal SW is loaded with a high level signal, so that the high level signal output from the shift register in the odd-numbered sub-driving circuit is provided to the control terminal of the second frequency conversion transistor TS2, and the high level signal of the first reference signal terminal CN is provided as a scan trigger signal to the first node N1 of the shift register in the even-numbered sub-driving circuit.

When the driving circuit including the shift registers SR (1) -SR (P-1) is driven to drive the driving circuit including the shift registers SR (P) -SR (m), the frequency conversion control signal terminal SW is loaded with a high level signal, so that the high level signal output from the shift register in the even-numbered sub-driving circuit is provided to the control terminal of the second frequency conversion transistor TS2, and the high level signal of the first reference signal terminal CN is provided as a scan trigger signal to the first node N1 of the shift register in the odd-numbered sub-driving circuit.

In the odd first low-frequency display period To-1, SW is equal To 0, all the first frequency conversion transistors TS1 and the second frequency conversion transistors TS2 in the driving circuit are turned off.

In the odd fifth phase to5, SW is 1, CK3 is 0, and CK4 is 0. The odd-numbered stage shift register sr (p) outputs a high level signal.

When SW is equal to1, the first frequency conversion transistor TS1 is turned on, the high level signal output from the odd-numbered stage shift register SR (P) is provided to the control terminal of the second frequency conversion transistor TS2, the second frequency conversion transistor TS2 is turned on, the high level signal of the first reference signal terminal CN is provided to the first node N1 of the even-numbered stage shift register SR (P +1), the first node N1 is set to high level, and the second node N2 is set to low level. CK3 is 0, and shift register SR (P +1) outputs a low level signal. CK4 is equal to 0, and the seventh switching transistor T7 is turned off.

After the odd fifth phase to5, SW is 0, and both the first frequency conversion transistor TS1 and the second frequency conversion transistor TS2 are turned off.

In the even-numbered first low-frequency display period Te-1, SW is 0, and both the first frequency-changing transistor TS1 and the second frequency-changing transistor TS2 are turned off.

In the even fifth stage te5, SW is 1, CK1 is 0, and CK2 is 0. The even-numbered stage shift register SR (P-1) outputs a high level signal.

When SW is equal to1, the first frequency conversion transistor TS1 is turned on, the high level signal output from the even-numbered stage shift register SR (P-1) is supplied to the control terminal of the second frequency conversion transistor TS2, the second frequency conversion transistor TS2 is turned on, the high level signal of the first reference signal terminal CN is supplied to the first node N1 of the odd-numbered stage shift register SR (P), the first node N1 is set to the high level, and the second node N2 is set to the low level. CK3 is 0, and shift register sr (p) outputs a low level signal. CK4 is equal to 0, and the seventh switching transistor T7 is turned off.

After the even fifth stage te5, SW is 0, and both the first frequency translating transistor TS1 and the second frequency translating transistor TS2 are turned off.

The display device comprises the frequency conversion circuit and N groups of sub-drive circuits which can output scanning signals independently, in one display frame, most groups of sub-drive circuits can output the scanning signals to realize high refresh frequency, only a few groups of sub-drive circuits can output the scanning signals, and other groups of sub-drive circuits do not output the scanning signals to realize low refresh frequency. By providing the frequency conversion circuit, when a small number of sub-drive circuits output scanning signals, the sub-drive circuits of other groups can also output scanning signals. By arranging a group of sub-driving circuits corresponding to a reset signal end, when each group of sub-driving circuits outputs scanning signals, part of the sub-driving circuits can be controlled to stop outputting the scanning signals. And then according to the display area watched by the user at present, the shift register of the plurality of sub-drive circuits is controlled to output the scanning signals only by the drive circuit corresponding to the user watching area, and the shift register of the less sub-drive circuits is controlled to output the scanning signals by the drive circuit corresponding to the non-user watching area, so that the high refresh frequency is realized in the user watching area, and the data transmission bandwidth, the equipment power consumption and the like are greatly reduced.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A driving circuit is characterized by comprising a frequency conversion circuit and N groups of sub-driving circuits, wherein N is a positive integer and is more than or equal to 2;

2. The driving circuit according to claim 1, wherein the frequency conversion circuit provides a scan trigger signal to a shift register in another set of the sub-driving circuits according to a signal at a frequency conversion control signal terminal and a signal at an output signal terminal of one set of the sub-driving circuits, and specifically comprises:

3. The driving circuit of claim 2, wherein N-2, the N groups of driving circuits comprise odd and even sub-driving circuits; wherein:

4. The driving circuit of claim 2, wherein the frequency conversion circuit comprises N groups of sub-frequency conversion circuits, one group of the sub-frequency conversion circuits corresponds to one group of the sub-driving circuits, and one group of the sub-frequency conversion circuits corresponds to one of the frequency conversion control signal terminals; the sub-frequency conversion circuit is configured to conduct the output signal terminal of the shift register of the corresponding group of sub-drive circuits with the input signal terminal of the shift register of the other group of sub-drive circuits under the signal control of the corresponding frequency conversion control signal terminal.

5. The drive circuit according to any of claims 2-4, wherein the N groups of sub-conversion circuits comprise an odd sub-conversion circuit and an even sub-conversion circuit, the odd sub-conversion circuit comprising a plurality of odd conversion transistors and the even sub-conversion circuit comprising a plurality of even conversion transistors;

6. The driving circuit of claim 2, wherein the frequency conversion circuit comprises a plurality of first frequency conversion transistors and a plurality of second frequency conversion transistors, all of the first frequency conversion transistors having control terminals electrically connected to one of the frequency conversion control signal terminals, and the second frequency conversion transistors having second terminals electrically connected to the first reference signal terminal;

7. The drive circuit according to claim 1, wherein the shift register includes: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, an eighth switching transistor, a ninth switching transistor, a first capacitor, and a second capacitor; wherein:

8. A display panel comprising the drive circuit according to any one of claims 1 to7, a plurality of scan lines and a plurality of sub-pixels; the output signal end of one shift register in the driving circuit is correspondingly and electrically connected with one scanning line, and one scanning line is correspondingly and electrically connected with one row of sub-pixels.

9. A display driving method of the display panel according to claim 8, comprising:

determining a user gaze area and a non-user gaze area;

10. The driving method according to claim 9, wherein N is 2, and when the first stage shift register outputs the scan signal in the driving circuit corresponding to the user's gaze region, the second level signal is applied to the variable frequency control signal terminal.

11. The driving method according to claim 9, wherein for N adjacent display frames, in the driving circuit corresponding to the non-user-gaze region in different display frames, the shift registers of different sets of sub-driving circuits are controlled to output the scan signals.