CN106601172B

CN106601172B - Shift register unit, driving method, grid driving circuit and display device

Info

Publication number: CN106601172B
Application number: CN201710001652.0A
Authority: CN
Inventors: 杜瑞芳; 王飞; 王萨萨; 马小叶
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2017-01-03
Filing date: 2017-01-03
Publication date: 2023-09-26
Anticipated expiration: 2037-01-03
Also published as: CN106601172A

Abstract

The invention provides a shift register unit, a driving method, a gate driving circuit and a display device. The shift register unit comprises a pull-up node input subunit which is respectively connected with a pull-up node, the odd line input end, the even line input end and a first level output end; resetting the subunit; pulling up the node pull-down subunit; a pull-down control node pull-down subunit; the pull-down node control subunit and the gate drive output subunit. Compared with the existing shift register unit which needs to adopt odd-numbered row pull-up nodes and even-numbered row pull-up nodes, the shift register unit, the driving method, the grid driving circuit and the display device have the advantages that the number of transistors is reduced, the layout space is saved, and narrow frames are conveniently realized.

Description

Shift register unit, driving method, grid driving circuit and display device

Technical Field

The present invention relates to the field of gate driving technologies, and in particular, to a shift register unit, a driving method, a gate driving circuit, and a display device.

Background

The GOA (Gate On Array) technology is to integrate a Gate driving circuit composed of TFTs (Thin Film Transistor, thin film transistors) On a glass substrate. The GOA technology has the advantages of reducing cost, improving the process yield of the module, being beneficial to realizing narrow frames and the like, and more display panels are developed and adopted.

The existing shift register unit has an odd row gate drive signal output and an even row gate drive signal output, and comprises two GOA units, each GOA unit comprising 17T1C, the existing shift register unit employing two pull-up nodes: the odd-numbered row pull-up nodes and the even-numbered row pull-up nodes, so that the number of transistors adopted by the existing shift register unit is excessive, which is unfavorable for saving GOA layout space and realizing a narrow frame.

Disclosure of Invention

The invention mainly aims to provide a shift register unit, a driving method, a grid driving circuit and a display device, and solves the problems that the existing shift register unit is unfavorable for saving GOA layout space and realizing a narrow frame due to excessive number of transistors.

In order to achieve the above object, the present invention provides a shift register unit for driving two adjacent rows of pixels, including an odd row input terminal, an even row input terminal, an odd row gate driving signal output terminal, an even row gate driving signal output terminal, a reset terminal, a first clock signal input terminal, and a second clock signal input terminal, the shift register unit further comprising:

The pull-up node input subunit is respectively connected with a pull-up node, the odd line input end, the even line input end and the first level output end;

the reset subunit is connected with the pull-up node, the reset end and the second level output end and is used for controlling the pull-up node to be connected with the second level output end under the control of a reset signal accessed by the reset end in a reset stage;

the pull-up node pull-down subunit is connected with the pull-up node, the odd line pull-down node, the even line pull-down node and the second level output end and is used for controlling the pull-up node to be connected with the second level output end when the potential of the odd line pull-down node and/or the potential of the even line pull-down node are/is the first level;

the pull-down control node pull-down subunit is respectively connected with the pull-up node, the odd line pull-down control node, the even line pull-down control node and the second level output end and is used for controlling the odd line pull-down control node and the even line pull-down control node to be connected with the second level output end when the potential of the pull-up node is a first level;

the pull-down node control subunit is respectively connected with an odd line voltage output end, an even line voltage output end, the pull-up node, the odd line pull-down control node, the even line pull-down control node, the odd line input end, the even line input end, the odd line pull-down node and the even line pull-down node; the method comprises the steps of,

And the grid driving output subunit is respectively connected with the odd-line pull-down node, the even-line pull-down node, the pull-up node, the odd-line grid driving signal output end, the even-line grid driving signal output end, the first clock signal input end and the second clock signal input end.

In implementation, the shift register unit of the present invention further includes: the starting subunit is respectively connected with the starting signal output end, the pull-up node and the second level output end and is used for controlling the pull-up node to be connected with the second level output end under the control of the starting signal output by the starting signal output end in a starting stage.

In practice, the shift register unit of the present invention further comprises an odd row carry out terminal, an even row carry out terminal and a carry out subunit, wherein,

the carry output subunit is respectively connected with the odd line carry output end, the even line carry output end, the pull-up node, the odd line pull-down node, the even line pull-down node, the first clock signal input end, the second clock signal input end and the second level output end, and is used for controlling the odd line carry output end to be connected with the first clock signal input end and controlling the even line carry output end to be connected with the second clock signal input end when the potential of the pull-up node is at a first level, controlling the odd line carry output end to be connected with the second level output end when the potential of the odd line pull-down node is at a first level, and controlling the even line carry output end to be connected with the second level output end when the potential of the even line pull-down node is at a first level.

In practice, the carry-out subunit comprises:

the grid electrode of the first odd-numbered row bit output transistor is connected with the pull-up node, the first electrode of the first odd-numbered row bit output transistor is connected with the first clock signal input end, and the second electrode of the first odd-numbered row bit output transistor is connected with the odd-numbered row carry output end;

the grid electrode of the second odd-numbered row carry output transistor is connected with the odd-numbered row pull-down node, the first electrode of the second odd-numbered row carry output transistor is connected with the odd-numbered row carry output end, and the second electrode of the second odd-numbered row carry output transistor is connected with the second level output end;

a third odd row carry output transistor, wherein the grid electrode of the third odd row carry output transistor is connected with the even row pull-down node, the first electrode of the third odd row carry output transistor is connected with the odd row carry output end, and the second electrode of the third odd row carry output transistor is connected with the second level output end;

the grid electrode of the first even-numbered row bit output transistor is connected with the pull-up node, the first electrode of the first even-numbered row bit output transistor is connected with the second clock signal input end, and the second electrode of the first even-numbered row bit output transistor is connected with the even-numbered row carry output end;

the grid electrode of the second even-numbered row carry output transistor is connected with the odd-numbered row pull-down node, the first electrode of the second even-numbered row carry output transistor is connected with the even-numbered row carry output end, and the second electrode of the second even-numbered row carry output transistor is connected with the second level output end; the method comprises the steps of,

and the grid electrode of the third even-numbered row carry output transistor is connected with the even-numbered row pull-down node, the first electrode of the third even-numbered row carry output transistor is connected with the even-numbered row carry output end, and the second electrode of the third even-numbered row carry output transistor is connected with the second level output end.

In practice, the reset subunit includes: a reset transistor, the grid electrode of which is connected with the reset end, the first electrode of which is connected with the second level output end, and the second electrode of which is connected with the pull-up node;

the pull-up node pull-down subunit includes:

the grid electrode of the first pull-up node pull-down transistor is connected with the odd-numbered row pull-down nodes, the first electrode of the first pull-up node pull-down transistor is connected with the second level output end, and the second electrode of the first pull-up node pull-down transistor is connected with the pull-up nodes; the method comprises the steps of,

the grid electrode of the second pull-up node pull-down transistor is connected with the even-numbered row pull-down nodes, the first electrode of the second pull-up node pull-down transistor is connected with the second level output end, and the second electrode of the second pull-up node pull-down transistor is connected with the pull-up nodes;

the pull-down control node pull-down subunit includes:

a first pull-down control node pull-down transistor, wherein a grid electrode is connected with the pull-up node, a first electrode is connected with a second level output end, and a second electrode is connected with the odd-row pull-down control node; the method comprises the steps of,

and the grid electrode of the second pull-down control node pull-down transistor is connected with the pull-up node, the first electrode is connected with the second level output end, and the second electrode is connected with the even-numbered row pull-down control node.

In implementation, the pull-down node control subunit includes:

the odd line pull-down control node control module is respectively connected with the odd line voltage output end and the odd line pull-down control node and is used for controlling the odd line pull-down control node to be connected with the odd line voltage output end when the odd line voltage output end outputs a first level;

The odd line pull-down node control module is respectively connected with the pull-up node, the odd line voltage output end, the odd line pull-down control node, the odd line pull-down node and the second level output end and is used for controlling the odd line pull-down node to be connected with the odd line voltage output end when the potential of the odd line pull-down control node is a first level and controlling the odd line pull-down node to be connected with the second level output end when the potential of the pull-up node is a first level;

the pull-down node input module is respectively connected with the odd line input end, the odd line pull-down node, the even line pull-down node and the second level output end and is used for controlling the odd line pull-down node and the even line pull-down node to be connected with the second level output end when an odd line input signal input by the odd line input end is of a first level;

the even-numbered row pull-down control node control module is respectively connected with the even-numbered row voltage output end and the even-numbered row pull-down control node and is used for controlling the even-numbered row pull-down control node to be connected with the even-numbered row voltage output end when the even-numbered row voltage output end outputs a first level; the method comprises the steps of,

And the even-numbered row pull-down node control module is respectively connected with the pull-up node, the even-numbered row voltage output end, the even-numbered row pull-down control node, the even-numbered row pull-down node and the second level output end and is used for controlling the even-numbered row pull-down node to be connected with the even-numbered row voltage output end when the potential of the even-numbered row pull-down control node is a first level and controlling the even-numbered row pull-down node to be connected with the second level output end when the potential of the pull-up node is the first level.

When in implementation, the odd-row pull-down control node control module comprises: the odd-row pull-down control node controls a transistor, a grid electrode and a first electrode are connected with the odd-row voltage output end, and a second electrode is connected with the odd-row pull-down control node;

the odd-line pull-down node control module comprises: the first odd-line pull-down node control transistor is characterized in that a grid electrode of the first odd-line pull-down node control transistor is connected with the odd-line pull-down control node, a first electrode of the first odd-line pull-down node control transistor is connected with the odd-line voltage output end, and a second electrode of the first odd-line pull-down node control transistor is connected with the odd-line pull-down node; and a second odd-line pull-down node control transistor having a gate connected to the pull-up node, a first pole connected to the odd-line pull-down node, and a second pole connected to the second level output terminal;

The pull-down node input module comprises:

an odd-line pull-down node input transistor, wherein a grid electrode is connected with the odd-line input end, a first electrode is connected with the odd-line pull-down node, and a second electrode is connected with a second level output end; the method comprises the steps of,

an even-numbered row pull-down node input transistor, wherein a grid electrode is connected with the even-numbered row input end, a first electrode is connected with the even-numbered row pull-down node, and a second electrode is connected with a second level output end;

the even number row pull-down control node control module comprises: the odd-numbered row pull-down control node controls a transistor, a grid electrode and a first electrode are connected with the even-numbered row voltage output end, and a second electrode is connected with the even-numbered row pull-down control node;

the even number row pull-down node control module comprises: the grid electrode of the first even-numbered row pull-down node control transistor is connected with the even-numbered row pull-down control node, the first electrode of the first even-numbered row pull-down node control transistor is connected with the even-numbered row voltage output end, and the second electrode of the first even-numbered row pull-down node control transistor is connected with the even-numbered row pull-down node; the method comprises the steps of,

and the second even-numbered row pull-down node control transistor is connected with the pull-up node, the first pole is connected with the even-numbered row pull-down node, and the second pole is connected with the second level output end.

When the input signals of the odd lines input by the odd line input end are the first level, the pull-up node input subunit is used for controlling the pull-up node to be connected with the first level output end, and when the input signals of the even lines input by the even line input end are the first level, the pull-up node is controlled to be connected with the first level output end.

In practice, the pull-up node input subunit includes:

the grid electrode of the first pull-up node input transistor is connected with the odd-number row input end, the first electrode of the first pull-up node input transistor is connected with the pull-up node, and the second electrode of the first pull-up node input transistor is connected with the first level output end;

the first end of the first storage capacitor is connected with the odd-row grid driving signal output end, and the second end of the first storage capacitor is connected with the pull-up node;

a second pull-up node input transistor having a gate connected to the even-numbered row input terminal, a first pole connected to the pull-up node, and a second pole connected to the first level output terminal; the method comprises the steps of,

and the first end of the second storage capacitor is connected with the pull-up node, and the second end of the second storage capacitor is connected with the even-numbered row grid driving signal output end.

In practice, the gate drive output subunit comprises:

the grid electrode of the first odd-row grid electrode driving output transistor is connected with the pull-up node, the first electrode of the first odd-row grid electrode driving output transistor is connected with the odd-row clock signal input end, and the second electrode of the first odd-row grid electrode driving output transistor is connected with the odd-row grid electrode driving signal output end;

A second odd-line gate drive output transistor, the gate of which is connected with the odd-line pull-down node, the first electrode of which is connected with the odd-line gate drive signal output end, and the second electrode of which is connected with the second level output end;

a third odd-line gate drive output transistor, wherein a gate is connected with the even-line pull-down node, a first pole is connected with the odd-line gate drive signal output end, and a second pole is connected with a second level output end;

the first even-numbered row grid electrode driving output transistor is characterized in that a grid electrode is connected with the pull-up node, a first electrode is connected with the even-numbered row grid electrode driving signal output end, and a second electrode is connected with the even-numbered row clock signal input end;

a second even-numbered row grid electrode driving output transistor, wherein a grid electrode is connected with the even-numbered row pull-down node, a first electrode is connected with the even-numbered row grid electrode driving signal output end, and a second electrode is connected with a second level output end; the method comprises the steps of,

and the grid electrode of the third even-numbered row grid electrode driving output transistor is connected with the odd-numbered row pull-down node, the first electrode is connected with the even-numbered row grid electrode driving signal output end, and the second electrode is connected with the second level output end.

The invention also provides a driving method of the shift register unit, which is applied to the shift register unit and comprises the following steps: in each of the display periods of the display device,

In the input stage, under the control of an odd line input signal, a pull-down control node and an even line pull-down control node are connected with a second level output end, a pull-up node input subunit control pull-up node is connected with a first level output end, when the odd line input signal is the first level pull-down node control subunit control the odd line pull-down node to be connected with the second level output end, and when the even line input signal is the first level pull-down node control subunit control the even line pull-down node to be connected with the second level output end; the grid driving output subunit controls the odd-numbered row grid driving signal output end and the even-numbered row grid driving signal output second level;

in the output stage, the pull-up node input subunit controls and maintains the potential of the pull-up node, the pull-down control node pull-down subunit continuously controls the odd row pull-down control node and the even row pull-down control node to be connected with the second level output end, and the grid drive output subunit controls the odd row grid drive signal output end to output a first clock signal and controls the even row grid drive signal output end to output a second clock signal;

In the reset stage, under the control of a reset signal, a reset subunit controls a pull-up node to be connected with a second level output end, a pull-down node control subunit controls an odd row pull-down node to be connected with an odd row voltage output end and controls an even row pull-down node to be connected with an even row voltage output end, so that the potential of the odd row pull-down node or the potential of the even row pull-down node is a first level, and a grid driving output subunit controls an odd row grid driving signal output end and an even row grid driving signal output end to both output a second level.

In implementation, the period T1 of the second clock signal output by the second clock signal input end is equal to the period T2 of the first clock signal output by the first clock signal input end;

the second clock signal is delayed by T1/2N from the first clock signal output by the first clock signal; n is a positive integer;

at the beginning of the output phase, the first clock signal is at a first level;

at the end of the output phase, the second clock signal transitions from a first level to a second level.

In practice, the input phase includes an odd line input period and an even line input period that are partially overlapped;

In the odd line input time period, an odd line input signal input by an odd line input end is a first level, and in the even line input time period, an even line input signal input by an even line input end is a first level; the even line input period is delayed by T1/2N from the odd line input period.

In implementation, the odd-numbered row voltage output end outputs a first square wave voltage, and the even-numbered row voltage output end outputs a second square wave voltage;

the period of the first square wave voltage and the period of the second square wave voltage are both voltage periods;

the voltage cycle includes a first voltage period and a second voltage period;

in the first voltage period, the odd row voltages are high and the even row voltages are low;

in the second voltage period, the odd row voltages are low and the even row voltages are high.

The invention also provides a grid driving circuit which comprises a plurality of cascaded register units.

the first clock signal input end of the KN+n-th shift register unit outputs a 2n-1 clock signal, and the second clock signal input end of the KN+n-th shift register unit outputs a 2n clock signal;

the period of the 2N-1 clock signal and the period of the 2N clock signal are equal to T1, and the 2N clock signal is delayed by T1/2N from the 2N-1 clock signal;

k is an integer greater than or equal to 0, and N is a positive integer less than or equal to N.

In practice, when the shift register cell further comprises an odd row carry out terminal, an even row carry out terminal and a carry out subunit,

the odd-numbered row carry output end of the shift register unit of the stage is connected with the odd-numbered row input end of the shift register unit of the next N stages;

the even number row carry output end of the shift register unit of the present stage is connected with the even number row input end of the shift register unit of the next N stages.

The invention also provides a display device comprising the gate driving circuit.

Compared with the prior art, the shift register unit, the driving method, the grid driving circuit and the display device adopt the common pull-up node of odd and even rows, reduce the number of transistors compared with the prior shift register unit which needs to adopt the pull-up nodes of odd rows and the pull-up nodes of even rows, save GOA layout space and facilitate the realization of a narrow frame.

Drawings

Fig. 1 is a block diagram of a shift register unit according to an embodiment of the present invention;

fig. 2 is a block diagram of a shift register unit according to another embodiment of the present invention;

fig. 3 is a block diagram of a shift register unit according to another embodiment of the present invention;

fig. 4 is a block diagram of a shift register unit according to still another embodiment of the present invention;

FIG. 5 is a circuit diagram of a shift register unit according to an embodiment of the present invention;

fig. 6 is a timing diagram illustrating the operation of the embodiment of the shift register unit shown in fig. 5 according to the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

As shown in fig. 1, the shift register unit according to the embodiment of the present invention is configured to drive two adjacent rows of pixels, and includes an odd row Input end input_o, an even row Input end input_e, an odd row gate driving signal OUTPUT end output_o, an even row gate driving signal OUTPUT end output_e, a RESET end RESET, a first clock signal Input end clk_o, and a second clock signal Input end clk_e, and further includes:

The pull-up node Input subunit 11 is respectively connected with a pull-up node PU, the odd-numbered line Input end input_o, the even-numbered line Input end input_e and the first level output end VO 1;

a RESET subunit 12, connected to the pull-up node PU, the RESET terminal RESET, and the second level output VO2, and configured to control, in a RESET stage, the pull-up node PU to be connected to the second level output VO2 under control of a RESET signal accessed by the RESET terminal RESET;

a pull-up node pull-down subunit 13, connected to the pull-up node PU, the odd-row pull-down node pd_e, the even-row pull-down node pd_o, and the second level output VO2, and configured to control the pull-up node to be connected to the second level output VO2 when the potential of the odd-row pull-down node pd_o and/or the potential of the even-row pull-down node pd_e is at a first level;

a pull-down control node pull-down subunit 14, respectively connected to the pull-up node PU, the odd-line pull-down control node pdcn_o, the even-line pull-down control node pdcn_e, and the second level output VO2, and configured to control, when the potential of the pull-up node PU is the first level, both the odd-line pull-down control node pdcn_o and the even-line pull-down control node pdcn_e to be connected to the second level output VO 2;

A pull-down node control subunit 15 connected to an odd row voltage output terminal vdd_o, an even row voltage output terminal vdd_e, the pull-up node PU, the odd row pull-down control node pdcn_o, the even row pull-down control node pdcn_e, the odd row Input terminal input_o, the even row Input terminal input_e, the odd row pull-down node pd_o, and the even row pull-down node pd_e, respectively; the method comprises the steps of,

the gate driving OUTPUT subunit 16 is connected to the odd row pull-down node pd_o, the even row pull-down node pd_e, the pull-up node PU, the odd row gate driving signal output_o, the even row gate driving signal output_e, the first clock signal input clk_o, and the second clock signal input clk_e, respectively.

In the embodiment shown in fig. 1, the first level output terminal VO1 may output a high level VGH and the second level output terminal VO2 may output a low level VSS.

Compared with the existing shift register unit which needs to adopt odd-numbered and even-numbered upward-pulling nodes PU_O and PU_E, the shift register unit provided by the embodiment of the invention adopts the odd-numbered and even-numbered upward-pulling nodes to share one upward-pulling node, reduces the number of transistors, saves GOA (Gate On Array) layout space, and is convenient for realizing a narrow frame.

In the shift register unit according to the embodiment of the present invention, the RESET subunit 12 controls the pull-up node PU to be connected to the second level output VO2 under the control of the RESET signal accessed by the RESET terminal RESET in the RESET stage, so that compared with the existing shift register unit that needs to use pu_o and pu_e, part of RESET transistors in the RESET subunit 12 are saved;

in the shift register unit according to the embodiment of the present invention, when the potential of the odd-row pull-down node pd_o and/or the potential of the even-row pull-down node pd_e are/is the first level, the pull-up node PU is controlled to be connected with the second level output terminal VO2 by the pull-up node pull-down subunit 13, so that part of pull-up node pull-down transistors in the pull-up node pull-down subunit 13 are saved;

in the shift register unit according to the embodiment of the present invention, the pull-down control node pull-down subunit 14 controls the odd-row pull-down control node pdcn_o and the even-row pull-down control node pdcn_e to be connected to the second level output terminal VO2 when the potential of the pull-up node PU is at the first level, so as to save a portion of pull-down control node pull-down transistors in the pull-down control node pull-down subunit 14.

Preferably, as shown in fig. 2, the shift register unit according to the embodiment of the present invention further includes: the start subunit 17 is connected to the start signal output terminal STV, the pull-up node PU, and the second level output terminal VO2, and is configured to control, in a start stage, the pull-up node PU to be connected to the second level output terminal VO2 under control of a start signal output by the start signal output terminal STV.

In actual operation, the second level output terminal VO2 may output the low level VSS.

The embodiment of the shift register unit shown in fig. 2 further comprises a start subunit 17 for controlling to pull the potential of the pull-up node PU low at the start stage of each display period, and since the pull-up node PU is shared by odd and even rows, part of the start transistors in the original start subunit are saved.

As shown in fig. 3, the shift register cell according to the embodiment of the present invention further includes an odd row carry output oc_o, an even row carry output oc_e, and a carry output subunit 18, wherein,

the carry-out subunit 18 is respectively connected to the odd-row carry-out end oc_o, the even-row carry-out end oc_e, the pull-up node PU, the odd-row pull-down node pd_o, the even-row pull-down node pd_e, the first clock signal input end clk_o, the second clock signal input end clk_e, and the second level output VO2, and is configured to control the odd-row carry-out end oc_o to be connected to the first clock signal input end clk_o and the even-row carry-out end oc_e to be connected to the second clock signal input end clk_e when the potential of the pull-up node PU is at the first level, and to control the odd-row carry-out end oc_o to be connected to the second level output end VO2 when the potential of the odd-row pull-down node pd_e is at the first level, and to control the even-row carry-out end oc_e to be connected to the second level VO2 when the potential of the even-row pull-down node pd_e is at the first level.

The embodiment of the shift register unit shown in fig. 3 further includes a carry output end, so as to avoid that the input signal and the reset signal are provided for other stages of shift register units by adopting the gate driving signal output end and can cause misoperation of the GOA circuit due to misoperation of the gate driving signal of the stage, and therefore the input signal and the reset signal are provided for other stages of shift register units by adopting the carry output end, and the carry signal output by the carry output end is equal to the predetermined gate driving signal of the stage, so that the probability of misoperation is reduced.

Specifically, the carry-out subunit may include:

Specifically, as shown in fig. 4, the reset subunit 12 may include: a RESET transistor MR having a gate connected to the RESET terminal RESET, a first electrode connected to the second level output terminal VO2, and a second electrode connected to the pull-up node PU;

the pull-up node pull-down subunit 13 includes:

a first pull-up node pull-down transistor M131 having a gate connected to the odd row pull-down node pd_o, a first pole connected to the second level output VO2, and a second pole connected to the pull-up node PU; the method comprises the steps of,

a second pull-up node pull-down transistor M132 having a gate connected to the even row pull-down node pd_e, a first electrode connected to the second level output VO2, and a second electrode connected to the pull-up node PU;

The pull-down control node pull-down subunit 14 includes:

a first pull-down control node pull-down transistor M141 having a gate connected to the pull-up node PU, a first pole connected to the second level output VO2, and a second pole connected to the odd row pull-down control node pdcn_o; the method comprises the steps of,

and a second pull-down control node pull-down transistor M142 having a gate connected to the pull-up node PU, a first pole connected to the second level output VO2, and a second pole connected to the even row pull-down control node pdcn_e.

In the embodiment shown in fig. 4, M131, M132, M141 and M142 are all n-type transistors, the second level output VO2 outputs the low level VSS, and in actual operation, M131, M132, M141 and M142 may be replaced by p-type transistors. When the first electrode is a source electrode, the second electrode is a drain electrode; when the first electrode is a drain electrode, the second electrode is a source electrode.

Specifically, the pull-down node control subunit may include:

The odd-line pull-down node control module is respectively connected with the pull-up node, the odd-line voltage output end, the odd-line pull-down control node, the odd-line pull-down node and the second level output end and is used for controlling the odd-line pull-down node to be connected with the odd-line voltage output end when the potential of the odd-line pull-down control node is a first level and controlling the odd-line pull-down node to be connected with the second level output end when the potential of the pull-up node is the first level;

And the even-numbered row pull-down node control module is respectively connected with the pull-up node, the even-numbered row voltage output end, the even-numbered row pull-down control node, the even-numbered row pull-down node and the second level output end and is used for controlling the even-numbered row pull-down node to be connected with the even-numbered row voltage output end when the potential of the even-numbered row pull-down control node is a first level and controlling the even-numbered row pull-down node PD_E to be connected with the second level output end when the potential of the pull-up node is the first level.

In the above embodiment, the first level may be a high level, and the second level output terminal may output the low level VSS.

Specifically, the odd row drop-down control node control module may include: the odd-row pull-down control node controls a transistor, a grid electrode and a first electrode are connected with the odd-row voltage output end, and a second electrode is connected with the odd-row pull-down control node;

the odd row drop down node control module may include:

the first odd-line pull-down node control transistor is characterized in that a grid electrode of the first odd-line pull-down node control transistor is connected with the odd-line pull-down control node, a first electrode of the first odd-line pull-down node control transistor is connected with the odd-line voltage output end, and a second electrode of the first odd-line pull-down node control transistor is connected with the odd-line pull-down node; the method comprises the steps of,

A second odd-line pull-down node control transistor, wherein a grid electrode is connected with the pull-up node, a first electrode is connected with the odd-line pull-down node, and a second electrode is connected with the second level output end;

the pull-down node input module comprises:

Specifically, the pull-up node input subunit includes:

Specifically, the gate driving output subunit may include:

The shift register unit according to the present invention is described below by way of a specific embodiment.

As shown in fig. 5, a specific embodiment of the shift register unit according to the present invention includes an odd-numbered row Input terminal input_o, an even-numbered row Input terminal input_e, an odd-numbered row gate driving signal output_o, an even-numbered row gate driving signal output_e, a RESET terminal RESET, a first clock signal Input terminal clk_o, a second clock signal Input terminal clk_e, an odd-numbered row carry OUTPUT terminal oc_o, and an even-numbered row carry OUTPUT terminal oc_e, the shift register unit further includes a pull-up node Input subunit, a RESET subunit, a pull-up node pull-down subunit, a pull-down control node pull-down subunit, a pull-down node control subunit, a gate driving OUTPUT subunit, a start subunit, and a carry OUTPUT subunit,

the pull-up node input subunit includes:

the first pull-up node Input transistor M111 has a gate connected with the odd-numbered row Input end input_O, a source connected with the pull-up node PU, and a drain connected with a high-level output end for outputting a high-level VGH;

the first storage capacitor C1 has a first end connected to the odd-numbered row gate driving signal output_o and a second end connected to the pull-up node PU;

a second pull-up node Input transistor M112 having a gate connected to the even-numbered row Input terminal input_e, a source connected to the pull-up node PU, and a drain connected to a high-level output terminal outputting a high-level VGH; the method comprises the steps of,

The first end of the second storage capacitor C2 is connected with the pull-up node PU, and the second end of the second storage capacitor C2 is connected with the even-numbered row grid driving signal OUTPUT end OUTPUT_E;

the reset subunit includes: the RESET transistor MR, the grid connects with RESET end RESET, the source connects with low level output end outputting low level VSS, the drain connects with pull-up node PU;

the pull-up node pull-down subunit includes:

the first pull-up node pull-down transistor M131 has a gate connected to the odd row pull-down node PD_O, a source connected to a low level output terminal outputting a low level VSS, and a drain connected to the pull-up node PU; the method comprises the steps of,

a second pull-up node pull-down transistor M132 having a gate connected to the even row pull-down node pd_e, a source connected to a low level output terminal outputting a low level VSS, and a drain connected to the pull-up node PU;

the pull-down control node pull-down subunit includes:

a first pull-down control node pull-down transistor M141 having a gate connected to the pull-up node PU, a source connected to a low-level output terminal outputting a low-level VSS, and a drain connected to the odd-numbered row pull-down control node pdcn_o; the method comprises the steps of,

a second pull-down control node pull-down transistor M142 having a gate connected to the pull-up node PU, a source connected to a low-level output terminal outputting a low-level VSS, and a drain connected to the even-numbered row pull-down control node pdcn_e;

The pull-down node control subunit comprises an odd-row pull-down control node control module, an odd-row pull-down node control module, a pull-down node input module, an even-row pull-down control node control module and an even-row pull-down node control module;

the odd-line pull-down control node control module comprises: an odd row pull-down control node control transistor M1510 having a gate and a source both connected to the odd row voltage output terminal vdd_o and a drain connected to the odd row pull-down control node pdcn_o;

the odd-line pull-down node control module comprises:

a first odd-row pull-down node control transistor M1521 having a gate connected to the odd-row pull-down control node pdcn_o, a source connected to the odd-row voltage output terminal vdd_e, and a drain connected to the odd-row pull-down node pd_o; the method comprises the steps of,

a second odd-numbered row pull-down node control transistor M1522 having a gate connected to the pull-up node PU, a source connected to the odd-numbered row pull-down node pd_o, and a drain connected to a low-level output terminal for outputting a low-level VSS;

the pull-down node input module comprises:

an odd-row pull-down node Input transistor M1531 having a gate connected to the odd-row Input terminal input_o, a source connected to the odd-row pull-down node pd_o, and a drain connected to a low-level output terminal for outputting a low-level VSS; the method comprises the steps of,

An even-numbered row pull-down node Input transistor M1532, wherein the gate is connected with the even-numbered row Input end input_E, the source is connected with the even-numbered row pull-down node PD_E, and the drain is connected with a low-level output end for outputting a low-level VSS;

the even row pulldown control node control module 154 includes: an odd row pull-down control node control transistor M1540, wherein the grid electrode and the source electrode are connected with the even row voltage output end VDD_E, and the drain electrode is connected with the even row pull-down control node PDCN_E;

the even row drop down node control module 155 includes: a first even-numbered row pull-down node control transistor M1551 having a gate connected to the even-numbered row pull-down control node pdcn_e, a source connected to the even-numbered row voltage output terminal vdd_e, and a drain connected to the even-numbered row pull-down node pd_e; the method comprises the steps of,

a second even-numbered row pull-down node control transistor M1552 having a gate connected to the pull-up node PU, a source connected to the even-numbered row pull-down node pe_e, and a drain connected to a low-level output terminal outputting a low-level VSS;

the gate drive output subunit includes:

a first odd-numbered row gate driving OUTPUT transistor M1611 having a gate connected to the pull-up node PU, a source connected to the odd-numbered row clock signal input terminal clk_o, and a drain connected to the odd-numbered row gate driving signal OUTPUT terminal output_o;

A second odd-numbered row gate driving OUTPUT transistor M1612, the gate is connected to the odd-numbered row pull-down node pd_o, the source is connected to the odd-numbered row gate driving signal output_o, and the drain is connected to the low-level OUTPUT terminal that OUTPUTs the low-level VSS;

a third odd-numbered row gate driving OUTPUT transistor M1613, the gate is connected to the even-numbered row pull-down node pd_e, the source is connected to the odd-numbered row gate driving signal output_o, and the drain is connected to the low-level OUTPUT terminal that OUTPUTs the low-level VSS;

a first even-numbered row gate driving OUTPUT transistor M1621 having a gate connected to the pull-up node PU, a source connected to the even-numbered row gate driving signal output_e, and a drain connected to the even-numbered row clock signal input clk_e;

a second even-numbered row gate driving OUTPUT transistor M1622, having a gate connected to the even-numbered row pull-down node pd_e, a source connected to the even-numbered row gate driving signal output_e, and a drain connected to a low-level OUTPUT terminal outputting a low-level VSS; the method comprises the steps of,

a third even-numbered row gate driving OUTPUT transistor M1623, having a gate connected to the odd-numbered row pull-down node pd_o, a source connected to the even-numbered row gate driving signal output_e, and a drain connected to a low-level OUTPUT terminal outputting a low-level VSS;

The starter subunit includes:

the initial transistor M170, the grid is connected with the initial signal output end STV, the source is connected with the pull-up node PU, and the drain is connected with the low level output end outputting the low level VSS;

the carry-out subunit includes:

a first odd row carry output transistor M1811 having a gate connected to the pull-up node PU, a drain connected to the first clock signal input clk_o, and a source connected to the odd row carry output oc_o;

a second odd row carry output transistor M1812 having a gate connected to the odd row pull-down node pd_o, a drain connected to the odd row carry output terminal oc_o, and a source connected to a low level output terminal for outputting a low level VSS;

a third odd column carry output transistor M1813 having a gate connected to the even column pull-down node pd_e, a source connected to the odd column carry output terminal oc_o, and a drain connected to a low level output terminal for outputting a low level VSS;

the gate of the first even-numbered row carry output transistor M1821 is connected to the pull-up node PU, the source is connected to the second clock signal input terminal clk_e, and the drain is connected to the even-numbered row carry output terminal oc_e;

a second even-numbered row carry output transistor M1822 having a gate connected to the odd-numbered row pull-down node pd_o, a source connected to the even-numbered row carry output terminal oc_e, and a drain connected to a low-level output terminal for outputting a low-level VSS; the method comprises the steps of,

And a third even row carry output transistor M1823, having a gate connected to the even row pull-down node pd_e, a source connected to the even row carry output terminal oc_e, and a drain connected to a low level output terminal outputting the low level VSS.

In the embodiment shown in fig. 5, all the transistors are n-type transistors, and in actual operation, the transistors in fig. 5 may be replaced by p-type transistors, and the types of the transistors are not limited herein.

In the embodiment shown in fig. 5, VSS is low, VGH is high (VGH may be adjusted according to specific process conditions and actual load, for example, may be between 27-33V), odd row voltages output by VDD-O and even row voltages output by VDD-E are mutually inverted, that is, when vdd_o outputs high, vdd_e outputs low VGL, and when vdd_o outputs low VGL, vdd_e outputs high (low VGL is a voltage corresponding to the lowest current value in the transistor electrical characteristic curve, which is related to the process conditions, for example, may be-8V), so that the transistors controlled by the same may be alternately resting, thereby improving circuit performance.

As shown in fig. 6, the period of the second clock signal output by clk_e is equal to the period T of the first clock signal output by clk_o;

The second clock signal is delayed by T/2N, N is equal to 4 from the first clock signal output by the first clock signal, and N can be replaced by other positive integers in actual operation;

as shown in fig. 6, at the start of the output phase TO, the first clock signal output by clk_o is high;

at the end of the output phase TO, clk_e outputs a second clock signal that transitions from high TO low;

as shown in FIG. 6, the even row INPUT signal output by INPUT-E is delayed by T/8 from the odd row INPUT signal output by INPUT-O; the even row gate drive signal OUTPUT by OUTPU_E is delayed by T/8 from the odd row gate drive signal OUTPUT by OUTPUT_O.

Compared with the prior art shift register unit which needs 34 transistors and 2 capacitors, the shift register unit shown in fig. 5 reduces 6 transistors by connecting two pull-up nodes in the prior art, effectively saves GOA layout space and is beneficial to realizing a narrow frame.

As shown in FIG. 6, input_ O, input _E charges the PU through M111, M112, respectively, the even row Input signal output by INPUT-E is delayed by T/8 from the odd row Input signal output by INPUT-O, as the PU is pulled high. M1621 and M1622 are simultaneously turned on, output_ O, OUTPUT _e OUTPUTs the first and second clock signals, respectively, which are both low during the input phase. Before RESET OUTPUTs high level, the odd-numbered row gate driving signal output_o coincides with the first clock signal OUTPUT by clk_o, and the even-numbered row gate driving signal OUTPUT output_e coincides with the second clock signal OUTPUT by clk_e. When RESET OUTPUTs high level, the potential of PU is pulled down by MR, M1611 and M1622 are turned off simultaneously, at this time, the first clock signal and the second clock signal are both low level, and the odd-numbered row gate driving signal OUTPUT from output_o and the even-numbered row gate driving signal OUTPUT from output_e are both kept low level accordingly. As is apparent from the timing chart shown in fig. 6, only the high level of one square wave is output for each of clk_o and clk_e during the period in which the potential of PU is high. The first clock signal OUTPUT by clk_o and the second clock signal OUTPUT by clk_e are periodic square wave signals differing by T/8, i.e., the odd-numbered row gate drive signals OUTPUT by output_o and the even-numbered row gate drive signals OUTPUT by output_e are pulse signals differing by T/8.

The driving method of the shift register unit according to the embodiment of the invention is applied to the shift register unit, and comprises the following steps: in each of the display periods of the display device,

Preferably, the period T1 of the second clock signal output by the second clock signal input terminal is equal to the period T2 of the first clock signal output by the first clock signal input terminal;

In a specific implementation, the input stage includes an odd line input period and an even line input period that are partially overlapped;

Preferably, the odd-numbered row voltage output terminal outputs a first square wave voltage, and the even-numbered row voltage output terminal outputs a second square wave voltage;

the voltage cycle includes a first voltage period and a second voltage period;

in the second voltage period, the odd row voltages are low and the even row voltages are high. Preferably, the odd row voltages and the even row voltages are mutually inverted, i.e. when the odd row voltages are high, the even row voltages are low; when the odd line voltage is at low level, the even line voltage is at high level, so that the transistors controlled by the even line voltage can be alternately stopped, and the circuit performance is improved.

The gate driving circuit according to the embodiment of the invention comprises a plurality of cascaded register units.

In a preferred case, the clock signals accessed by the shift register units of each stage are sequentially delayed by a group of 2N.

In actual operation, when the shift register cell further comprises an odd row carry out terminal, an even row carry out terminal and a carry out subunit,

The display device according to the embodiment of the invention comprises the gate driving circuit.

While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.

Claims

1. A shift register unit for driving two adjacent rows of pixels, comprising an odd row input terminal, an even row input terminal, an odd row gate drive signal output terminal, an even row gate drive signal output terminal, a reset terminal, a first clock signal input terminal, and a second clock signal input terminal, the shift register unit further comprising:

2. The shift register cell of claim 1, further comprising: the starting subunit is respectively connected with the starting signal output end, the pull-up node and the second level output end and is used for controlling the pull-up node to be connected with the second level output end under the control of the starting signal output by the starting signal output end in a starting stage.

3. The shift register cell as claimed in claim 1, further comprising an odd row carry out, an even row carry out and a carry out subunit, wherein,

4. A shift register cell as claimed in claim 3, in which the carry-out subunit comprises:

5. The shift register cell as claimed in claim 1, wherein the reset subunit comprises: a reset transistor, the grid electrode of which is connected with the reset end, the first electrode of which is connected with the second level output end, and the second electrode of which is connected with the pull-up node;

the pull-up node pull-down subunit includes:

the pull-down control node pull-down subunit includes:

6. The shift register unit as claimed in any one of claims 1 to 5, wherein the pull-down node control subunit comprises:

7. The shift register cell of claim 6, wherein the odd row pulldown control node control module comprises: the odd-row pull-down control node controls a transistor, a grid electrode and a first electrode are connected with the odd-row voltage output end, and a second electrode is connected with the odd-row pull-down control node;

the pull-down node input module comprises:

8. The shift register cell as claimed in any one of claims 1 to 5, wherein the pull-up node input sub-unit is configured to control the pull-up node to be connected to the first level output terminal when the odd line input signal inputted from the odd line input terminal is at the first level, and to control the pull-up node to be connected to the first level output terminal when the even line input signal inputted from the even line input terminal is at the first level.

9. The shift register cell as claimed in claim 8, wherein the pull-up node input subunit comprises:

10. A shift register cell as claimed in any one of claims 1 to 5, in which the gate drive output sub-unit comprises:

the first odd-row grid drive output transistor is characterized in that a grid electrode is connected with the pull-up node, a first electrode is connected with an odd-row clock signal input end, and a second electrode is connected with an odd-row grid drive signal output end;

11. A driving method of a shift register unit, applied to a shift register unit according to any one of claims 1 to 10, characterized by comprising: in each of the display periods of the display device,

12. The driving method of a shift register unit as claimed in claim 11, wherein a period T1 of the second clock signal output from the second clock signal input terminal is equal to a period T2 of the first clock signal output from the first clock signal input terminal;

13. The driving method of a shift register unit as claimed in claim 12, wherein the input stage includes an odd line input period and an even line input period which are partially overlapped;

14. A method of driving a shift register unit as claimed in any one of claims 11 to 13, wherein the odd-numbered row voltage output terminals output a first square wave voltage, and the even-numbered row voltage output terminals output a second square wave voltage;

The voltage cycle includes a first voltage period and a second voltage period;

15. A gate drive circuit comprising a plurality of cascaded register cells as claimed in any one of claims 1 to 10.

16. The gate driving circuit according to claim 15, wherein a period T1 of the second clock signal output from the second clock signal input terminal is equal to a period T2 of the first clock signal output from the first clock signal input terminal;

17. The gate driving circuit of claim 16, wherein when the shift register cell further comprises an odd row carry out terminal, an even row carry out terminal, and a carry out subunit,

18. A display device comprising the gate drive circuit according to any one of claims 15 to 17.