KR20000037549A - Circuit for managing error spread of plasma display panel - Google Patents

Abstract

PURPOSE: A circuit for managing error spread of plasma display panel is provided to simplify a circuit and make high speed calculation possible and reduce cost by making only one adding circuit be used by restricting difference of bit between original pixel image signal and output image signal to 1 bit and to prevent bit overflow which can occur when input image signal is peak level of realizable range by installing overflow predicting circuit additionally. CONSTITUTION: A circuit for managing error spread of plasma display panel includes an LSB(least significant bit) detecting circuit(102) which detects LSB if n bits image signal of original pixel inputted to image input terminal(101) is outputted in error spread through an adding circuit(107); a higher line LSB delaying circuit(103) which adds LSB value, which occurs at 1 line past than the original pixel, to the detected LSB value; a left dot LSB delaying circuit(104) which adds LSB value, which occurs at one dot past than the original pixel, to the detected LSB value; an OR gate(105) which outputs error signal due to past LSB value by OR-operating output signals of the higher line LSB delaying circuit(103) and the left dot LSB delaying circuit(104); an adding circuit(107) which adds error signal of the OR gate(105) to the original pixel and spreads it; and an LSB removing circuit(108) which removes LSB value from the error spread output signal of the adding circuit(107) and transforms it to m(=n-1) bits and outputs it to image output terminal(109).

Description

Error Diffusion Processing Circuit of Plasma Display Panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error diffusion processing circuit of a plasma display panel (hereinafter referred to as " PDP "), in particular converting an n-bit original pixel video signal into an m (= n-1) bit output video signal and The present invention relates to an error diffusion processing circuit of a PDP that compensates for image quality deterioration by distributing an error amount between a signal and an output video signal to adjacent pixels that have not been processed yet to perform pseudo halftone display.

As is well known, the PDP obtains a discharge by adjusting a voltage applied between vertical and horizontal electrodes of a cell constituting a pixel, and the amount of light discharged is adjusted by changing the length of the discharge time in the cell.

The full screen includes a write pulse for inputting a digital image signal to the vertical and horizontal electrodes of each cell, a scan pulse for scanning, a sustain pulse for maintaining the discharge, and a stop for discharging the discharged cell. It is obtained by driving a matrix type by applying an escape pulse.

In addition, the gray level required for displaying an image is realized by varying the length of time that individual cells are discharged within a given time required to display the entire image.

At this time, the brightness of the screen is determined by the brightness when each cell is driven to the maximum, and in order to increase the brightness, the discharge time of the cell must be kept as long as possible within a given time for configuring a screen.

In addition, the contrast, which is a difference in contrast, is determined by the brightness and the brightness of the background. In order to increase the contrast, it is necessary to not only darken the background but also increase the brightness.

For example, an image digital signal required for displaying an image of 256 gray levels requires an 8-bit signal for each of RGB, and a cell discharge time should be kept as long as possible in order to obtain required luminance and contrast.

On the other hand, the sub-field scanning method which is currently attracting the most attention as a gray scale implementation method of the AC PDP is that the 8-bit digital video signal has the same weight bit between the MSB (highest bit) to LSB (lowest bit). After collecting, the MSB scans for the time T and the lower bits in order of bit closest to the MSB for T / 2, T / 4, ..., T / 128, respectively, to form a sub picture, and is emitted from each sub picture. By using the integrated effect of the eye on light, 256 gray levels are realized.

However, since the PDP must be driven in a matrix manner, there is a limitation in that a write pulse cannot be applied to one or more scan electrodes at a time for a given address electrode, and thus the scan electrodes must be driven at different times.

Therefore, in order to construct each subscreen, a time (address period) for scanning all scan electrodes is required, and each cell discharges only during a time (sustain period) reduced by the scanning time from the time allocated to the average subscreen. It can be maintained. The address period increases as the number of scan electrodes increases. During this time, since the discharge cannot be maintained, the sustain period decreases, which causes a decrease in luminance and contrast of the PDP. Therefore, the address period needs to be reduced as much as possible. have.

Accordingly, in recent years, even when an original pixel video signal quantized with n bits is input, a driving method of converting an output video signal into m (≤ n-1) bits and displaying only m bits in the PDP without displaying all bits is used.

However, such a bit conversion driving method has a disadvantage in that the image quality is degraded because the luminance is increased by reducing the number of bits of the handling signal but the gray scale display is reduced.

To compensate for this drawback, Japanese Patent Application Laid-Open No. 7-64501 distributes an error amount between an original pixel image signal and an output image signal to adjacent pixels that have not yet been processed to compensate for image degradation by performing pseudo halftone display. One error diffusion processing circuit has been proposed.

Hereinafter, the operation and effect of the error diffusion processing circuit proposed in Japanese Patent Laid-Open No. 7-64501 will be described with reference to FIGS. 1, 2, and 4.

When the pixel of the j-th column of the i-th line (row) of the PDP is called the original pixel Ai, j, Ai, j-h is a pixel higher than the original pixel by h line, and Ai, j-d is a pixel on the left side of the d column than the original pixel.

First, an n-bit video signal of the original pixels Ai and j is input to the video input terminal 1, and the error detection circuit 2 detects error amounts Kd and Kh for a predetermined weight.

Then, the h line delay circuit 3 outputs the reproduction error Ej-h generated in the h line past than the original pixel Ai, j to the error amount Kh and outputs the output signal in the vertical addition circuit 4. It adds to the pixel Ai, j.

Then, the d dot delay circuit 5 outputs the reproduction error Ei-d generated in the past d dots from the original pixels Ai, j to the error amount Kd, and outputs the output signal by the horizontal addition circuit 6 to the original. The pixel is added to Ai, j.

Next, the n-bit quantized spread output signal spread by adding the error in the h line delay circuit 3 and the d dot delay circuit 5 is converted into m (≤ n-1) bits in the bit conversion circuit 7. And output to the video output terminal 8.

Therefore, even if the error is weighted and diffused to the video signal inputted to the video input terminal 1, and the gray scale is implemented with fewer bits than the original video signal, the pseudo halftone display is performed by the error diffusion to compensate for the deterioration in image quality.

However, in the conventional error diffusion processing circuit, the bit difference between the n-bit original pixel video signal input to the video input terminal 1 and the m-bit output video signal output to the video output terminal 8 is 2 bits or more. In this case, even when halftone display is performed through error diffusion, the image is displayed unnaturally, and there is a problem in that the image quality is reduced due to less grayscale display.

In addition, as shown in FIG. 1, the use of two addition circuits, namely, a vertical addition circuit 4 and a horizontal addition circuit 6, not only is a complicated circuit, but also has a low computational speed and a high cost. there was.

Also, even when the bit difference between the n-bit original pixel video signal input to the video input terminal 1 and the m-bit output video signal output to the video output terminal 8 is 1 bit, the original pixel video signal is realized. In the case where the peak value of the gray level is possible, bit overflow occurs when the error amount of adjacent pixels is increased and diffused.

For example, in a PDP implementing 256 gray scales (0 to 255), as shown in FIG. When the reproduction error occurred in the d dot past is implemented at the level 254, when the error amount of the video signal Ai, j is weighted to the adjacent video signals Ai, j + h and Ai + d, j as shown in FIG. This is because 256 levels that cannot be implemented are calculated.

Therefore, the present invention has been proposed to solve the above-described problems of the prior art, and the circuit can be simplified by using only one addition circuit by limiting the bit difference between the original pixel video signal and the output video signal to 1 bit. The purpose of the present invention is to enable high-speed calculation, to reduce cost, and to provide an overflow prediction circuit to prevent bit overflow that may occur when an input video signal is at a peak value of gray level that can be implemented.

The technical means of the present invention for achieving the object is an LSB detection circuit for detecting the least significant bit (LSB) when the n-bit video signal of the original pixel input to the video input terminal is diffused output through the subsequent addition circuit, and An upper line LSB delay circuit that weights the LSB value generated one line past the pixel to the LSB value detected by the LSB detection circuit, and weights the LSB value generated one dot past the original pixel to the LSB value detected by the LSB detection circuit. An OR gate for outputting an error signal based on a past LSB value by performing an OR operation on an output signal of a left dot LSB delay circuit, an upper line LSB delay circuit and a left dot LSB delay circuit, and an original pixel represented by n bits An overflow estimation circuit that blocks the error signal of the or gate by anticipating the bit overflow at the peak value, and an error signal of the or gate that has passed through the overflow prediction circuit. And an LSB elimination circuit that adds and diffuses the original pixel, and removes the LSB value from the error diffusion output signal of the addition circuit, converts it into m (= n-1) bits, and outputs it to an image output terminal. .

1 is a block diagram of an error diffusion processing circuit of a conventional plasma display panel.

2 is an explanatory diagram of coordinate positions of pixels.

3 is a block diagram of an error diffusion processing circuit of the plasma display panel according to the present invention;

4 is an error diffusion processing state diagram according to the prior art and the present invention.

*** Explanation of symbols for the main parts of the drawing ***

101: video input terminal 102: LSB detection circuit

103: upper line LSB delay circuit 104: left dot LSB delay circuit

105: OR gate 106: overflow prediction circuit

107: addition circuit 108: LSB removal circuit

109: video output terminal

Hereinafter, the present invention will be described with reference to the accompanying drawings.

3 is a block diagram of an error diffusion processing circuit according to an embodiment of the present invention, in which an image input terminal 101 into which an n-bit image signal of an original pixel is input is inputted through an addition circuit 107 to the least significant bit ( The upper pixel LSB delay circuit 103 and the original pixel, which are connected to the LSB detection circuit 102 for detecting the LSB, and whose two output terminals of the LSB detection circuit 102 weight LSB values generated in the past one line than the original pixel. The left dot LSB delay circuit 104, which weights the LSB value generated in the past one dot, is connected to two input terminals of the OR gate 105, respectively. In addition, an output terminal of the OR gate 105 is connected to an overflow predicting circuit 106 that blocks an error signal of the OR gate 105 in anticipation of a bit overflow when the original pixel is at a peak value represented by n bits. The overflow prediction circuit 106 is connected to an adder circuit 107 which adds and diffuses the error signal of the OR gate 105 to the original pixel, which adds the LSB value from the error diffusion output signal. It is connected to the LSB removal circuit 108 which removes the signal, converts it into m (= n-1) bits, and outputs it to the image output terminal 109.

The operation and effect of the present invention configured as described above will be described with reference to FIGS. 2 to 4 as follows.

First, when the n-bit video signal of the original pixel Ai, j is input to the video input terminal 101 and error-produced through the addition circuit 107, the LSB detection circuit 102 detects the LSB for a predetermined weight.

Then, the upper line delay circuit 103 weights the LSB value generated one line past the original pixel Ai, j to the OR gate 105 by weighting the LSB detected by the LSB detection circuit 102, and outputs a left dot delay. The circuit 104 weights the LSB value generated one dot past the original pixel Ai, j to the LSB detected by the LSB detection circuit 102 and outputs it to the OR gate 105.

Next, the OR gate 105 performs an OR operation on the output signals of the upper line delay circuit 103 and the left dot LSB delay circuit 104 and outputs an error signal based on a past LSB value to the overflow prediction circuit 106. do.

In this case, the overflow prediction circuit 106 predicts a bit overflow when the original pixel input from the image input terminal 101 to the addition circuit 107 is a peak value represented by n bits, and the error signal of the OR gate 105 is estimated. Block it.

For example, in a PDP that implements 256 gradations (0 to 255), as shown in FIG. 4A, when all four adjacent pixel video signals have 255 levels, LSB values generated in the past of one line in the video signal Ai, j and When the LSB value generated in the past of one dot is weighted and implemented at 254 levels, as shown in FIG. 4 (C), the overflow prediction circuit 106 causes the video signal Ai to be adjacent to the adjacent video signals Ai, j + h and Ai + d, j. Do not weight the LSB of, j.

That is, if the original pixel video signals Ai, j + h and Ai + d, j are " 255 ", and the error signal output from the OR gate 105 is " 1, " Since 256 "is calculated, the overflow prediction circuit 106 prevents bit overflow by making the error signal output from the OR gate 105 as" 0 "when the original pixel image signal is" 255 ".

On the other hand, the addition circuit 107 adds and spreads the error signal of the OR gate 105 that has passed through the overflow predicting circuit 106 to the original pixel, and LSB elimination circuit from the error diffusion output signal of the addition circuit 107. 108 removes the LSB value, converts it into m (= n-1) bits, and outputs it to the image output terminal 109.

Therefore, even if the error is weighted and diffused to the input n-bit video signal, and the gray scale is implemented with m (= n-1) bits smaller than the original video signal, pseudo image halftone display is performed by the error diffusion to compensate for the deterioration in image quality.

As described above, according to the present invention, the bit difference between the original pixel image signal and the output image signal is limited to 1 bit so that only one addition circuit is used, thereby simplifying the circuit, enabling high-speed calculation, and reducing the cost. In addition, an overflow prediction circuit may be additionally installed to prevent bit overflow that may occur when the input image signal is at a peak value of gray level that can be implemented.

Claims (2)

LSB detection circuit 102 for detecting the least significant bit (LSB) when the n-bit video signal of the original pixel inputted to the video input terminal 101 is error-diffused and output through the subsequent addition circuit 107; An upper line LSB delay circuit 103 for weighting the LSB value generated one line past the original pixel to the LSB value detected by the LSB detection circuit 102; A left dot LSB delay circuit 104 for weighting the LSB value generated one dot earlier than the original pixel to the LSB value detected by the LSB detection circuit 102; An OR gate 105 for performing an OR operation on the output signals of the upper line LSB delay circuit 103 and the left dot LSB delay circuit 104 to output an error signal based on a past LSB value; An addition circuit 107 that adds and diffuses an error signal of the or gate 105 to the original pixel; LSB removal circuit 108 for removing the LSB value from the error diffusion output signal of the addition circuit 107, converting it to m (= n-1) bits, and outputting it to the image output terminal 109. Error diffusion processing circuit of a plasma display panel. The method of claim 1, And an overflow predicting circuit 106 for blocking an error signal of the OR gate 105 in anticipation of a bit overflow when the original pixel is at a peak value represented by n bits. Diffusion processing circuit.