KR20000031794A - Method for producing semiconductor device - Google Patents
Method for producing semiconductor device Download PDFInfo
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- KR20000031794A KR20000031794A KR1019980048020A KR19980048020A KR20000031794A KR 20000031794 A KR20000031794 A KR 20000031794A KR 1019980048020 A KR1019980048020 A KR 1019980048020A KR 19980048020 A KR19980048020 A KR 19980048020A KR 20000031794 A KR20000031794 A KR 20000031794A
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- field oxide
- oxide film
- gate electrode
- storage electrode
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title abstract description 20
- 238000003860 storage Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000005684 electric field Effects 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 238000005468 ion implantation Methods 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 239000012535 impurity Substances 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 5
- 238000009826 distribution Methods 0.000 abstract description 2
- 239000002019 doping agent Substances 0.000 abstract 4
- 238000002955 isolation Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
본 발명은 반도체소자에 관한 것으로 특히, 디램(DRAM)의 리프래쉬(refresh) 특성을 향상시키는데 적당한 반도체 소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for improving a refresh characteristic of a DRAM.
이하, 첨부된 도면을 참조하여 종래 기술에 따른 반도체소자 제조방법을 설명하기로 한다.Hereinafter, a semiconductor device manufacturing method according to the related art will be described with reference to the accompanying drawings.
도 1은 종래 반도체 소자 제조방법에 따른 레이아웃도이고, 도 2a 내지 2c는 종래 기술에 따른 반도체 소자 제조방법을 설명하기 위한 공정단면도이다.1 is a layout diagram according to a conventional semiconductor device manufacturing method, Figures 2a to 2c is a process cross-sectional view for explaining a semiconductor device manufacturing method according to the prior art.
도 1의 A는 액티브 영역이고, B는 게이트 전극, 그리고 C는 스토리지 전극을 형성하기 위한 노드콘택영역을 나타낸다.A of FIG. 1 is an active region, B is a gate electrode, and C is a node contact region for forming a storage electrode.
도 1의 Ⅰ-Ⅰ'선에 따라 종래 기술에 따른 반도체 소자 제조방법을 설명하면 다음과 같다.A semiconductor device manufacturing method according to the prior art according to line II ′ of FIG. 1 is as follows.
도 2a 내지 2b는 종래 기술에 따른 반도체 소자 제조방법을 설명하기 위한 공정단면도이다.2A through 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art.
도 2a에 도시한 바와 같이, 필드영역과 활성영역으로 정의된 반도체 기판(21)의 필드영역에 채널 스톱 이온주입(22)을 실시한 후, 필드 산화막(23)을 형성한다.As shown in FIG. 2A, after the channel stop ion implantation 22 is performed in the field region of the semiconductor substrate 21 defined as the field region and the active region, the field oxide film 23 is formed.
활성영역의 반도체 기판(21)상에 게이트 절연막(도시되지 않음)과 게이트용 폴리실리콘층을 형성한 후, 선택적으로 제거하여 게이트 전극(도시되지 않음)을 형성한다.A gate insulating film (not shown) and a gate polysilicon layer are formed on the semiconductor substrate 21 in the active region, and then selectively removed to form a gate electrode (not shown).
게이트 전극을 마스크로 이용한 저농도의 불순물 이온주입으로 LDD영역(도시되지 않음)을 형성한 후, 상기 게이트 전극 양측면에 측벽(도시되지 않음)을 형성한다.After the LDD region (not shown) is formed by implanting impurity ions at low concentration using the gate electrode as a mask, sidewalls (not shown) are formed on both sides of the gate electrode.
상기 측벽은 게이트 전극을 포함한 기판(21) 전면에 절연물질을 증착한 후, 에치백하는 공정에 의해 형성된다.The sidewall is formed by depositing an insulating material on the entire surface of the substrate 21 including the gate electrode and then etching back.
상기 측벽 및 게이트 전극을 마스크로 이용한 고농도의 불순물 이온주입으로 상기 게이트 전극 양측의 기판내에 소오스/드레인 불순물 영역(24)을 형성한다.Source / drain impurity regions 24 are formed in the substrates on both sides of the gate electrodes by the implantation of high concentration impurity ions using the sidewalls and the gate electrodes as masks.
이후, 도 1b에 도시한 바와 같이, 상기 게이트 전극을 포함한 기판(21)상에 절연막(25)을 증착한 후, 상기 소오스 또는 드레인 불순물 영역(24)이 노출되도록 상기 절연막을 선택적으로 제거하여 노드 콘택(26)을 형성한다.Thereafter, as illustrated in FIG. 1B, an insulating film 25 is deposited on the substrate 21 including the gate electrode, and then the insulating film is selectively removed so that the source or drain impurity region 24 is exposed. Contact 26 is formed.
이때, 도 1b에 도시된 바와 같이, 노드 콘택(26)이 필드 산화막(23)에 국부적으로 형성되는 것을 피할 수 없는 제품에 대해서는 노드 콘택 형성 후, 스토리지 전극(도시하지 않음)을 형성함에 따라 N+층의 스토리지 전극과 P+층인 필드 산화막(23)이 접하게 되는 현상이 발생한다.In this case, as shown in FIG. 1B, for a product in which the node contact 26 cannot be locally formed in the field oxide layer 23, the storage electrode (not shown) is formed after forming the node contact. the storage electrode and the P + layer, the field oxide film 23, a phenomenon encountered in the + layer occurs.
따라서, 스토리지 전극과 필드 산화막(23)간에 형성되는 정션(junction)은 공핍층이 얇고 전계의 세기는 매우 크다.Therefore, the junction formed between the storage electrode and the field oxide film 23 has a thin depletion layer and a very high electric field strength.
상기와 같은 종래 반도체 소자 제조방법은 노드 콘택이 필드 산화막에 국부적으로 형성되는 것을 피할 수 없는 제품에 있어서는 기생적 정션 구조내에 존재하는 공핍층의 내부전계가 스토리지 셀에 저장된 전하를 누설시켜 제품의 리프레쉬 특성을 저하시키는 결과를 초래하는 문제점이 있었다.In the conventional method of manufacturing a semiconductor device as described above, in a product in which a node contact is locally formed in a field oxide film, an internal electric field of a depletion layer existing in a parasitic junction structure leaks charge stored in a storage cell to refresh the product. There was a problem that results in deterioration of properties.
본 발명은 상기한 종래의 문제점을 해결하기 위해 안출한 것으로, 스토리지 전극과 필드 산화막과의 접합 부근에서 두 접합간의 농도 분포가 완만해지도록 전계의 세기를 완화시켜 제품의 리프레쉬 특성을 개선시키는데 적당한 반도체 소자 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and is suitable for improving the refresh characteristics of a product by relieving the strength of an electric field so that the concentration distribution between two junctions is smooth in the vicinity of the junction between the storage electrode and the field oxide film. Its purpose is to provide a device manufacturing method.
도 1은 종래 반도체 소자 제조방법에 따른 레이아웃도1 is a layout diagram according to a conventional semiconductor device manufacturing method
도 2a 내지 2b는 종래 반도체 소자 제조방법을 설명하기 위한 공정단면도2A through 2B are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.
도 3은 본 발명의 반도체 소자 제조방법에 따른 레이아웃도3 is a layout diagram according to a method of manufacturing a semiconductor device of the present invention;
도 4a 내지 4b는 본 발명의 반도체 소자 제조방법을 설명하기 위한 공정단면도4A through 4B are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
41 : 반도체 기판 42 : 채널 스톱 이온41 semiconductor substrate 42 channel stop ion
43 : 필드 산화막 44 : 전계완화용 불순물층43: field oxide film 44: impurity layer for electric field relaxation
45 : 소오스 또는 드레인 불순물영역 46 : 절연막45 source or drain impurity region 46 insulating film
47 : 노드 콘택47: node contact
상기의 목적을 달성하기 위한 본 발명의 반도체 소자 제조방법은 스토리지 전극이 필드산화막에 국부적으로 형성되는 반도체 소자에 있어서, 제 1 도전형의 필드산화막에 의해 정의되는 활성영역의 반도체 기판상에 게이트 절연막을 개재하여 게이트 전극을 형성하는 공정, 상기 게이트 전극에 평행한 방향으로 경사 이온주입을 교차지게 주입하여 제 2 도전형의 고농도 소오스 또는 드레인 불순물 영역을 형성하고, 동시에 상기 필드산화막의 하부면에 제 2 도전형의 저농도 불순물층을 형성하는 공정, 상기 게이트 전극을 포함한 반도체 기판 전면에 절연막을 증착한 후, 패터닝하여 노드콘택을 형성하는 공정, 상기 소오스 또는 드레인 불순물 영역 및 상기 저농도 불순물층 그리고 상기 필드산화막의 소정부분에 접하도록 제 2 도전형의 스토리지 전극을 형성하는 공정을 포함하여 이루어지는 것을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving the above object is a gate insulating film on a semiconductor substrate in the active region defined by the field oxide film of the first conductivity type in the semiconductor device in which the storage electrode is formed locally on the field oxide film Forming a gate electrode through the gate electrode, and injecting diagonal ion implantation in a direction parallel to the gate electrode to form a high concentration source or drain impurity region of a second conductivity type, and simultaneously Forming a two-conductive low concentration impurity layer, depositing an insulating film on the entire surface of the semiconductor substrate including the gate electrode, and then patterning to form a node contact, the source or drain impurity region and the low concentration impurity layer, and the field A storage electrode of the second conductivity type so as to contact a predetermined portion of the oxide film It characterized by comprising a step of forming a.
이하, 본 발명의 반도체 소자 제조방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a method of manufacturing a semiconductor device of the present invention will be described with reference to the accompanying drawings.
도 3은 본 발명의 반도체 소자 제조방법에 따른 레이아웃도이다.3 is a layout diagram according to a method of manufacturing a semiconductor device of the present invention.
도 3에 도시된 A는 활성영역이고, B는 게이트 전극, C는 스토리지 전극이 형성되는 영역이다.In FIG. 3, A is an active region, B is a gate electrode, and C is a region where a storage electrode is formed.
여기서, 활성영역(A) 이외의 부분이 필드영역이다.Here, the part other than the active area A is a field area.
도면에서와 같이, 스토리지 전극이 필드산화막에 국부적으로 형성되는 반도체 소자에 있어서, 활성영역에 접하는 필드산화막의 하부에 스토리지 전극과 동일도전형이고, 스토리지 전극에 비해 저농도를 갖는 전계완화용 불순물층(44)을 형성하였다.As shown in the figure, in a semiconductor device in which a storage electrode is formed locally on a field oxide film, an impurity layer for electric field relaxation having the same conductivity type as the storage electrode and a lower concentration than the storage electrode under the field oxide film in contact with the active region ( 44).
이와 같은 본 발명의 반도체 소자 제조방법을 도 4a 내지 4b를 참조하여 설명하면 다음과 같다.Such a method of manufacturing a semiconductor device of the present invention will be described with reference to FIGS. 4A to 4B.
도 4a에 도시한 바와 같이, 필드영역과 활성영역으로 정의된 제 1 반도체 기판(41)의 필드영역에 채널스톱 이온(42)을 주입한 후, 제 1 도전형의 필드산화막(43)을 형성한다.As shown in FIG. 4A, after injecting channel stop ions 42 into the field region of the first semiconductor substrate 41 defined as the field region and the active region, a field oxide layer 43 of the first conductivity type is formed. do.
활성영역상의 반도체 기판(41)상에 게이트 절연막(도시되지 않음)을 형성하고, 상기 게이트 절연막상에 게이트 전극물질을 증착한다.A gate insulating film (not shown) is formed on the semiconductor substrate 41 in the active region, and a gate electrode material is deposited on the gate insulating film.
사진 식각 공정을 통해 상기 게이트 전극물질을 선택적으로 제거하여 게이트 절연막에 의해 반도체 기판(41)과 절연되는 게이트 전극(도시되지 않음)을 형성한다.The gate electrode material is selectively removed through a photolithography process to form a gate electrode (not shown) insulated from the semiconductor substrate 41 by the gate insulating layer.
게이트 전극을 마스크로 이용한 저농도의 불순물 이온주입으로 LDD영역(도시되지 않음)을 형성한 후, 상기 게이트 전극 양측면에 측벽(도시되지 않음)을 형성한다.After the LDD region (not shown) is formed by implanting impurity ions at low concentration using the gate electrode as a mask, sidewalls (not shown) are formed on both sides of the gate electrode.
상기 측벽은 게이트 전극을 포함한 기판(41) 전면에 절연물질을 증착한 후, 에치백하는 공정에 의해 형성된다.The side wall is formed by depositing an insulating material on the entire surface of the substrate 41 including the gate electrode and then etching back.
이때, 이후에 형성될 스토리지 전극이 필드산화막에 국부적으로 형성되는 것을 피할 수 없는 제품에 있어서는 스토리지 전극과 필드산화막간의 접합면에 나타나는 강한 전계로 인해 스토리지 전극에 형성된 전하가 누설되어 리프레쉬 특성이 저하되는데, 본 발명에서는 상기와 같은 문제를 해결하기 위해 상기 필드산화막과 반대도전형인 n-불순물을 경사지게 주입하여 전계완화용 불순물층(44)을 형성한다.In this case, in the case where the storage electrode to be formed later cannot be locally formed in the field oxide film, the strong electric field appearing at the junction between the storage electrode and the field oxide film leaks the charges formed in the storage electrode, thereby reducing the refresh characteristics. In the present invention, in order to solve the above problems, n − impurities having a conductivity opposite to that of the field oxide film are inclined to form an electric field relaxation impurity layer 44.
여기서, n-불순물을 경사지게 주입하기 때문에 상기 전계완화용 불순물층(44)의 농도는 왕복 2회에 걸쳐 불순물이 주입되는 중앙부위(소오스 또는 드레인 불순물 영역으로 사용됨)(45)에 비해 저농도를 유지한다.Here, n - because obliquely implanting impurities (which is used as a source or a drain impurity region) concentrations reciprocating twice the center portion where the impurity is implanted over the impurity layer 44 for the electric-field stress maintain a low concentration compared to 45 do.
이때, n-불순물은 게이트 전극에 대하여 평행한 축에 대해서만 실시하고, 수직한 축에 대해서는 실시하지 않는다.At this time, n − impurities are performed only for the axis parallel to the gate electrode, and not for the axis perpendicular to the gate electrode.
따라서, 활성영역에 접하는 필드산화막(43)의 하부에만 전계완화용 불순물층(44)이 형성된다.Therefore, the electric field relaxation impurity layer 44 is formed only under the field oxide film 43 in contact with the active region.
이와 같이, 전계완화용 불순물층(44)을 형성한 후, 도 4b에 도시한 바와 같이, 상기 게이트 전극을 포함한 기판(41)상에 절연막(46)을 증착한다.In this manner, after the impurity layer 44 for electric field relaxation is formed, an insulating film 46 is deposited on the substrate 41 including the gate electrode as shown in FIG. 4B.
이후, 사진식각 공정을 이용하여 상기 전계완화용 불순물층(44) 및 상기 소오스 또는 드레인 불순물 영역(45)이 노출되도록 상기 절연막을 패터닝하여 노드 콘택(47)을 형성한다.Subsequently, the insulating layer is patterned to form the node contact 47 so that the field relaxation impurity layer 44 and the source or drain impurity region 45 are exposed using a photolithography process.
이어, 상기 소오스 또는 드레인 불순물 영역(45) 및 상기 저농도의 전계완화용 불순물층(44) 그리고 상기 필드산화막(43)의 소정부분에 접하도록 제 2 도전형의 스토리지 전극(도시하지 않음)을 형성한다.Subsequently, a second conductivity type storage electrode (not shown) is formed to contact the source or drain impurity region 45, the low concentration electric field relaxation impurity layer 44, and a predetermined portion of the field oxide layer 43. do.
그리고 도면에 도시되지 않았지만, 스토리지 전극상에 커패시터 유전체막과 플레이트 전극을 형성하면 본 발명에 따른 반도체 소자 제조공정이 완료된다.Although not shown in the drawings, the capacitor dielectric film and the plate electrode are formed on the storage electrode to complete the semiconductor device manufacturing process according to the present invention.
이상에서 상술한 바와 같이, 본 발명의 반도체 소자 제조방법은 필드산화막에 국부적으로 형성되는 스토리지 전극이 전계완화용 불순물층상에 형성되므로 스토리지 전극과 필드산화막간의 접합면에서 전계를 완화시켜 스토리지 전극에 저장된 전하가 누설되는 것을 방지한다. 따라서, 소자의 리프레쉬(Refresh) 특성을 개선시키는 효과가 있다.As described above, in the semiconductor device manufacturing method of the present invention, since the storage electrode formed locally on the field oxide film is formed on the impurity layer for relaxing the field, the electric field is relaxed at the junction between the storage electrode and the field oxide film and stored in the storage electrode. Prevents leakage of charge. Therefore, there is an effect of improving the refresh characteristics of the device.
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| CN117219657B (en) * | 2023-11-07 | 2024-02-06 | 江苏游隼微电子有限公司 | Transverse punching type SiC-TVS device and preparation method thereof |
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