KR20000031767A - Planar type triac device and fabrication method thereof - Google Patents

Abstract

PURPOSE: A planar typed TRIAC device is provided to improve the balance of the trigger characteristics of TRIAC device in all maximum modes and to improve the trigger function of the TRIAC device in a fourth maximum operation mode. CONSTITUTION: A p+ typed device separation area(31) of a second conductive type is formed on a certain part of upper/lower surfaces of an n-typed semiconductor substrate(30) of a first conductive type. Then, a p-typed first anode area(32) is formed on a certain part of the upper surface of the substrate, and a p-typed second anode area(33) is formed on the lower surface of the substrate. Then, an n+ typed gate area(35) and an n- typed first cathode area(34) are formed on the first anode area for being separated from each other. And, an n+ typed second cathode area(36) is formed on the second anode area. Herein, the semiconductor substrate area plays a role of a drift. Also, each conductive layer(41,42) is connected to the first anode area and the first cathode area, and a conductive layer(44) is connected to the second anode area including the second cathode area. The conductive layers are electrically connected to a first main electrode(T1) while being electrically connected to a gate electrode(G) and to a second main electrode(T2).

Description

Planer type triac element and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planar type triac element, and more particularly, to a planar type triac element for improving the trigger characteristics of the fourth upper limit operation mode and improving the trigger characteristics balance in all the upper limit modes. It relates to a manufacturing method.

In general, a triac (TRIAC) device is a semiconductor device having a structure in which two thyristor devices are gated in common and connected in parallel to each other, and thus are mainly used for alternating current switching. The triac element controls the AC power by switching the main electrode T1 from the off state to the on state according to the voltage applied to the main electrode T2 and the gate electrode G.

The operation is divided into four upper limit operation modes according to the bias states of the main electrode T2 and the gate electrode G. FIG. That is, in the first upper limit operation mode, a constant voltage is applied to the main electrode T2 and a constant voltage is applied to the gate electrode G. In the second upper limit operation mode, a constant voltage is applied to the main electrode T2 and a negative voltage is applied to the gate electrode G. In the third upper limit operation mode, a negative voltage is applied to the main electrode T2 and a negative voltage is applied to the gate electrode G. In the fourth upper limit operation mode, a negative voltage is applied to the main electrode T2, and a constant voltage is applied to the gate electrode G.

However, in general, two of the upper limit operation modes except the fourth upper limit operation mode among the four upper limit operation modes have been used in combination. The fourth upper limit operation mode has not been used so far since the gate current required for the operation is larger than other upper limit operation modes due to the complexity of the operation mechanism.

In the conventional planar type triac device, as shown in FIG. 1, the p + type device isolation region 11 is formed in a portion of the upper and lower surfaces of the n-type semiconductor substrate 10 as a drift layer. The p-type first anode region 12 is formed on a portion of the upper surface of the substrate 10, the p-type second anode region 13 is formed on the lower surface of the substrate 10, and the first anode region 12 is formed. The n + type first cathode region 14 and the n + type gate region 15 are formed spaced apart from each other, and the n + type second cathode region 16 is formed in the second anode region 13.

In addition, the conductive layers 21 and 22 are connected to the first anode region 12 and the first cathode region 14, respectively, and the conductive layer 23 is connected to the gate region 15. It extends and connects to the 1st anode area | region 12 partially, and the conductive layer 24 is connected to the 2nd anode area | region 13 including the 2nd cathode area | region 16. FIG. The conductive layers 21 and 22 are electrically connected to the first main electrode T1 in common, the conductive layer 23 is electrically connected to the gate electrode G, and the conductive layer 24 is connected to the second main electrode. It is electrically connected to the electrode T2.

In the conventional triac element configured as described above, since the first and second anode regions 12 and 13 are formed at the same time, they have the same doping concentration and the junction depth. This is because the trigger operation in the fourth upper limit operation mode is not required, and the trigger operation in the other operation modes does not require high sensitivity.

In addition, the first and second cathode regions 14, 16 do not vertically overlap at all.

However, in recent years, the demand for semiconductor devices capable of all four upper limit operation modes including the fourth upper limit operation mode has increased, and in particular, the triac element of an integrated circuit using the first upper limit operation mode and the fourth upper limit operation mode has been increasing. Direct drive realization is required.

However, in the case of the conventional triac device, the above-mentioned requirements are not properly met due to the constraints on the mechanism of operation, as the p-type regions 12 and 13, which are the anode layers, are formed with the same doping concentration and the junction depth. Can't. Therefore, it is difficult to increase the sensitivity of the trigger characteristics in the fourth upper limit operation mode, and the balance of the trigger characteristics is poor in all the upper limit operation modes.

Accordingly, an object of the present invention is to improve the trigger function of the triac element in the fourth upper limit operation mode.

It is another object of the present invention to improve the balance of the trigger characteristics of the triac element in all upper operating modes.

1 is a cross-sectional view showing a planar type triac (TRIAC) device according to the prior art.

2 is a cross-sectional view showing a planar type triac device according to the present invention.

Figure 3a to 3d is a process chart showing a method of manufacturing a planar type triac device according to the present invention.

<Explanation of symbols for main parts of the drawings>

DESCRIPTION OF REFERENCE NUMERALS 10 semiconductor substrate 11 device isolation region 12 first anode region 13 second anode region 14 first cathode region 15 gate region 16 second cathode region 21, 22, 23, 24 conductive layer 30 semiconductor Substrate 31 Device isolation region 32 First anode region 33 Second anode region 34 First cathode region 35 Gate region 36 Second cathode regions 41, 42, 43, 44 Conductive layers 51, 53, 55 Insulating films 52,54,56,57,58: openings

In the planar type triac device according to the present invention, a second conductive type device isolation region is formed in each of the upper and lower portions of the first conductive semiconductor substrate which is the drift layer, and the second conductive type isolation region is formed in the partial region of the upper surface of the substrate. A conductive first anode region is formed, a second conductive second anode region is formed on a lower surface of the substrate, and the first conductive first cathode region and the first conductive gate region are spaced apart from each other in the first anode region. And a first conductivity type second cathode region are formed in the second anode region, the conductive layers respectively connected to the first cathode region and the first anode region are commonly connected to the first main electrode, and the first anode A triacoxide in which a conductive layer partially extending into the region and connected to the gate region is connected to the gate electrode, and a conductive layer connected to the second anode region including the second cathode region is connected to the second main electrode; The method further characterized in that the first anode region and the second anode region formed of a different doping levels and junction depths from each other.

Preferably, the second anode region is doped to a lower concentration than the first anode region. The second anode region has a junction depth that is shallower than the first anode region. The first cathode region and the second cathode region partially overlap vertically.

In the method of manufacturing a planar type triac device according to the present invention, a second conductivity type device isolation region is formed on both upper and lower surfaces of a first conductivity type semiconductor substrate as a drift layer, and a second conductivity is formed on a portion of the upper surface of the substrate. In addition to forming a type first anode region, a second conductivity type second anode region is formed on the bottom surface of the substrate, and the first conductivity type first cathode region and the first conductivity type gate region are spaced apart from each other. And a first conductivity type second cathode region in the second anode region, a conductive layer is formed in each of the first cathode region and the first anode region and partially extends to the first anode region, and the conductive layer is formed in the gate region. , A conductive layer is formed in the second anode region including the second cathode region, and the conductive layer on the first cathode region and the first anode region is connected to the first main electrode in common. And a triac element manufacturing method for connecting a conductive layer on a second anode region including a second cathode region to a second main electrode and connecting a conductive layer on the gate region to a gate electrode. The two anode regions are formed to have different doping concentrations and junction depths.

Preferably, the second anode region is doped to a lower concentration than the first anode region. The second anode region has a junction depth that is shallower than the first anode region. The first cathode region and the second cathode region partially overlap vertically.

Therefore, the present invention improves the trigger characteristic in the fourth upper limit operation mode and improves the balance of the trigger characteristic in all the upper limit operation modes.

Hereinafter, a planar type triac device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view showing the structure of a planar type triac device according to the present invention.

As shown in FIG. 2, in the triac device of the present invention, a p + type device isolation region 31 of a second conductivity type is formed in a portion of upper and lower surfaces of both surfaces of the first conductivity type n-type semiconductor substrate 30. The p-type first anode region 32 is formed on a portion of the upper surface of the substrate 30, the p-type second anode region 33 is formed on the lower surface of the substrate 30, and the first anode region 32 is formed. The n + type first cathode region 34 and the n + type gate region 35 are formed to be spaced apart from each other, and the n + type second cathode region 36 is formed in the second anode region 33. Here, the semiconductor substrate 30 acts as a drift layer.

In addition, the conductive layers 41 and 42 are connected to the first anode region 32 and the first cathode region 34, respectively, and the conductive layer 43 is connected to the gate region 35. A part of the first anode region 12 extends and is connected, and the conductive layer 44 is connected to the second anode region 33 including the second cathode region 36. The conductive layers 41 and 42 are electrically connected in common to the first main electrode T1, the conductive layer 43 is electrically connected to the gate electrode G, and the conductive layer 44 is connected to the second main electrode. It is electrically connected to the electrode T2.

Here, the second anode region 33 is doped to a lower concentration than the first anode region 32. The second anode region 33 has a shallower junction depth than the first anode region 32. The first cathode region 34 and the second cathode region 36 partially overlap each other vertically. The method of manufacturing the triac device configured as described above will be described in detail with reference to FIGS. 3A to 3D. 3A to 3D are process charts showing a method for manufacturing a triac device according to the present invention.

As shown in FIG. 3A, first, an insulating film 51, for example, an oxide film is grown on both upper and lower surfaces of the first conductivity type n-type semiconductor substrate 30, and then the p + type isolation is removed. In order to expose the upper and lower surfaces of the semiconductor substrate 30 in the region corresponding to the region 31, the opening 52 is formed in a predetermined region of the insulating film 51 by a photolithography process. Here, the semiconductor substrate 30 acts as a drift layer.

Subsequently, the same p-type liquid diffusion source is coated on the upper and lower surfaces of the semiconductor substrate 30 having the above structure by using a diffusion method using a liquid diffusion source, which is one of the conventional methods, and diffused, thereby dispersing the semiconductor substrate in the opening 52. P + type device isolation regions 31 are formed on the upper and lower surfaces of (30).

As shown in FIG. 3B, an insulating film 53, for example, an oxide film, is grown to cover the upper and lower surfaces of the semiconductor substrate 30 in the opening 52.

Then, an opening 54 is formed in a predetermined region of the insulating film 53 by a photolithography process to expose the upper surface of the semiconductor substrate 30 in the region corresponding to the p-type first anode region 32. In addition, the insulating film on the lower surface of the semiconductor substrate 30 is completely etched to expose the entire lower surface of the semiconductor substrate 30.

Next, a first p-type liquid diffusion source having a first concentration is coated on the upper surface of the semiconductor substrate 30 of the structure, and a second p-type liquid diffusion source having a second concentration is formed on the bottom surface of the semiconductor substrate 30. The entire surface of the semiconductor substrate 30 in the opening 54 to form a p-type first anode region 32 on the bottom surface of the semiconductor substrate 30, and simultaneously diffuse the same, To form. At this time, the first anode region 32 is formed with a higher doping concentration and a deeper junction depth than the second anode region 33. For this purpose, the first concentration of the first liquid diffusion source is the second of the second liquid diffusion source. It must be higher than the concentration.

As shown in FIG. 3C, an insulating film 55, for example, an oxide film, is grown to cover the upper surface of the semiconductor substrate 30 and the lower surface of the semiconductor substrate 30 in the opening 54.

Thereafter, the upper surface of the semiconductor substrate 30 in the region corresponding to the n + type first cathode region 34 and the n + type gate region 35 and the semiconductor substrate 30 in the region corresponding to the second cathode region 36 are formed. Openings 56, 57, and 58 are formed in a predetermined region of the insulating film 53 by a photolithography process to expose the lower surface.

Then, the same n-type liquid diffusion source is coated on the upper surface of the semiconductor substrate 30 and the lower surface of the semiconductor substrate 30 of the structure, respectively, and then diffused at the same time to n + type to the semiconductor substrate 30 in the opening 56 The first cathode region 34 is formed, the n + type gate region 35 is formed in the semiconductor substrate 30 in the opening 57, and the n + type second is formed on the bottom surface of the semiconductor substrate 30 in the opening 58. The cathode region 36 is formed.

In this case, the first and second cathode regions 34 and 36 may be partially overlapped vertically.

As shown in FIG. 3D, an insulating film (not shown) is then applied to cover the upper surface of the semiconductor substrate 30 in the openings 56 and 57 and the lower surface of the semiconductor substrate 30 in the opening 58. For example, an oxide film is grown.

Then, contact holes (not shown) for the conductive layers 41, 42, and 43 are formed in a predetermined region of the insulating film by a photolithography process. At this time, the entire lower surface of the semiconductor substrate 30 is exposed. Here, the contact hole for the conductive layer 41 exposes a portion of the first anode region 32, and the contact hole for the conductive layer 42 includes a portion of the first anode region 32 and a gate region ( A portion of 43 is exposed together, and a contact hole for the conductive layer 43 exposes a portion of the first cathode region 34.

Then, a conductive layer is deposited on the upper and lower surfaces of the semiconductor substrate 30 having the above structure, and the conductive layer is formed in a pattern of conductive layers 41, 42, and 43 by a photolithography process. In addition, it forms in the pattern of the conductive layer 44. FIG.

That is, the conductive layer 41 is connected to a partial region of the first anode region 32, and the conductive layer 42 extends to a partial region of the first anode region 32 and to a partial region of the gate region 43. The conductive layer 43 is connected to a partial region of the first cathode region 34, and the conductive layer 44 is connected to the second anode region 33 including the second cathode region 36.

Finally, as illustrated in FIG. 2, the conductive layers 41 and 42 are electrically connected to the first main electrode T1, and the conductive layer 43 is electrically connected to the gate electrode G. The conductive layer 44 is electrically connected to the second main electrode T2.

In the triac device manufactured by the above method, the doping concentration and the junction depth of the first anode region 32 and the second anode region 33 are different from each other. That is, the second anode region 33 is doped to a lower concentration than the first anode region 32, and the second anode region 33 has a shallower junction depth than the first anode region 32. In addition, the first and second cathode regions 34 and 36 partially overlap each other vertically.

Therefore, the triac device of the present invention can achieve high sensitivity of the gate trigger characteristic in the fourth upper limit operation mode. That is, the gate current flows in the transverse direction of the first anode region 32 from the conductive layer 43 connected to the gate electrode G to the conductive layer connected to the first main electrode T1 in the fourth upper limit operation mode. Electrons are injected from a portion close to the gate region 35 in the junction J1 between the first anode region 32 and the first cathode region 34.

Then, the electrons reach the semiconductor substrate 30 which is the drift layer and lower the potential of the portion to forward-bias the junction J1, and holes are injected from the first anode region 32 into the semiconductor substrate 30. . This hole diffuses into the semiconductor substrate 30 to reach the second anode region 33 and finally flows into the second main electrode T2 via the second cathode 36. In this case, since the first cathode region 34, which starts the injection of electrons, is formed to vertically overlap with the partial region of the second anode region 36, the semiconductor substrate 30 is diffused so that the second anode region 33 Holes that have reached N) avoid the second cathode region 36 and the overlapped portion of the second anode region 33 flows laterally in the second anode region 33. At this time, a transverse voltage drop occurs in the second anode region 33 due to the lateral resistance of the overlapped portion, and partially forward-biases the junction J2 between the second anode region 33 and the second cathode region 36. As a result, electrons are injected from the second cathode region 36. The electrons diffuse the second anode region 33 and inject into the semiconductor substrate 30 to lower the potential of the semiconductor substrate 30.

Since the junctions J1 and J2 are strongly forward biased by this series of operations, the thyristor composed of the first anode region 32, the semiconductor substrate 30, the second anode region 33, and the second cathode region 36 is turned on. It enters a state and operation by a 4th upper limit operation mode is started.

As described above, according to the planar type triac device and a method of manufacturing the same according to the present invention, the first anode region formed together with the gate region on one surface of the semiconductor substrate is higher than the second anode region formed on the other surface of the semiconductor substrate. Doped to concentration and formed to deep junction depth.

Therefore, the triac element of the present invention can achieve high sensitivity of the trigger characteristic even in the fourth upper limit operation mode, and improve the balance of the trigger characteristic in all the upper limit operation modes.

On the other hand, in the present invention, it is obvious that in addition to the doping method using the liquid diffusion source, the doping method using the ion implantation process can be applied.

Claims (6)

A first conductivity type semiconductor substrate which is a drift layer; Second conductivity type device isolation regions formed in partial regions of upper and lower surfaces of the substrate, respectively; A second conductivity type first anode region formed in a portion of the upper surface of the substrate; A second conductivity type second anode region formed on the bottom surface of the substrate and having a doping concentration and a junction depth different from the doping concentration and the junction depth of the first anode region; A first conductivity type first cathode region formed in a portion of the first anode region; A first conductivity type gate region formed in a portion of the first anode region spaced apart from the first cathode region; A first conductivity type second cathode region formed in a portion of the second anode region; A conductive layer connected to each of the first cathode region and the first anode region and commonly connected to a first main electrode; A conductive layer partially extending into the first anode region and connected to the gate region and connected to a gate electrode; And And a conductive layer connected to a second anode region including the second cathode region and connected to a second main electrode. The planar device of claim 1, wherein the second anode region is formed with a lower doping concentration and a shallower junction depth than the first anode region. The planar type triac device according to claim 1 or 2, wherein the first cathode region and the second cathode region are partially overlapped vertically. Forming a second conductivity type isolation region in partial regions on both upper and lower surfaces of the first conductive semiconductor substrate as a drift layer; A second conductivity type agent having a second conductivity type first anode region in a portion of the upper surface of the substrate, and having a doping concentration and a bonding depth different from the doping concentration and the bonding depth of the first anode region on the lower surface of the substrate. Forming a two anode region; Forming a first conductivity type first cathode region and a first conductivity type gate region in the first anode region, and forming a first conductivity type second cathode region in the second anode region; And A conductive layer connected to the first cathode region and a first anode region and commonly connected to a first main electrode, a conductive layer partially extending to the first anode region and connected to the gate region, and connected to a gate electrode; Forming a conductive layer connected to a second anode region including the second cathode region and connected to a second main electrode. The method of claim 4, wherein the second anode region is formed at a lower doping concentration and a shallower junction depth than the first anode region. The method according to claim 4 or 5, wherein the first cathode region and the second cathode region are partially overlapped vertically.