KR20000031195A - Soi semiconductor device with improved characteristic for protecting electrostatic discharge and producing method thereof - Google Patents
Soi semiconductor device with improved characteristic for protecting electrostatic discharge and producing method thereof Download PDFInfo
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- KR20000031195A KR20000031195A KR1019980047107A KR19980047107A KR20000031195A KR 20000031195 A KR20000031195 A KR 20000031195A KR 1019980047107 A KR1019980047107 A KR 1019980047107A KR 19980047107 A KR19980047107 A KR 19980047107A KR 20000031195 A KR20000031195 A KR 20000031195A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 title claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 73
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 73
- 239000010703 silicon Substances 0.000 claims abstract description 73
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 7
- -1 oxygen ions Chemical class 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims 2
- 239000012212 insulator Substances 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000872 buffer Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
본 발명은 에스오아이(SOI; silicon on insulateor) 기판을 이용하여 제조한 에스오아이 반도체 소자에 관한 것으로, 특히 정전방전(ESD; electrostatic discharge) 보호 성능을 개선한 에스오아이 반도체 소자 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SIO semiconductor device manufactured using a silicon on insulateor (SOI) substrate, and more particularly, to an SIO semiconductor device having improved electrostatic discharge (ESD) protection performance and a method of manufacturing the same. will be.
VLSI회로의 성능향상을 위한 기술로서 SOI기술이 주목을 받고 있다. SOI기술은 집적회로의 요소 회로들(circuit elements)이 매립산화막에 의해 분리되기 때문에 트랜지스터의 래치업이 없어지고, 접합 용량이 줄어든다. 따라서 SOI 반도체 소자는 기생용량의 감소로 인하여 같은 치수(dimension)의 벌크 실리콘 기판에 형성된 집적회로 소자에 비하여 동작 속도가 빠른 장점이 있다. 또한 SOI 기판을 이용한 반도체 소자는 쇼트 채널 효과의 개선, 방사선(radiation)에 대한 강한 내성, 공정의 단순함과, 뛰어나고 확실한 소자 분리 특성으로 인하여 0.1㎛ 이하의 모스페트(MOSFET) 트랜지스터를 제작하는데 적용가능성이 높을 것으로 평가되고 있다.SOI technology is attracting attention as a technology for improving the performance of the VLSI circuit. SOI technology eliminates latchup of transistors and reduces junction capacity because the circuit elements of the integrated circuit are separated by buried oxide. Therefore, the SOI semiconductor device has an advantage that the operation speed is faster than the integrated circuit device formed on the bulk silicon substrate having the same dimensions due to the reduction of parasitic capacitance. In addition, semiconductor devices using SOI substrates can be applied to fabricate MOSFET transistors smaller than 0.1 μm due to improved short channel effects, strong resistance to radiation, simplicity of process, and excellent and reliable device isolation characteristics. This is estimated to be high.
그러나 현재까지 SOI 기판을 사용하여 집적회로 소자를 제조하는데 있어서 가장 큰 문제점은, 반도체 칩을 구성하는 집적회로 소자에 대해서는 우수한 성능을 갖도록 하는 매립 절연막이, ESD 보호 특성에 대해서는 오히려 악영향을 미치고 있다는 것이며, 이 점이 SOI 기판이 벌크 실리콘 기판을 대체하는데 장애가 되고 있다.However, to date, the biggest problem in manufacturing integrated circuit devices using SOI substrates is that buried insulating films, which have excellent performance for integrated circuit devices constituting semiconductor chips, have an adverse effect on ESD protection characteristics. This is an obstacle for SOI substrates to replace bulk silicon substrates.
참고로, 벌크 실리콘 기판에서의 ESD 보호 특성과 SOI 기판에서의 ESD 보호특성에 대해 비교한 내용이 Proceedings of 1994 IEEE/IRPS, pp292-298, "Comparison of ESD Protection Capability of SOI and Bulk CMOS Output Buffers"에서 Mansun Chan, Selina S. Yuen, Zhi-Zian Ma, Chenming Hu등에 의해 발표되었다. 상기 참조 자료에 의하면, SOI 기판에서 ESD 보호 특성이 악화되는 이유로서, 벌크 실리콘 기판에서의 ESD 보호 트랜지스터는 기판과 드레인간 p-n 접합에 의해 낮은 직렬저항(low series resistance)이 형성되는데 비하여, SOI 기판에 형성된 ESD 보호 트랜지스터의 경우에는 드레인 아래에 매립 절연막(SiO2)이 형성되어 있기 때문에 그러한 p-n 접합이 형성되지 못하며 따라서 직렬 저항 성분이 없기 때문인 것으로 분석하고 있다. 또, ESD 발생(ESD event) 동안, 열이 발생되는데 이때 매립 산화막인 실리콘 산화막의 열방출(heat sink) 능력이 벌크 실리콘에 비하여 떨어지는 것도 또다른 이유이다. 따라서, 상기와 같은 점을 고려할 때, SOI기판을 이용하여 ESD 보호소자를 제조할 때, 매립 산화막 위의 실리콘 필름의 두께가 두꺼울수록 ESD 보호 특성이 좋아진다고 한다. 도1은 상기 참조자료에서 제시한 실리콘 필름의 두께에 따른 ESD 파괴 전압의 변화를 도시하고 있다. 도1의 X축에 나타난 숫자는 SOI기판의 매립 절연막 위에 형성되어 있는 실리콘 필름의 두께를 나타낸 것으로 X축의 오른쪽으로 갈수록 두께가 두꺼워 진다. Y축에 나타난 숫자는 ESD 파괴 전압을 나타내고 있다. 도1에 도시된 바와 같이, SOI 기판위에 형성된 ESD 보호소자에서 매립 산화막위의 실리콘 필름의 두께가 두꺼워 질수록 ESD 파괴 전압이 높아짐을 알 수 있다. 즉 실리콘 필름의 두께가 두꺼울수록 더 높은 전압의 정전 방전에 대해서도 견딜 수 있다는 것을 의미한다. 따라서 상기 ESD 파괴 전압이 높을수록 ESD보호의 신뢰성이 높다고 할 수 있다.For reference, a comparison of ESD protection on bulk silicon substrates and ESD protection on SOI substrates can be found in Proceedings of 1994 IEEE / IRPS, pp292-298, "Comparison of ESD Protection Capability of SOI and Bulk CMOS Output Buffers". Presented by Mansun Chan, Selina S. Yuen, Zhi-Zian Ma and Chenming Hu. According to the above reference, as a reason for the deterioration of ESD protection characteristics in an SOI substrate, an ESD protection transistor in a bulk silicon substrate has a low series resistance due to a pn junction between the substrate and the drain, whereas an SOI substrate is formed. In the case of the ESD protection transistor formed therein, the buried insulating film (SiO2) is formed under the drain, such a pn junction is not formed, and therefore it is analyzed that there is no series resistance component. In addition, heat is generated during an ESD event, and the heat sinking capability of the silicon oxide film, which is a buried oxide film, is also lower than that of bulk silicon. Accordingly, in view of the above, when the ESD protection device is manufactured using the SOI substrate, the thicker the thickness of the silicon film on the buried oxide film is, the better the ESD protection property is. Figure 1 shows the change in ESD breakdown voltage with the thickness of the silicon film presented in the above reference. The number on the X axis of FIG. 1 represents the thickness of the silicon film formed on the buried insulating film of the SOI substrate, and the thickness becomes thicker toward the right side of the X axis. The number on the Y-axis represents the ESD breakdown voltage. As shown in FIG. 1, it can be seen that as the thickness of the silicon film on the buried oxide film becomes thicker in the ESD protection device formed on the SOI substrate, the ESD breakdown voltage increases. In other words, the thicker the silicon film, the higher the voltage can withstand electrostatic discharge. Therefore, the higher the ESD breakdown voltage, the higher the reliability of the ESD protection.
본 발명은 상기와 같은 문제점에 근거하여 안출된 것으로, 본발명의 목적은 매립 산화막이 상대적으로 얕게 형성된 영역과 상대적으로 깊게 형성된 영역을 갖는 SOI 기판에 있어서, 매립산화막의 깊이가 깊은 영역에는 ESD보호소자가 형성되고 매립 산화막의 깊이가 얕은 영역에는 집적회로 소자를 형성된 ESD보호 특성을 개선한 SOI 반도체 소자를 제공하는 것을 목적으로 한다.The present invention has been made in view of the above problems, and an object of the present invention is to provide an ESD protection device in a deep region of a buried oxide film in an SOI substrate having a relatively shallow region and a relatively deep region. An object of the present invention is to provide an SOI semiconductor device having improved ESD protection characteristics in which an integrated circuit device is formed in a self-formed and shallow region of a buried oxide film.
본발명은 상기 목적을 달성하기 위하여, 벌크 실리콘 기판을 준비하고, 상기 벌크 실리콘 기판 내부에 소정 영역에는 상대적으로 깊은 곳에 매립 산화막을 형성하고 다른 영역에는 상대적으로 얕은 곳에 매립산화막을 형성하고, 상기 상대적으로 매립 산화막의 깊이가 깊은 영역에는 ESD보호 소자를 형성하고 상대적으로 매립 산화막의 깊이가 얕은 영역에는 집적회로 소자를 제조하는 공정으로 이루어진 SOI 반도체 소자의 제조방법을 제공한다.In order to achieve the above object, the present invention provides a bulk silicon substrate, a buried oxide film is formed in a relatively deep region in a predetermined region, and a buried oxide film is formed in a relatively shallow region in another region. Accordingly, an ESD protection device is formed in a deep region of a buried oxide film, and an integrated circuit device is manufactured in a relatively shallow depth of a buried oxide film.
도1. 실리콘 필름의 두께에 따른 정전방전 파괴 전압의 변화를 도시한 그래프.Figure 1. Graph showing the change of the electrostatic discharge breakdown voltage according to the thickness of the silicon film.
도2. 본발명에 따른 SOI반도체 소자의 개략적인 종단면도.Figure 2. Schematic longitudinal sectional view of an SOI semiconductor device according to the present invention.
도3a 내지 도3g. 본발명에 따른 SOI 반도체 소자의 제조공정 순서도.3A-3G. Flow chart of the manufacturing process of SOI semiconductor device according to the present invention.
***** 도면부호의 설명 ********** Explanation of Drawings *****
A1 : 제1영역 A2 : 제2영역A1: first area A2: second area
T1 : 집적회로소자 T2 : ESD 보호 소자T1: integrated circuit device T2: ESD protection device
D1, D2 : SOI기판 표면으로부터 매립 절연막까지의 깊이D1, D2: depth from the surface of the SOI substrate to the buried insulating film
11 : 게이트전극 12 : 소스11 gate electrode 12 source
13 : 드레인 21 : 게이트 전극13 drain 21 gate electrode
22 : 소스 23 : 드레인22: source 23: drain
200 : SOI 기판 201 : 매립 산화막200: SOI substrate 201: buried oxide film
202a, 202b : 실리콘 필름202a, 202b: Silicon Film
203 : 벌크 실리콘203: Bulk Silicon
300 : 벌크 실리콘 기판 300' : 에스오아이 기판300: bulk silicon substrate 300 ': SOH eye substrate
301 : 절연막 301a : 절연막 패턴301: insulating film 301a: insulating film pattern
302 : 매립산화막 303, 303a, 303b : 실리콘 필름302: buried oxide film 303, 303a, 303b: silicon film
304 : 소자 분리용 절연막 306 : 게이트 절연막304: insulating film for device isolation 306: gate insulating film
307a, 307b : 게이트 전극 308a, 308b : 소스/드레인307a and 307b: Gate electrodes 308a and 308b: Source and drain
본발명의 SOI반도체 소자에 관하여 도2를 참조하여 설명하면 다음과 같다. 본 발명은, ESD 보호 특성이 실리콘 필름의 두께가 두꺼울수록 뛰어나다는 데 착안하여 다음과 같이 구성되어 있다.The SOI semiconductor device of the present invention will be described with reference to FIG. The present invention has been constructed as follows, taking note that the ESD protection property is excellent as the thickness of the silicon film is thick.
먼저 SOI기판(200)이 준비되어 있다. SOI기판(200)은 벌크 실리콘 기판내에 매립 산화막(201)(일반적으로 실리콘 산화막)을 형성함으로써 제조된다. 상기 벌크 실리콘 기판내의 매립산화막(201)은 그 상부측의 실리콘 필름(202a, 202b)과 그 하부측의 벌크 실리콘(203)을 전기적으로 분리하는 역할을 한다. 또한, 상기 매립산화막(201)은 집적 회로를 구성하는 소자들이 형성되는 제1영역(A1)에서의 매립 깊이(D1)와 ESD 보호 소자를 형성하기 위한 제2영역(A2)에서의 매립깊이(D2)가 다르도록 형성된다. 즉 ESD 보호 소자를 형성하기 위한 제2영역(A2)의 매립 깊이(D2)가 제1영역(A1)의 매립 절연막(201)의 매립깊이(D1) 보다 깊게 형성되어 있으며, 따라서, 제2영역(A2)의 실리콘 필름(202b)의 두께가 제1영역(A1)의 실리콘 필름(202a)의 두께보다 두껍다. 상기 제1영역(A1)에는 일반적인 집적 회로 소자(T1)가 형성되어 있고, 제2영역(A2)에는 ESD 보호 소자(T2)가 형성되어 있고, 상기 집적회로 소자(T1)와 ESD보호소자(T2)간을 분리용 절연막(isolating insulator)(203)이 전기적으로 분리하고 있다.First, the SOI substrate 200 is prepared. The SOI substrate 200 is manufactured by forming a buried oxide film 201 (generally a silicon oxide film) in a bulk silicon substrate. The buried oxide film 201 in the bulk silicon substrate serves to electrically separate the silicon films 202a and 202b on the upper side thereof and the bulk silicon 203 on the lower side thereof. In addition, the buried oxide film 201 has a buried depth D1 in a first region A1 where elements constituting an integrated circuit are formed and a buried depth in a second region A2 for forming an ESD protection device ( D2) is formed to be different. That is, the buried depth D2 of the second region A2 for forming the ESD protection element is formed deeper than the buried depth D1 of the buried insulating film 201 of the first region A1, and thus, the second region. The thickness of the silicon film 202b of (A2) is thicker than the thickness of the silicon film 202a of the first region A1. A general integrated circuit device T1 is formed in the first area A1, an ESD protection device T2 is formed in the second area A2, and the integrated circuit device T1 and an ESD protection device ( An insulating insulator 203 is electrically separated between T2).
상기 집적 회로 소자(T1)는 실리콘 필름(202a)의 상부에 형성된 게이트 전극(11)과 상기 게이트 전극(11)의 양측 실리콘 필름(202a)내에 형성된 소스(12) 및 드레인(13)으로 구성되어 있다. 한편 ESD 보호 소자(T2)는 실리콘 필름(202b)의 상부에 형성된 게이트 전극(21)과 상기 게이트 전극(21)의 양측 실리콘 필름(202b)내에 형성된 소스(22) 및 드레인(23)으로 구성되어 있다.The integrated circuit device T1 includes a gate electrode 11 formed on the silicon film 202a and a source 12 and a drain 13 formed in both silicon films 202a of the gate electrode 11. have. Meanwhile, the ESD protection element T2 includes a gate electrode 21 formed on the silicon film 202b and a source 22 and a drain 23 formed in both silicon films 202b of the gate electrode 21. have.
상기와 같은 본발명의 SOI 반도체 소자의 제조공정을 도3a 내지 도3h를 이용하여 설명하면 다음과 같다.The manufacturing process of the SOI semiconductor device of the present invention as described above will be described with reference to FIGS. 3A to 3H.
먼저 도3a와 같이 벌크 실리콘 기판(300)위에 절연막(301)을 형성한다. 상기 절연막(301)은 실리콘 산화막 또는 질화막등으로 형성한다. 상기 절연막(301)의 재료는 상기 벌크 실리콘 기판(300)과 식각 선택비가 큰 재료인 것이 바람직하다.First, an insulating film 301 is formed on the bulk silicon substrate 300 as shown in FIG. 3A. The insulating film 301 is formed of a silicon oxide film or a nitride film. The material of the insulating layer 301 is preferably a material having a large etching selectivity with respect to the bulk silicon substrate 300.
다음으로, 사진식각 공정을 이용하여 ESD 보호 소자를 형성하기 위한 영역(A2)(제2영역)의 절연막(301)을 부분적으로 제거하여 도3b와 같이 집적회로 소자를 제조하기 위한 영역(A1)(제1영역)위에 절연막(301) 패턴(301a)을 형성한다.Next, the insulating layer 301 of the region A2 (second region) for forming the ESD protection element is partially removed by using a photolithography process, and the region A1 for manufacturing the integrated circuit device as shown in FIG. 3B. The insulating film 301 pattern 301a is formed on the (first region).
다음으로, 상기 도3b의 전체 구조에 대해 산소 이온주입공정을 실시한다. 이때, 절연막 패턴(301a)이 형성되어 있는 곳에서는 산소 이온이 벌크 실리콘 기판(300)의 얕은 곳에 주입되고, 절연막 패턴(201a)으로 덮여 있지 않은 제2영역(A2)에서는 산소이온이 벌크 실리콘 기판(300)의 깊은 곳까지 침투하게 되어 도3c의 구조가 된다. 도3c에서 벌크 실리콘 기판(300)내의 점으로 표시된 부분이 산소 이온이 존재하는 영역이다.Next, an oxygen ion implantation process is performed for the entire structure of FIG. 3B. At this time, oxygen ions are implanted in the shallow region of the bulk silicon substrate 300 where the insulating film pattern 301a is formed, and oxygen ions are bulk silicon substrate in the second region A2 that is not covered with the insulating film pattern 201a. It penetrates to the depth of 300 and becomes the structure of FIG. 3C. In FIG. 3C, the portion indicated by the dot in the bulk silicon substrate 300 is a region where oxygen ions are present.
다음으로, 상기 도3c의 기판(300)을 고온열처리한다. 상기 고온열처리 공정에 의하여 상기 산소이온과 벌크 실리콘 기판(300)내의 실리콘이 반응하여 도3d와 같이 실리콘 산화막(302)이 형성되어 SOI 기판(300')이 제조된다. 이때, 상기 실리콘 산화막(302)을 매립 절연막(302) 또는 매립 산화막(302)이라고 한다. 상기 벌크 실리콘 기판(300)에서 매립 산화막(302) 윗부분이 반도체 소자(집적회로 소자 및 ESD 보호소자)가 형성될 곳이며 이하 실리콘 필름(303)이라고 한다. 또 이하에서 설명의 편의를 위하여 집적회로 소자를 형성하기 위한 얇은 제1영역(A1)의 얇은 실리콘 필름을 도면부호(303a)로 나타내고 또 ESD 보호소자가 제조될 영역인 제2영역(A2)의 두꺼운 실리콘 필름을 도면부호(303b)로 각각 나타내었다.Next, the substrate 300 of FIG. 3C is subjected to high temperature heat treatment. The oxygen ion and the silicon in the bulk silicon substrate 300 are reacted by the high temperature heat treatment process to form a silicon oxide film 302 as shown in FIG. 3d to manufacture the SOI substrate 300 '. In this case, the silicon oxide film 302 is referred to as a buried insulating film 302 or a buried oxide film 302. An upper portion of the buried oxide layer 302 in the bulk silicon substrate 300 is where a semiconductor device (an integrated circuit device and an ESD protection device) is to be formed, hereinafter referred to as a silicon film 303. In the following description, a thin silicon film of a thin first region A1 for forming an integrated circuit device is denoted by reference numeral 303a, and a thick portion of the second region A2, which is an region where an ESD protection element is to be manufactured, is described below. Silicon films are shown by reference numeral 303b, respectively.
다음으로, 도3e와 같이 각 단위 소자를 분리하기 위한 소자 분리용 절연막(304)을 형성한다. 도3e에서는 소자 분리용 절연막(304)으로서 LOCOS법에 의하여 필드산화막(304)을 형성한 예를 도시하였다. 그러나, 소자 분리용 절연막(304)는 일반적으로 잘 알려진 얕은 트렌치 분리법(shallow trench isolation process)으로 형성할 수도 있으며, 기타 다른 소자 분리방법을 적용하여 형성할 수 있다.Next, as shown in FIG. 3E, an isolation layer 304 for separating the unit elements is formed. 3E shows an example in which the field oxide film 304 is formed by the LOCOS method as the insulating film 304 for element isolation. However, the device isolation insulating film 304 may be formed by a well-known shallow trench isolation process, and may be formed by applying other device isolation methods.
다음으로 도3e의 상기 실리콘 필름(303a, 303b)위에 게이트 절연막(306)을 형성한 후, 상기 게이트 절연막(303a, 303b) 상면 소정부위에 도3f와 같이, 집적회로 소자의 게이트 전극(307a)과 ESD 보호 소자의 게이트 전극(307b)을 각각 형성한다.Next, after the gate insulating film 306 is formed on the silicon films 303a and 303b of FIG. 3E, the gate electrode 307a of the integrated circuit device is formed as shown in FIG. 3F on a predetermined portion of the upper surface of the gate insulating films 303a and 303b. And the gate electrode 307b of the ESD protection element are formed, respectively.
다음으로 도3g와 같이, 상기 게이트 전극(307a, 307b)의 양측 실리콘 필름(303a, 303b)내에 불순물 이온을 주입하여 각 소스/드레인(308a, 308b)을 형성함으로써 본발명의 SOI 반도체 소자 제조를 완료한다.Next, as shown in FIG. 3G, the source / drain 308a and 308b are formed by implanting impurity ions into the silicon films 303a and 303b of the gate electrodes 307a and 307b to form the SOI semiconductor device of the present invention. To complete.
상기와 같이 구성된 본발명의 SOI반도체 소자 및 제조방법에 따르면, SOI반도체 소자의 장점( 래치업 및 기생 용량의 감소로 인한 집적 회로 소자의 빠른 동작 특성, 쇼트 채널 효과의 개선으로 인한 집적도의 증가 및 뛰어난 소자 분리 특성등 )을 가지면서, ESD 보호 특성이 개선되기 때문에 뛰어난 신뢰성과 성능을 갖는 반도체 소자를 제공하여 시장에서의 제품 경쟁력을 한층 높일 수 있는 효과가 있다.According to the SOI semiconductor device and the manufacturing method of the present invention configured as described above, the advantages of the SOI semiconductor device (fast operation characteristics of the integrated circuit device due to the latch-up and reduction of parasitic capacitance, increase in integration due to the improvement of the short channel effect and With excellent device isolation characteristics, etc., the ESD protection characteristics are improved, so that semiconductor devices with excellent reliability and performance can be provided to enhance product competitiveness in the market.
Claims (6)
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| KR1019980047107A KR100282523B1 (en) | 1998-11-04 | 1998-11-04 | SOHI semiconductor device with improved electrostatic discharge protection and manufacturing method |
| US09/257,299 US6063652A (en) | 1998-11-04 | 1999-02-25 | Silicon-on-insulator semiconductor device improving electrostatic discharge protection capability and fabrication method thereof |
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| KR1019980047107A KR100282523B1 (en) | 1998-11-04 | 1998-11-04 | SOHI semiconductor device with improved electrostatic discharge protection and manufacturing method |
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| US6150697A (en) * | 1998-04-30 | 2000-11-21 | Denso Corporation | Semiconductor apparatus having high withstand voltage |
| US6476445B1 (en) * | 1999-04-30 | 2002-11-05 | International Business Machines Corporation | Method and structures for dual depth oxygen layers in silicon-on-insulator processes |
| US6333532B1 (en) * | 1999-07-16 | 2001-12-25 | International Business Machines Corporation | Patterned SOI regions in semiconductor chips |
| JP4202563B2 (en) * | 1999-11-18 | 2008-12-24 | 株式会社東芝 | Semiconductor device |
| US6166420A (en) * | 2000-03-16 | 2000-12-26 | International Business Machines Corporation | Method and structure of high and low K buried oxide for SoI technology |
| US6787422B2 (en) | 2001-01-08 | 2004-09-07 | Chartered Semiconductor Manufacturing Ltd. | Method of body contact for SOI mosfet |
| US6589823B1 (en) * | 2001-02-22 | 2003-07-08 | Advanced Micro Devices, Inc. | Silicon-on-insulator (SOI)electrostatic discharge (ESD) protection device with backside contact plug |
| US6835983B2 (en) * | 2002-10-25 | 2004-12-28 | International Business Machines Corporation | Silicon-on-insulator (SOI) integrated circuit (IC) chip with the silicon layers consisting of regions of different thickness |
| US7173309B2 (en) * | 2003-04-29 | 2007-02-06 | Via Technologies Inc. | SOI single crystalline chip structure with multi-thickness silicon layer |
| JP4167565B2 (en) * | 2003-07-31 | 2008-10-15 | 株式会社東芝 | Method for manufacturing partial SOI substrate |
| US7235433B2 (en) * | 2004-11-01 | 2007-06-26 | Advanced Micro Devices, Inc. | Silicon-on-insulator semiconductor device with silicon layers having different crystal orientations and method of forming the silicon-on-insulator semiconductor device |
| US7666721B2 (en) * | 2006-03-15 | 2010-02-23 | International Business Machines Corporation | SOI substrates and SOI devices, and methods for forming the same |
| US20080128797A1 (en) * | 2006-11-30 | 2008-06-05 | International Business Machines Corporation | Structure and method for multiple height finfet devices |
| US7985633B2 (en) * | 2007-10-30 | 2011-07-26 | International Business Machines Corporation | Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors |
| US7956415B2 (en) * | 2008-06-05 | 2011-06-07 | International Business Machines Corporation | SOI transistor having a carrier recombination structure in a body |
| US9324792B1 (en) | 2015-03-31 | 2016-04-26 | International Business Machines Corporation | FinFET including varied fin height |
| US10748934B2 (en) * | 2018-08-28 | 2020-08-18 | Qualcomm Incorporated | Silicon on insulator with multiple semiconductor thicknesses using layer transfer |
| CN111129054B (en) * | 2019-12-23 | 2023-09-05 | 上海集成电路研发中心有限公司 | CMOS image sensor structure and manufacturing method |
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| US5773326A (en) * | 1996-09-19 | 1998-06-30 | Motorola, Inc. | Method of making an SOI integrated circuit with ESD protection |
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