KR20000030972A - Method for forming contact in semiconductor device - Google Patents
Method for forming contact in semiconductor device Download PDFInfo
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- KR20000030972A KR20000030972A KR1019980045880A KR19980045880A KR20000030972A KR 20000030972 A KR20000030972 A KR 20000030972A KR 1019980045880 A KR1019980045880 A KR 1019980045880A KR 19980045880 A KR19980045880 A KR 19980045880A KR 20000030972 A KR20000030972 A KR 20000030972A
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 150000004767 nitrides Chemical class 0.000 claims abstract description 30
- 239000010410 layer Substances 0.000 claims abstract description 29
- 238000005530 etching Methods 0.000 claims abstract description 13
- 239000007789 gas Substances 0.000 claims abstract description 10
- 125000006850 spacer group Chemical group 0.000 claims abstract description 10
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 239000011229 interlayer Substances 0.000 claims abstract description 5
- 229910052786 argon Inorganic materials 0.000 claims abstract description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 4
- 238000009832 plasma treatment Methods 0.000 claims description 8
- 239000006227 byproduct Substances 0.000 abstract description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 abstract 1
- 238000005507 spraying Methods 0.000 abstract 1
- 230000004888 barrier function Effects 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체장치의 콘택 형성방법에 관한 것으로, 보다 상세하게는 비트라인 접속을 위한 콘택홀의 형성시 질화막을 C-플라즈마 처리를 함으로써 식각 중단(etch stop) 현상과 질화막 배리어 파괴를 방지할 수 있는 반도체장치의 콘택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact in a semiconductor device, and more particularly, by performing C-plasma treatment on a nitride film when forming a contact hole for a bit line connection, an etch stop phenomenon and a nitride barrier barrier can be prevented. A method for forming a contact in a semiconductor device.
반도체장치가 고집적화 됨에 따라 미세선폭의 구현 기술은 반도체장치 제작에 필수적인 사항이 되고 있다. 더욱이 여러층의 도전층을 이용하는 메모리 장치에서는 다른 도전층과의 브리지(bridge)가 없이 미세한 라인과 라인을 연결해주는 콘택홀의 형성기술이 반도체장치 제작의 결정적인 요인으로 그 중요성이 높아지고 있는 실정이다.As semiconductor devices have been highly integrated, the technology for implementing fine line widths has become an essential item for manufacturing semiconductor devices. Furthermore, in a memory device using multiple conductive layers, a technology for forming a contact hole that connects fine lines and lines without bridges with other conductive layers is a critical factor in the fabrication of semiconductor devices.
과거 반도체장치의 제조공정중 비트라인 접속을 위한 콘택홀의 형성방법은 도 1에 나타낸 바와 같이 절연층을 형성하고 상부에 콘택홀 형성을 위한 감광막을 패터닝한 후 직접 건식해내는 직접 콘택(Direct Contact) 방식을 취하여 왔으나, 고집적화에 따른 콘택홀의 크기 감소와 다층 중첩 마진(Poly Overlay Margin)에 의해 0.24μm 이하급 소자에서는 사용이 불가능하게 되었다.In the past, a method of forming a contact hole for a bit line connection during the manufacturing process of a semiconductor device, as shown in FIG. 1, forms a dielectric layer and directly drys the photoresist film for patterning a contact hole on the upper part, and then directly dryes it. However, due to the high integration and reduced size of contact holes and the multi-layer overlay margin, it has become impossible to use in devices of 0.24μm or less.
이러한 문제점을 극복하기 위해 현재는 질화물 스페이서를 이용하는 측벽 산화물 스페이서 자가정렬 콘택(Sidewall Oxide Spacer self-align CONtack; SOSCON) 방식(도 2)이나 질화물 장벽을 이용한 자가정렬 콘택(Nitride Barrier Self-Align Contack; Nitride Barrier SAC) 형성방법(도 3)이 사용되고 있다.In order to overcome this problem, a sidewall oxide spacer self-aligned contact (SOSCON) method using a nitride spacer (FIG. 2) or a self-aligned contact using a nitride barrier (Nitride Barrier Self-Align Contack); Nitride Barrier SAC) formation method (FIG. 3) is used.
그러나 이들 방법은 콘택홀을 형성하기 위해 플루오르계 가스하에서 진행하는 콘택 식각 공정에서 산화물의 건식 식각 도중 질화막이 드러날 경우 형성되는 부산물로 인하여 식각의 진행이 중단되는 식각중단(etch stop) 현상과, 건식식각중 질화막이 식각되거나 깨어짐으로써 장벽으로서의 역할을 더 이상 하지 못하게 되는 질화막 파괴(nitride broken) 현상이 나타나게 된다.However, these methods use an etch stop phenomenon in which the progress of etching is stopped due to by-products formed when a nitride film is exposed during dry etching of an oxide in a contact etching process performed under a fluorine-based gas to form a contact hole. As the nitride film is etched or broken during etching, a nitride broken phenomenon occurs, which can no longer serve as a barrier.
따라서, 이러한 문제점을 해결하기위해 식각 공정의 최적화 및 장벽층의 변경 등에 관한 활발한 연구가 진행되고 있는 중이다.Therefore, in order to solve this problem, active researches on the optimization of the etching process and the change of the barrier layer are being conducted.
따라서, 본 발명이 이루고자 하는 기술적 과제는 콘택 식각 공정에서 질화막이 드러날 경우 형성되는 부산물에 의해 식각의 진행이 중단되는 식각중단 현상과 질화물 파괴현상을 방지할 수 있는 반도체장치의 콘택형성방법을 제공하는 데에 있다.Accordingly, a technical object of the present invention is to provide a method for forming a contact of a semiconductor device which can prevent the etch stop phenomenon and the nitride breakdown phenomenon in which the etching process is stopped by the by-product formed when the nitride film is exposed in the contact etching process. There is.
도 1 은 종래의 직접콘택 방식을 보여주는 단면도이다.1 is a cross-sectional view showing a conventional direct contact method.
도 2 는 종래의 SOSCON 방식을 보여주는 단면도이다.2 is a cross-sectional view showing a conventional SOSCON method.
도 3 은 종래의 질화물 베리어 SAC 방식을 보여주는 단면도이다.3 is a cross-sectional view showing a conventional nitride barrier SAC method.
도 4 내지 도 6는 본 발명의 실시예에 따른 콘택 형성방법을 구현하기 위한 공정순서를 나타낸 단면도 들이다.4 to 6 are cross-sectional views illustrating a process sequence for implementing a contact forming method according to an embodiment of the present invention.
도 7 및 도 8는 본 발명의 또 다른 실시예에 따른 콘택 형성방법을 구현하기 위한 공정순서를 나타낸 단면도 들이다.7 and 8 are cross-sectional views showing a process sequence for implementing a contact forming method according to another embodiment of the present invention.
* 도면 중의 주요 부분에 대한 부호설명** Explanation of Codes on Major Parts of Drawings *
10 : 반도체기판 20 : 제1 도전층10: semiconductor substrate 20: first conductive layer
30 : 산화막 40 : 산화막 스페이서30: oxide film 40: oxide film spacer
42 : 질화막 스페이서 45 : C-Si층42 nitride film spacer 45 C-Si layer
50 : 아크층 60 : 완충 산화막50 arc layer 60 buffer oxide film
70 : 질화막 75 : C-Si층70 nitride film 75 C-Si layer
80 : 절연층80: insulation layer
상기 기술적 과제를 달성하기 위한 본 발명에 따르는 콘택형성방법은 비트라인 접속을 위한 콘택홀의 형성에 있어서, 반도체 기판 상에 게이트전극과 질화막 스페이서를 형성하는 제 1 단계: 질화막을 C-플라즈마 처리하여 질화막 상부에 C-Si 층을 형성시키는 제 2 단계; 및 층간절연막을 증착하고, 콘택 마스크, 콘택 식각 공정을 진행하여 콘택홀을 형성시키는 제 3 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a contact hole for a bit line connection, comprising: forming a gate electrode and a nitride spacer on a semiconductor substrate: a nitride film by C-plasma treatment of the nitride layer Forming a C-Si layer on top; And a third step of depositing an interlayer insulating layer and forming a contact hole by performing a contact mask and a contact etching process.
본 발명의 콘택형성방법에서 C-플라즈마 처리는 CHF3또는 CF4가스를 이용하여 질소 또는 아르곤 가스하에서 실시하는 것이 바람직하다.In the contact forming method of the present invention, the C-plasma treatment is preferably performed under nitrogen or argon gas using CHF 3 or CF 4 gas.
본 발명의 반도체 장치의 콘택형성방법에는 제 1 단계에서 질화막 스페이서 대신에 산화막 스페이서를 형성시킨 다음, 완충산화막과 질화막을 웨이퍼 전면에 증착하는 단계를 추가로 포함시킬 수 있다.The contact forming method of the semiconductor device of the present invention may further include the step of forming an oxide spacer instead of the nitride spacer in the first step, and then depositing a buffer oxide and a nitride on the entire surface of the wafer.
이하 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다.Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
도 4 내지 도 6 은 본 발명의 실시예에 따른 콘택형성방법을 구현하기 위한 공정 순서를 나타낸 단면도이다.4 to 6 are cross-sectional views illustrating a process sequence for implementing a contact forming method according to an embodiment of the present invention.
먼저, 도 4 는 반도체 기판(10) 상에 제1 도전층(20)을 형성한 후, 웨이퍼 전면에 산화막(30)을 증착하고 이를 감광막이 없는 상태에서 건식식각하여 제1 도전층(20) 측면에 질화막 스페이서(42)를 형성한 상태를 도시하고 있다.First, FIG. 4 illustrates that after forming the first conductive layer 20 on the semiconductor substrate 10, the oxide layer 30 is deposited on the entire surface of the wafer and dry-etched in the absence of the photosensitive layer to form the first conductive layer 20. The state where the nitride film spacer 42 was formed in the side surface is shown.
그 다음, 도 5와 같이 CHF3또는 CF4가스를 사용하여 C-플라즈마 처리하여 질화막 스페이서(42) 상부에 C-Si 층(45)을 형성시킨다. 이 때, ICP 방식의 TCP 장비를 사용하여 10~20 mTorr 의 압력으로 질소나 아르곤 기체하에서 실시하였다.Next, as shown in FIG. 5, C-plasma treatment is performed using CHF 3 or CF 4 gas to form a C-Si layer 45 on the nitride spacer 42. At this time, it was carried out under nitrogen or argon gas at a pressure of 10-20 mTorr using TCP equipment of the ICP method.
그리고 나서, 도 6에서와 같이 워드라인과 비트라인이 형성되는 층간절연막(80)을 형성한 후 감광막을 웨이퍼 전면에 도포하여 패턴닝하고 건식식각하여 콘택홀을 형성시킨다.Then, as shown in FIG. 6, after forming the interlayer insulating film 80 in which the word line and the bit line are formed, a photoresist is applied to the entire surface of the wafer to be patterned and dry etched to form contact holes.
도 7 및 도 8는 본 발명의 또 다른 실시예에 따른 콘택형성방법을 구현하기 위한 공정 순서를 나타낸 단면도이다.7 and 8 are cross-sectional views showing a process sequence for implementing a contact forming method according to another embodiment of the present invention.
먼저, 도 7 는 반도체 기판(10) 상에 제1 도전층(20)을 형성한 후, 웨이퍼 전면에 산화막(30)을 증착하고 이를 감광막이 없는 상태에서 건식식각하여 제1 도전층(20) 측면에 스페이서(40)를 형성한 상태를 도시하고 있다.First, FIG. 7 illustrates that after forming the first conductive layer 20 on the semiconductor substrate 10, the oxide layer 30 is deposited on the entire surface of the wafer and dry-etched in the absence of the photosensitive layer to form the first conductive layer 20. The state which formed the spacer 40 in the side surface is shown.
그 다음, 도 8와 같이 완충 산화막(buffer oxide)(60)을 웨이퍼 전면에 증착하고, 연속적으로 그 상부에 질화막(70)을 증착한다. 그리고 나서, CHF3또는 CF4가스를 사용하여 ECR 식각 장치로 C-플라즈마 처리하여 질화막(70) 상부에 C-Si 층(75)을 형성시킨다.Next, as shown in FIG. 8, a buffer oxide 60 is deposited on the entire surface of the wafer, and the nitride layer 70 is successively deposited thereon. The C-Si layer 75 is then formed on the nitride film 70 by C-plasma treatment with an ECR etching apparatus using CHF 3 or CF 4 gas.
상기 공정이 완료된 다음, 층간절연막(80)을 증착하고, 콘택 마스크, 콘택 식각 공정을 진행하여 콘택홀을 형성하여 도 3 에서와 같은 콘택홀을 형성한다.After the process is completed, the interlayer insulating film 80 is deposited, and a contact hole is formed by performing a contact mask and a contact etching process to form a contact hole as shown in FIG. 3.
본 발명의 콘택형성방법은 상기 실시예에만 한정되는 것은 아니며 본 발명이 속하는 분야의 통상의 지식을 가진자라면 본 발명의 구성 및 특징에 따라 질화막을 이용하는 콘택 형성방법에는 본 발명을 쉽게 적용할 수 있을 것이다.The contact forming method of the present invention is not limited to the above embodiments, and those skilled in the art can easily apply the present invention to a contact forming method using a nitride film according to the configuration and features of the present invention. There will be.
본 발명에 따르면, 질화막을 C-플라즈마 처리함으로써 질화막이 손상되고 식각중단되는 형상을 억제시킴으로써 소자의 워드라인과 비트라인간의 브리지가 생기지 않고 안정적이로 양호한 비트라인 접속용 콘택홀을 형성할 수 있어 소자의 특성 개선 및 수율을 증가시킬 수 있다.According to the present invention, C-plasma treatment of the nitride film suppresses the shape of the nitride film being damaged and etched off, thereby making it possible to form a stable good contact hole for the bit line without forming a bridge between the word line and the bit line of the device. It is possible to improve the characteristics and yield of the device.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980045880A KR20000030972A (en) | 1998-10-29 | 1998-10-29 | Method for forming contact in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980045880A KR20000030972A (en) | 1998-10-29 | 1998-10-29 | Method for forming contact in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000030972A true KR20000030972A (en) | 2000-06-05 |
Family
ID=19556189
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980045880A KR20000030972A (en) | 1998-10-29 | 1998-10-29 | Method for forming contact in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000030972A (en) |
-
1998
- 1998-10-29 KR KR1019980045880A patent/KR20000030972A/en not_active Application Discontinuation
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