KR20000030971A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR20000030971A
KR20000030971A KR1019980045825A KR19980045825A KR20000030971A KR 20000030971 A KR20000030971 A KR 20000030971A KR 1019980045825 A KR1019980045825 A KR 1019980045825A KR 19980045825 A KR19980045825 A KR 19980045825A KR 20000030971 A KR20000030971 A KR 20000030971A
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South Korea
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insulating film
forming
junction region
spacer
semiconductor substrate
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KR1019980045825A
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Korean (ko)
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김을락
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김영환
현대전자산업 주식회사
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Priority to KR1019980045825A priority Critical patent/KR20000030971A/en
Publication of KR20000030971A publication Critical patent/KR20000030971A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to improve the characteristic and the reliability of a semiconductor device by forming an insulating film spacer on the side wall of an insulating film to prevent an impurity from being injected into the insulating film. CONSTITUTION: A word line is formed on the upper portion of a semiconductor substrate(11) having an element isolation insulating film(13) by laminating a gate electrode and a mask insulating film. And, an impurity junction region(19) of low density is formed by injecting impurity ions into the semiconductor substrate. A first spacer insulating film(21) with a certain degree of thickness is formed on the upper portion of the entire surface, and an insulating film spacer is formed on the side wall of the word line as well as remaining the first spacer insulating film on the upper portion of the isolation insulating film by anisotropic-etching the first spacer insulating film with an isolation mask. An impurity junction region of an LDD structure is formed by forming an impurity junction region(27) of high density through a plug implant process for injecting impurity ions into the semiconductor substrate. Then, a semiconductor device is fabricated by forming a contact plug(29) contacted to the impurity junction region.

Description

반도체소자의 제조방법Manufacturing method of semiconductor device

본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 반도체 소자의 집적도가 고집적화되면서 기억소자에 사용되는 트랜지스터의 게이트 길이는 더 작아지고 기억소자간의 간격도 더 작아짐으로써 웰 농도를 상향조정하여 트랜지스터의 펀치 ( punch ) 도 막고 소자분리시 공핍층 ( depletion ) 폭을 줄여주어 작은 간격에서도 소자분리가 가능하도록 하는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, as the integration density of semiconductor devices is increased, the gate length of the transistors used in the memory device is smaller and the spacing between the memory devices is smaller, so that the well concentration is adjusted upward to punch the transistor. The present invention also relates to a technology that prevents punch and reduces the depletion width during device separation so that device separation is possible even at small intervals.

그러나, 트랜지스터의 펀치도 막고 소자분리시 공핍층 폭을 줄여줌으로써 작은 간격에서도 소자분리가 가능하도록 하기 위한 웰의 농도로 인하여 기억소자의 전하축전용 캐패시터에 연결되는 폴리3콘택과 엔형 불순물 접합영역 ( P3C / N-junction ) 의 동작전압에서의 누설전류가 크게 된다.However, due to the well concentration to prevent the punch of the transistor and reduce the depletion layer width at the time of device isolation, the poly3 contact and N-type impurity junction region connected to the charge storage capacitor of the memory device ( Leakage current at the operating voltage of P3C / N-junction) becomes large.

즉, 높아진 웰 농도로 인하여 엔/피 ( N/P ) 접합의 공핍층에 걸리는 필드가 커지면서 유발되는 결함으로 인한 누설전류가 증가된다.In other words, the increased well concentration increases the leakage current due to defects caused by a large field in the depletion layer of the N / P junction.

종래에는, 기억소자가 만들어지는 활성영역과 소자분리영역 포함한 모든 부분에 웰과 반대형인 P31 이온주입 ( 이하, "플러그 임플란트"라 함 ) 을 행하여 웰 농도를 줄이는 방법이다.Conventionally, P31 ion implantation (hereinafter referred to as " plug implant ") opposite to the well is applied to all the portions including the active region and the isolation region in which the memory element is made to reduce the well concentration.

다시말하면, 이를 위해 종래에는 기억소자가 만들어지는 모든 부분을 여는 셀 마스크를 사용하여 1차 스패이서 산화막을 건식식각하여 P3C / N-P2C / N-접합부분(si-bulk)이 드러나고 뒤이어 플러그 임플란트를 실시하였다.In other words, conventionally, the P3C / N-P2C / N-junction (si-bulk) is exposed by dry etching the primary spacer oxide using a cell mask that opens all parts where the memory device is made. Was carried out.

그러나, 이 경우 플러그 임플란트 공정시 에너지를 일정 정도 이상을 필요로 하고 있는데 소자분리가 이루어지는 소자분리절연막 밑부분의 웰 농도를 감소시킨다. 그리고, 소자분리절연막 두께가 가장 두꺼운 부분은 영향이 없다고 하더라고 가장자리 부분의 두께가 가장 두꺼운 부분에 비해 반정도밖에 되질않아 이부분은 플러그 임플란트 공정시 거의 엔형 접합에 가깝게 특성이 바뀐다.However, in this case, the plug implant process requires more than a certain amount of energy, which reduces the well concentration at the bottom of the isolation layer where device isolation occurs. Although the thickest part of the device isolation insulating film has no effect, it is only about half the thickness of the thickest part of the edge, so that the part is almost close to the Y-type junction during the plug implant process.

그로인하여, 소자분리가 이루어지는 부분의 총 간격중 1/3 정도는 작아질 가능성이 있고 이것에 기인하여 기억소자간의 소자분리가 이루어지지않고 누설전류가 발생함으로써 반도체소자의 전류특성을 저하시키고 그에 따른 반도체소자의 특성 및 신뢰성을 저하시키는 문제점이 있다.As a result, about one third of the total spacing of the device isolation parts may become small, and as a result, leakage current occurs without device separation between memory devices, thereby lowering the current characteristics of the semiconductor device. There is a problem of lowering the characteristics and reliability of the semiconductor device.

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 플러그 임플라트 공정시 소자분리절연막에 불순물이 주입되는 현상을 방지하기 위해 상부에 소자분리절연막 상부에 절연막을 형성하거나 그 측벽에 절연막 스패이서를 형성함으로써 반도체소자의 전류특성을 향상시켜 그에 따른 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법을 제공하는데 그 목적이 있다.In order to solve the above problems of the prior art, an insulating film is formed on the side of the device isolation insulating film or an insulating film spacer on the sidewall of the device isolation insulating film to prevent impurities from being injected into the device isolation insulating film during the plug implant process. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can improve the current characteristics of the semiconductor device, thereby improving the characteristics and reliability of the semiconductor device.

도 1a 내지 도 1e 는 본 발명의 제1실시예에 따른 반도체소자의 제조방법을 도시한 단면도.1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

도 2a 내지 도 2d 는 본 발명의 제2실시예에 따른 반도체소자의 제조방법을 도시한 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

<도면의 주요부분에 대한 부호 설명><Description of Signs of Major Parts of Drawings>

11,31 : 반도체기판 13,33 : 소자분리절연막11,31: semiconductor substrate 13,33: device isolation insulating film

15,35 : 게이트전극 17,37 : 마스크산화막15,35 gate electrode 17,37 mask oxide film

19,39 : 저농도의 불순물 접합영역, 캐패시터 연결용 엔형 접합19,39: Low concentration impurity junction region, en-type junction for capacitor connection

21,41 : 1차 스패이서 산화막 25 : 감광막패턴21,41: primary spacer oxide film 25: photoresist pattern

27,45 : 고농도의 불순물 접합영역, 플러그 임플란트 엔형 접합27,45: high concentration impurity junction region, plug implant en-type junction

29,47 : 비트라인 및 캐패시터 콘택플러그29,47: Bitline and Capacitor Contact Plug

43 : 2차 스패이서 산화막43: secondary spacer oxide film

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 제조방법은,In order to achieve the above object, a semiconductor device manufacturing method according to the present invention,

소자분리절연막이 구비된 반도체기판 상부에 게이트전극과 마스크절연막을 적층구조로 워드라인을 형성하는 공정과,Forming a word line in a lamination structure with a gate electrode and a mask insulating film on the semiconductor substrate including the device isolation insulating film;

상기 반도체기판에 불순물을 이온주입하여 저농도의 불순물 접합영역을 형성하는 공정과,Forming a low concentration impurity junction region by implanting impurities into the semiconductor substrate;

전체표면상부에 1차 스패이서 절연막을 일정두께 형성하는 공정과,Forming a primary spacer insulating film on the entire surface of the substrate;

상기 1차 스패이서 절연막을 소자분리마스크를 이용하여 이방성식각함으로써 상기 소자분리절연막 상부에 1차 스패이서 절연막을 남기는 동시에 워드라인 측벽에 절연막 스패이서를 형성하는 공정과,Anisotropically etching the primary spacer insulating film using a device isolation mask to form an insulating film spacer on a word line sidewall while leaving the primary spacer insulating film on the device isolation insulating film;

상기 반도체기판에 불순물 이온주입하는 플러그 임플란트 공정으로 고농도의 불순물 접합영역을 형성하여 LDD 구조의 불순물 접합영역을 형성하는 공정과,Forming an impurity junction region having an LDD structure by forming a high concentration impurity junction region by a plug implant process implanting impurity ions into the semiconductor substrate;

상기 불순물 접합영역에 접속되는 콘택플러그를 형성하는 공정을 포함하는 것을 특징으로 한다.And forming a contact plug connected to the impurity junction region.

이상의 목적을 달성하기 위한 본 발명의 원리는,The principle of the present invention for achieving the above object,

P3C / 엔형 접합의 누설전류를 최소화하기위해 접합의 바닥부분만 웰 농도를 낮추어주는 방법을 고안해 보았다. 즉, 셀 트랜지스터의 채널 ( channel ) 부분과 소자분리가 이루어지는 소자분리절연막 밑부분의 웰 농도는 그대로 유지시켜 주면서 기억소자가 만들어지는 부분의 활성영역 지역중 게이트가 형성되는 부분을 제외한 부분, 즉 P3C / 엔형접합 및 P2C / 엔형 접합이 형성되는 부분에만 추가적으로 웰과 반대형의 불순물인 P31 을 이온주입하여, 다시말하면 플러그 임플란트하여 웰 농도를 줄이는 것이다.In order to minimize the leakage current of the P3C / EN junction, we designed a method to reduce the well concentration only at the bottom of the junction. That is, while maintaining the well concentration of the channel portion of the cell transistor and the lower portion of the isolation layer where device isolation is performed, the portion of the active region of the region where the memory device is formed is excluded except for the gate formation portion, that is, P3C. Only the portion where the / en-type junction and the P2C / en-type junction are formed are ion-implanted with P31, an impurity opposite to the well, that is, a plug implant reduces the well concentration.

본 발명의 경우 플러그 임플란트 공정시 특히 소자분리가 이루어지고 있는 소자분리절연막 부분에 초기의 소자분리절연막, 즉 열산화막 이외에 1차 스패이서 산화막을 일정두께 이상으로 존재하고 그 위에 소자분리용 감광막패턴과 같은 감광막패턴을 만들어 주어 소자분리절연막의 밑부분까지 P31 이온이 들어가지 않도록 하는 방법이다.In the present invention, in the plug implant process, an element isolation insulating film, ie, a thermal spacer film, has a primary spacer oxide film more than a predetermined thickness in a portion of the device isolation insulating film, in which device isolation is performed, and a photoresist pattern for device isolation. By making the same photoresist layer pattern, the P31 ion is prevented from entering the bottom of the isolation layer.

그리고, 소자분리절연막의 하부로 불순물이 이온주입되는 현상을 방지하기 위하여 상기 1차 스패이서 산화막의 측벽에 2차 스패이서 산화막을 형성하여줌으로써 후속공정으로 실시되는 플러그 임플란트 공정의 공정마진을 향상시킬 수 있고 그에 따른 반도체소자의 소자분리 특성을 향상시켜 반도체소자의 전류특성을 향상시킬 수 있도록 하는 것이다.In addition, by forming a secondary spacer oxide film on the sidewall of the primary spacer oxide film in order to prevent the implantation of impurities into the lower portion of the device isolation insulating film, the process margin of the plug implant process performed in the subsequent process may be improved. It is possible to improve the current characteristics of the semiconductor device by improving the device isolation characteristics of the semiconductor device accordingly.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1e 는 본 발명의 제1실시예에 따른 반도체소자의 제조방법을 도시한 단면도이다.1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

먼저, 반도체기판(11) 상부에 소자분리용 마스크를 사용하여 소자분리가 가능하도록 특정지역에 소자분리막(130을 형성한다.First, a device isolation layer 130 is formed in a specific region so that device isolation is possible by using a device isolation mask on the semiconductor substrate 11.

그리고 게이트전극(15)을 형성하되, 마스크산화막(17)이 상부에 구비하여 워드라인을 형성한다.A gate electrode 15 is formed, and a mask oxide film 17 is provided on the top to form a word line.

그 다음에, P2C / 엔형 접합 및 P3C / N-접합을 형성하기 위해 LDD 용 엔형 불순물 접합영역(19)을 형성한다. (도 1a)Then, the N-type impurity junction region 19 for LDD is formed to form a P2C / En-type junction and a P3C / N-junction. (FIG. 1A)

그리고, 워드라인과 전체표면상부에 1차 스패이서 산화막(21)을 충분한 두께로 형성한다. 이는 후속공정으로 형성될 콘택플러그를 형성하기 위한 것이다. (도 1b)Then, the primary spacer oxide film 21 is formed to a sufficient thickness on the word line and the entire surface. This is for forming a contact plug to be formed in a subsequent process. (FIG. 1B)

그 다음에, 상기 1차 스패이서 산화막(23) 상부에 제1감광막패턴(25)을 형성한다. 이때, 상기 제1감광막패턴(25)은 상기 소자분리용 마스크를 이용하여 형성한다. (도 1c)Next, a first photosensitive film pattern 25 is formed on the primary spacer oxide film 23. In this case, the first photoresist layer pattern 25 is formed using the device isolation mask. (FIG. 1C)

그리고, 상기 제1감광막패턴(25)을 마스크로하여 상기 1차 스패이서 산화막(23)을 식각함으로써 P2C / N-접합 및 P3C / N-접합이 형성될 부분이 드러난다. (도 1d)The primary spacer oxide layer 23 is etched using the first photoresist pattern 25 as a mask to reveal a portion where a P2C / N-junction and a P3C / N-junction are to be formed. (FIG. 1D)

그 다음에, 상기 플러그 임플라트 공정으로 상기 반도체기판(11)의 불순물 접합영역(19)에 엔형 불순물을 이온주입함으로써 고농도의 엔형 불순물 접합영역(27)을 형성한다.Subsequently, a high concentration of the yen-type impurity junction region 27 is formed by ion implantation of the yen-type impurity into the impurity junction region 19 of the semiconductor substrate 11 by the plug implant process.

여기서, 상기 플러그 임플란트 공정은 P2C / N-접합 및 P3C / N-접합이 형성된 부분에 추가적으로 P31 이 이온주입되면서 기 형성된 N-웰 및 P-웰의 P-N 접합의 공핍층이 이루어지는 P-웰 부분이 추가로 이온주입되어 카운터-도핑 ( counter-doping ) 이 이루어지면서 웰 농도가 낮아지고 주어진 역방향 바이어스에 의하여 P-N 접합의 공핍층에 전기장 ( Electric-field ) 이 줄어들면서 접합의 누설전류를 감소될 수 있다.Herein, the plug implant process includes a P-well portion in which a depletion layer of a PN junction of an N-well and a P-well formed as P31 is ion-implanted in addition to a P2C / N-junction and a P3C / N-junction is formed. In addition, ion-implantation results in a well-lower concentration as the counter-doping is performed, and a leakage current at the junction can be reduced as the electric field is reduced in the depletion layer of the PN junction by a given reverse bias. .

이때, 소자분리가 이루어지는 부분은 제1감광막 패턴(25)과 1차 스패이서 산화막(23)이 그대로 존재한다. 그래서 플러그 임플란트 공정의 에너지는 순수하게 접합 누설전류를 최소화하는 것에 가장 적합하게 조절하고, 소자분리가 이루어지는 소자분리절연막의 밑부분에는 플러그 임플란트 공정의 에너지로 진행될 때 이온주입이 거의 차단되기 때문에 기억소자의 소자간 분리에 영향을 주지는 않는다.In this case, the first photosensitive film pattern 25 and the primary spacer oxide film 23 are present as they are in the device separation. Therefore, the energy of the plug implant process is best adjusted to minimize the junction leakage current purely, and since the ion implantation is almost blocked at the bottom of the device isolation insulating film where the device isolation is performed, the ion implantation is blocked. It does not affect the isolation between devices.

후속공정으로, 상기 불순물 접합영역(19,27)에 접속되는 비트라인 및 캐패시터 콘택플러그(29)를 형성한다. (도 1e)In a subsequent step, bit lines and capacitor contact plugs 29 connected to the impurity junction regions 19 and 27 are formed. (FIG. 1E)

도 2a 내지 도 2d 는 본 발명의 제2실시예에 따른 반도체소자의 제조방법을 도시한 단면도이다.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

먼저, 상기 제1실시예의 도 1d 까지와 같이 반도체기판(31) 상부에 소자분리절연막(33), 게이트전극(35), 마스크산화막(37)을 형성하고, 상기 게이트전극(35) 및 마스크 산화막(37)을 패터닝하여 워드라인을 형성한 다음, 전체표면상부에 1차 스패이서 산화막(41)을 일정두께 형성하고 소자분리용 마스크를 이용한 식각공정으로 이방성식각하여 소자분리절연막 상부에 1차 스패이서 산화막(41)을 남기는 동시에 상기 워드라인의 측벽에 스페이서를 형성한다. 그리고, 상기 반도체기판(19)에 엔형 불순물을 주입하여 엔형 접합(39)을 형성한다.First, as shown in FIG. 1D of the first embodiment, an isolation layer 33, a gate electrode 35, and a mask oxide film 37 are formed on the semiconductor substrate 31, and the gate electrode 35 and the mask oxide film are formed. (37) is formed to form a word line, and then a primary spacer oxide film 41 is formed on the entire surface at a constant thickness and anisotropically etched by an etching process using an element isolation mask to form a primary spar on the element isolation insulating film. A spacer is formed on the sidewalls of the word line while leaving the oxide film 41. The Y-type junction 39 is formed by injecting Y-type impurities into the semiconductor substrate 19.

그 다음에, 전체표면상부에 2차 스패이서 산화막(43)을 일정두께 형성한다. (도 2a)Then, a secondary spacer oxide film 43 is formed on the entire surface at a constant thickness. (FIG. 2A)

그리고, 상기 2차 스패이서 산화막(43)을 일정두께 이방성식각하여 상기 1차 스패이서 산화막(41)의 측벽에 2차 스패이서 산화막(43)으로 형성된 스패이서를 형성함으로써 1차 스페이서 산화막(41) 식각공정이 유발될 수 있는 정렬오차로 인하여 소자분리절연막(33)의 하부로 불순물이 유입되는 현상을 보상한다. (도 2b)The primary spacer oxide film 41 is formed by anisotropically etching the secondary spacer oxide film 43 by forming a spacer formed of the secondary spacer oxide film 43 on the sidewall of the primary spacer oxide film 41. Compensation for impurities flowing into the lower portion of the device isolation insulating layer 33 due to an alignment error that may cause an etching process. (FIG. 2B)

그 다음에, 상기 반도체기판(31) 상부의 구조물을 마스크로하여 플러그 임플란트 공정으로 상기 반도체기판(31) 고농도의 엔형 불순물을 주입하여 고농도의 엔형 불순물 접합영역(45)을 형성한다. (도 2c)Next, a high concentration of yen-type impurity junction region 45 is formed by implanting a high concentration of en-type impurities into the semiconductor substrate 31 by a plug implant process using the structure of the upper portion of the semiconductor substrate 31 as a mask. (FIG. 2C)

그리고, 상기 불순물 접합영역(39,45)에 접속되는 비트라인 및 캐패시터 콘택플러그(47)를 형성한다. (도 2d)Then, bit lines and capacitor contact plugs 47 connected to the impurity junction regions 39 and 45 are formed. (FIG. 2D)

상기한 바와같이 본 발명에 따른 반도체소자의 제조방법은, 플러그 임플란트 공정으로 기억소자의 접합 누설전류를 최소화할 수 있고, 기억소자의 소자분리 특성열화를 방지할 수 있으며 미스얼라인시 소자분리 특성열화를 방지함으로써 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 효과가 있다.As described above, the method of manufacturing a semiconductor device according to the present invention can minimize the junction leakage current of the memory device through a plug implant process, prevent deterioration of device isolation characteristics of the memory device, and prevent device misalignment during misalignment. By preventing deterioration, there is an effect that can improve the characteristics and reliability of the semiconductor device.

Claims (3)

소자분리절연막이 구비된 반도체기판 상부에 게이트전극과 마스크절연막의 적층구조로 워드라인을 형성하는 공정과,Forming a word line in a stacked structure of a gate electrode and a mask insulating film on the semiconductor substrate including the device isolation insulating film; 상기 반도체기판에 불순물을 이온주입하여 저농도의 불순물 접합영역을 형성하는 공정과,Forming a low concentration impurity junction region by implanting impurities into the semiconductor substrate; 전체표면상부에 1차 스패이서 절연막을 일정두께 형성하는 공정과,Forming a primary spacer insulating film on the entire surface of the substrate; 상기 1차 스패이서 절연막을 소자분리마스크를 이용하여 이방성 식각함으로써 상기 소자분리절연막 상부에 1차 스패이서 절연막을 남기는 동시에 워드라인 측벽에 절연막 스패이서를 형성하는 공정과,Anisotropically etching the primary spacer insulating film using a device isolation mask to form an insulating film spacer on a word line sidewall while leaving the primary spacer insulating film on the device isolation insulating film; 상기 반도체기판에 불순물 이온주입하는 플러그 임플란트 공정으로 고농도의 불순물 접합영역을 형성하여 LDD 구조의 불순물 접합영역을 형성하는 공정과,Forming an impurity junction region having an LDD structure by forming a high concentration impurity junction region by a plug implant process implanting impurity ions into the semiconductor substrate; 상기 불순물 접합영역에 접속되는 콘택플러그를 형성하는 공정을 포함하는 반도체소자의 제조방법.And forming a contact plug connected to the impurity junction region. 제 1 항에 있어서,The method of claim 1, 상기 스패이서 절연막은 산화막으로 형성하는 것을 특징으로하는 반도체소자이 제조방법.And the spacer insulating film is formed of an oxide film. 제 1 항에 있어서,The method of claim 1, 상기 콘택플러그는 비트라인 콘택플러그와 캐패시터 콘택플러그인 것을 특징으로하는 반도체소자의 제조방법.And the contact plug is a bit line contact plug and a capacitor contact plug.
KR1019980045825A 1998-10-29 1998-10-29 Method for fabricating semiconductor device KR20000030971A (en)

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