KR20000027792A - Circuit for protecting electrostatic discharge - Google Patents
Circuit for protecting electrostatic discharge Download PDFInfo
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- KR20000027792A KR20000027792A KR1019980045819A KR19980045819A KR20000027792A KR 20000027792 A KR20000027792 A KR 20000027792A KR 1019980045819 A KR1019980045819 A KR 1019980045819A KR 19980045819 A KR19980045819 A KR 19980045819A KR 20000027792 A KR20000027792 A KR 20000027792A
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- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 230000036039 immunity Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 정전기 방지 회로에 관한 것으로, 특히 정전기 방전 ( electro static discharge, 이하 ESD 라 함 ) 의 내성을 증가시키기 위하여 데이타 출력핀인 DQ 핀 의 Vccq 를 입력핀에도 사용하여 ESD 핀-투-핀 ( ESD pin-to-pin ) 테스트 ( test ) 시 ESD 내성을 증가시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an antistatic circuit, and in particular, to increase the immunity of electrostatic discharge (ESD), Vccq of the DQ pin, which is a data output pin, is also used as an input pin. An ESD pin-to-pin test is a technique for increasing ESD immunity.
일반적으로 공지된 바와같이, 정전기 방전은 반도체 장치의 내부 회로를 파괴하는 주요 원인 중의 하나이다.As is generally known, electrostatic discharge is one of the main causes of breaking internal circuits of semiconductor devices.
예를들어, 패키지된 반도체 장치의 외부 핀을 통하여 인가된 정전기는 반도체 장치내의 다이오드 또는 트랜지스터에 인가되어 이들 소자의 기능을 파괴시키게된다.For example, static electricity applied through the external pins of a packaged semiconductor device may be applied to diodes or transistors in the semiconductor device to destroy the functionality of these devices.
즉, 다이오드의 P-N 접합사이에 인가되어 접합 스파이크를 발생시키거나, 트랜지스터의 게이트 절연막을 파괴시켜 게이트와 드레인 및 소오스를 단락시켜 상기 소자의 신뢰성에 큰 영향을 미치게 된다.That is, it is applied between the P-N junctions of the diodes to generate junction spikes, or destroy the gate insulating film of the transistor to short-circuit the gate, the drain, and the source, thereby greatly affecting the reliability of the device.
최근들어, 반도체 장치는 고집적화되고 그에따라 반도체 소자의 두께는 점점 더 얇아지고 있다.In recent years, semiconductor devices have been highly integrated, and accordingly, the thickness of semiconductor devices has become thinner and thinner.
이로 인하여, 최근의 반도체 장치는 정전기 방전에 의한 영향을 더욱 더 심하게 받고 있다.As a result, recent semiconductor devices are more severely affected by electrostatic discharge.
도 1 은 종래기술에 따른 ESD 보호회로의 구성을 도시한 개략도이다.1 is a schematic diagram showing the configuration of an ESD protection circuit according to the prior art.
먼저, DQ 핀인 제1핀(11)과 제2핀(13)에는 Vccq 와 연결된 풀-엎 ( pull-up ) 소자 ( PMOS )(도시안됨)와 Vssq 에 연결된 풀-다운 ( pull-down ) 소자 ( NMOS )(도시안됨)로 구성되고, 입력핀인 제3핀(15)과 제4핀(17)에는 Vcc 와 Vss 를 사용한다. 이때, Vcc 와 Vccq 는 연결되지 않는다.First, a pull-up device (PMOS) (not shown) connected to Vccq and a pull-down device connected to Vssq are provided on the first pin 11 and the second pin 13, which are DQ pins. (NMOS) (not shown), and Vcc and Vss are used for the third and fourth pins 15 and 17, which are input pins. At this time, Vcc and Vccq are not connected.
그리고, ESD 핀-투-핀 테스트는, 테스트를 하는 핀 이외의 핀들은 접지하여 테스트 핀에 전압을 인가하여 실시하는 것으로, 이 전류는 인접한 패드를 통하여 흐르게 되나 입력핀의 Vcc 와 패드의 Vccq 가 연결되어 있지 않으므로 제1핀(11)으로부터 흐르는 전류가 입력핀인 제3핀(15)과 제4핀(17)으로는 흐를 수 없다.In addition, the ESD pin-to-pin test is performed by applying a voltage to the test pin by grounding pins other than the test pin, and the current flows through the adjacent pad, but Vcc of the input pin and Vccq of the pad are Since it is not connected, the current flowing from the first pin 11 cannot flow to the third pin 15 and the fourth pin 17 which are input pins.
여기서, "19" 는 전압 인가시 전류흐름을 도시한 것이다.Here, "19" shows the current flow when voltage is applied.
상기한 바와같이 종래기술에 따른 ESD 방지회로는, ESD 핀-투-핀 테스트시 풀-엎 소자의 Vccq 가 제3핀(15) 및 제4핀(17)과 같은 입력핀에 연결되지 못해 입력핀으로 전류를 흘리지 못하고 인접된 패드에만 전류를 흘리기 때문에 보다 많은 전류의 분산이 어려워 고집적화에 따른 반도체소자의 ESD 특성 향상이 어려운 문제점이 있다.As described above, in the ESD protection circuit according to the related art, the Vccq of the pull-up device is not connected to an input pin such as the third pin 15 and the fourth pin 17 during the ESD pin-to-pin test. Since current does not flow through the pins and only the adjacent pads, it is difficult to distribute more currents, which makes it difficult to improve the ESD characteristics of semiconductor devices due to high integration.
본 발명은, 종래기술의 문제점을 해결하기 위하여, ESD 핀-투-핀 테스트시 풀-엎 소자의 Vccq 를 입력핀의 Vcc 에 연결함으로서 인접된 DQ 핀 뿐만아니라 입력핀에도 전류가 흐르도록 하여 ESD 내성을 향상시킬 수 있는 정전기 방지회로를 제공하는데 그 목적이 있다.The present invention, in order to solve the problems of the prior art, by connecting the Vccq of the pull-up device to the Vcc of the input pin during the ESD pin-to-pin test, the current flows to the input pin as well as the adjacent DQ pin ESD It is an object of the present invention to provide an antistatic circuit capable of improving resistance.
도 1 은 종래기술에 따른 정전기 방지 회로의 구성을 도시한 개략도.1 is a schematic diagram showing the configuration of an antistatic circuit according to the prior art;
도 2 는 본 발명에 따른 정전기 방지 회로의 구성을 도시한 개략도.2 is a schematic diagram showing a configuration of an antistatic circuit according to the present invention;
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11 : 제1핀(pin) 13 : 제2핀11: first pin 13: second pin
15 : 제3핀 17 : 제4핀15: third pin 17: fourth pin
19,21 : 전류흐름19,21: current flow
이상의 목적을 달성하기 위해 본 발명에 따른 정전기 방지 회로는,In order to achieve the above object, the antistatic circuit according to the present invention,
정전기 방지회로의 패일이 Vssq 에서 유발되는 경우의 정전기 방지회로에 있어서,In the antistatic circuit when the failure of the antistatic circuit is caused by Vssq,
Vccq 와 연결된 풀-엎 소자와, Vssq 에 연결된 풀-다운 소자로 구성된 DQ 핀과,A DQ pin consisting of a pull-up device connected to Vccq, a pull-down device connected to Vssq,
Vccq 와 연결된 풀-엎 소자와, Vss 에 연결된 풀-다운 소자로 구성된 입력핀으로 정전기 방지회로가 구성되되,An antistatic circuit consists of an input pin consisting of a pull-up device connected to Vccq and a pull-down device connected to Vss.
상기 Vccq 와 Vcc 가 상호 연결되어 상기 Vssq 에 전류가 적게 흐르도록 하는 것을 제1특징으로 한다.The first feature is that Vccq and Vcc are interconnected to allow a small current to flow in Vssq.
이상의 목적을 달성하기 위해 본 발명에 따른 정전기 방지 회로는,In order to achieve the above object, the antistatic circuit according to the present invention,
정전기 방지회로의 패일이 Vssq 에서 유발되는 경우의 정전기 방지회로에 있어서,In the antistatic circuit when the failure of the antistatic circuit is caused by Vssq,
Vccq 와 연결된 풀-엎 소자와, Vssq 에 연결된 풀-다운 소자로 구성된 DQ 핀과,A DQ pin consisting of a pull-up device connected to Vccq, a pull-down device connected to Vssq,
Vssq 와 연결된 풀-엎 소자와, Vss 에 연결된 풀-다운 소자로 구성된 입력핀으로 정전기 방지회로가 구성되되,An antistatic circuit consists of an input pin consisting of a pull-up device connected to Vssq and a pull-down device connected to Vss.
상기 Vssq 와 Vss 가 상호 연결되어 상기 Vccq 에 전류가 적게 흐르도록 하는 것을 제2특징으로한다.A second feature is that the Vssq and Vss are interconnected to allow a small current to flow in the Vccq.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2 는 본 발명의 실시예에 따라 ESD 핀-투-핀 테스트시 ESD 보호회로의 구성을 도시한 개략도로서, 정전기 방지회로의 패일 ( failure ) 이 Vssq 에서 유발되는 경우의 정전기 방지회로에서 두개의 DQ 핀과 두개의 입력핀을 예로하여 도시한 것이다.FIG. 2 is a schematic diagram showing the configuration of an ESD protection circuit during an ESD pin-to-pin test according to an embodiment of the present invention, in which an antistatic circuit in the case where a failure of the antistatic circuit is caused at Vssq is shown in FIG. DQ pin and two input pins are shown as an example.
먼저, DQ 핀인 제1핀(11)과 제2핀(13)에는 Vccq 와 연결된 풀-엎 ( pull-up ) 소자 ( PMOS )(도시안됨)와, Vssq 에 연결된 풀-다운 ( pull-down ) 소자 ( NMOS )(도시안됨)로 구성되고, 입력핀인 제3핀(15)과 제4핀(17)에는 Vcc 와 Vss 를 사용한다. 이때, 풀-엎 소자의 Vccq 와 입력핀의 Vcc 는 서로 연결된 구조로 형성되어 입력핀의 입력전원은 Vccq 가 된다.First, a pull-up device (PMOS) (not shown) connected to Vccq and a pull-down connected to Vssq are provided on the first pin 11 and the second pin 13, which are DQ pins. A device (NMOS) (not shown), and Vcc and Vss are used for the third pin 15 and the fourth pin 17, which are input pins. At this time, the Vccq of the pull-up device and the Vcc of the input pin are formed to be connected to each other so that the input power of the input pin becomes Vccq.
후속공정으로 ESD 핀-투-핀 테스트를 실시한다.Subsequent processes perform ESD pin-to-pin tests.
이때, 전류는 인접한 패드를 통하여 흐를 뿐아니라 입력핀의 Vcc 와 패드의 Vccq 가 연결되어 있으므로 제1핀(11)으로부터 흐르는 전류가 제2핀(13), 제3핀(15) 및 제4핀(17)으로 흐르게 된다.At this time, the current flows not only through the adjacent pads, but also because the Vcc of the input pin and the Vccq of the pad are connected, the current flowing from the first pin 11 flows through the second pin 13, the third pin 15, and the fourth pin. Flows to (17).
그리고, Vccq 쪽으로 많은 전류가 흐르게 되어 ESD 패일 ( failure ) 가 많이 생기게 되는 Vssq 쪽으로는 전류가 적게 흐르게 된다.And, much current flows toward Vccq, and less current flows toward Vssq, which causes many ESD failures.
여기서, "21" 는 전압 인가시 전류흐름을 도시한 것이다.Here, "21" shows the current flow when voltage is applied.
도시되진 않았으나, 본 발명의 다른 실시예는, 정전기 방지회로의 패일이 Vccq 에서 유발되는 경우의 정전기 방지회로에 있어서, 상기 제2도의 풀-다운 소자의 Vssq 와 입력핀의 Vss 는 서로 연결된 구조로 형성되어 입력핀의 입력전원은 Vssq 가 되는 것이다. 여기서, 상기 Vssq 는 풀-업 소자의 역할을 한다.Although not shown, in another embodiment of the present invention, in the antistatic circuit in which the failing of the antistatic circuit is caused by Vccq, Vssq of the pull-down device of FIG. 2 and Vss of the input pin are connected to each other. The input power of the input pin is formed to be Vssq. Here, Vssq serves as a pull-up device.
ESD 핀-투-핀 테스트시 전류는, 인접한 패드를 통하여 흐를 뿐아니라 입력핀의 Vss 와 패드의 Vssq 가 연결되어 있으므로 제1핀(11)으로부터 흐르는 전류가 제2핀(13), 제3핀(15) 및 제4핀(17)으로 흐르게 된다.In the ESD pin-to-pin test, the current flows not only through adjacent pads, but also the Vss of the input pin and the Vssq of the pad are connected so that the current flowing from the first pin 11 is applied to the second pin 13 and the third pin. 15 and the fourth pin 17.
그리고, Vssq 쪽으로 많은 전류가 흐르게 되어 ESD 패일 ( failure ) 가 많이 생기게 되는 Vccq 쪽으로는 전류가 적게 흐르게 된다.And, much current flows toward Vssq, and less current flows toward Vccq, which causes many ESD failures.
이상에서 상세히 기술한 바와 같이 본 발명은 반도체 장치의 내부 소자를 보호하기위한 정전기 방지 회로에 관한 것으로서, DQ 핀의 Vccq 와 입력핀의 Vcc 를 연결시켜 DQ 핀으로부터 입력핀으로 전류가 흐르도록 함으로써 ESD 패일을 많이 일으키는 Vssq 쪽으로 전류가 적게 흐르게 하여 ESD 내성을 향상시키고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 효과가 있다.As described in detail above, the present invention relates to an antistatic circuit for protecting an internal device of a semiconductor device. The present invention relates to a connection between Vccq of the DQ pin and Vcc of the input pin so that a current flows from the DQ pin to the input pin. The current flows toward the Vssq that causes a lot of failure, thereby improving the ESD resistance and thereby improving the characteristics and reliability of the semiconductor device.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980045819A KR20000027792A (en) | 1998-10-29 | 1998-10-29 | Circuit for protecting electrostatic discharge |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980045819A KR20000027792A (en) | 1998-10-29 | 1998-10-29 | Circuit for protecting electrostatic discharge |
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| KR20000027792A true KR20000027792A (en) | 2000-05-15 |
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| KR1019980045819A KR20000027792A (en) | 1998-10-29 | 1998-10-29 | Circuit for protecting electrostatic discharge |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7518898B2 (en) | 2005-01-10 | 2009-04-14 | Samsung Electronics Co., Ltd. | Semiconductor memory device with strengthened power and method of strengthening power of the same |
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1998
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7518898B2 (en) | 2005-01-10 | 2009-04-14 | Samsung Electronics Co., Ltd. | Semiconductor memory device with strengthened power and method of strengthening power of the same |
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