KR20000025858A - Method for etching polysilicon in step-like area of semiconductor device - Google Patents
Method for etching polysilicon in step-like area of semiconductor device Download PDFInfo
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- KR20000025858A KR20000025858A KR1019980043119A KR19980043119A KR20000025858A KR 20000025858 A KR20000025858 A KR 20000025858A KR 1019980043119 A KR1019980043119 A KR 1019980043119A KR 19980043119 A KR19980043119 A KR 19980043119A KR 20000025858 A KR20000025858 A KR 20000025858A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 58
- 238000000034 method Methods 0.000 title claims abstract description 30
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 30
- 238000005530 etching Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000009616 inductively coupled plasma Methods 0.000 claims abstract description 7
- 238000001020 plasma etching Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 abstract 2
- 150000004767 nitrides Chemical class 0.000 description 15
- 238000001312 dry etching Methods 0.000 description 6
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 5
- 229910021342 tungsten silicide Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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Abstract
Description
본 발명은 반도체 소자의 단차영역에서 다결정실리콘의 식각방법에 관한 것으로, 특히 플라즈마 식각후 단차영역의 측면부에 잔존하는 다결정실리콘을 등방성식각하거나 트랜스포머 커플드 플라즈마 소스(transformer coupled plasma source)를 이용하여 식각함으로써 단차영역의 측면부에 다결정실리콘을 모두 제거하여 이후의 공정에서 금속배선 등과 같은 도전성층과 쇼트(short)가 발생하는 것을 방지하는데 적당하도록 한 반도체 소자의 단차영역에서 다결정실리콘의 식각방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of etching polycrystalline silicon in a stepped region of a semiconductor device. In particular, the present invention relates to an isotropic etching of a polysilicon remaining on a side surface of a stepped region after plasma etching, or by using a transformer coupled plasma source. The present invention relates to a method for etching polycrystalline silicon in a stepped region of a semiconductor device, by removing all polycrystalline silicon at a side surface of the stepped region, thereby preventing occurrence of a short circuit with a conductive layer such as metal wiring in a subsequent process. .
일반적으로, 종래 반도체 소자의 단차영역에서 다결정실리콘의 식각방법은 ECR(electron cyclotron resonance) 플라즈마 소스를 이용하여 다결정실리콘을 식각하였으나 하부 구조의 형성으로 단차가 발생한 단차영역에서는 그 단차영역의 측면에 다결정실리콘이 잔존하게 된다. 이는 산화막측벽 등의 단차측면에 형성하는 구조의 형성법을 고려하면 당연한 결과이며, 종래에는 이와 같이 잔존하는 다결정실리콘을 제거하는 후속공정을 사용하지 않음으로써, 이후에 형성하는 배선 등의 도전성막과 쇼트(short)되어 반도체 소자를 사용할 수 없게 될 수 있으며, 이와 같은 종래 반도체 소자의 단차영역에서 다결정실리콘의 식각방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In general, the etching method of polysilicon in the stepped region of a semiconductor device is etched polycrystalline silicon using an electron cyclotron resonance (ECR) plasma source, but in the stepped region where the step is formed due to the formation of the underlying structure, the polycrystalline side of the stepped region Silicon remains. This is a natural result in consideration of the formation method of the structure formed on the side surface of the step such as the oxide film side wall, and conventionally, since the subsequent process of removing the remaining polycrystalline silicon is not used, the conductive film and the short such as the wiring formed thereafter are short. The semiconductor device may be shortened and the semiconductor device may not be used. Hereinafter, the etching method of the polysilicon in the stepped region of the conventional semiconductor device will be described in detail with reference to the accompanying drawings.
도1은 반도체 메모리의 공통 플래이트(common plate)를 형성하는 과정을 보인 반도체 소자의 단차영역에서 다결정실리콘의 식각방법의 일실시예도로서, 이에 도시한 바와 같이 고온저압산화막(1), 다결정실리콘(2), 텅스텐실리사이드(3) 적층구조의 상부에 고온저압산화막(4)을 증착하고, 상기 고온저압산화막(4)의 상부에 질화막(5)과 절연층인 다결정실리콘(6)을 순차적으로 증착하는 단계(도1a)와; 상기 다결정실리콘(6)과 질화막을 ECR 플라즈마 소스를 이용한 건식식각으로 식각하여 상기 고온저압산화막(4)의 상부면을 노출시키며, 그 고온저압산화막(4)의 측면에 질화막(5) 측벽을 형성하는 단계(도1b)로 구성된다.FIG. 1 is an embodiment of a method of etching polycrystalline silicon in a stepped region of a semiconductor device showing a process of forming a common plate of a semiconductor memory. As shown therein, a high temperature low pressure oxide film 1 and a polycrystalline silicon ( 2), the high temperature low pressure oxide film 4 is deposited on the tungsten silicide 3 stacked structure, and the nitride film 5 and the polysilicon 6, which is an insulating layer, are sequentially deposited on the high temperature low pressure oxide film 4, respectively. (Step 1a); The polysilicon 6 and the nitride film are etched by dry etching using an ECR plasma source to expose the upper surface of the high temperature low pressure oxide film 4, and a sidewall of the nitride film 5 is formed on the side surface of the high temperature low pressure oxide film 4. It consists of a step (Fig. 1B).
이하, 상기와 같은 종래 반도체 소자의 단차영역에서 다결정실리콘의 식각방법을 좀 더 상세히 설명한다.Hereinafter, a method of etching polycrystalline silicon in the stepped region of the conventional semiconductor device will be described in more detail.
먼저, 도1a에 도시한 바와 같이 고온저압산화막(1), 다결정실리콘(2), 텅스텐실리사이드(3)가 적층된 공통 플래이트 구조의 상부에 고온저압산화막(4)을 증착한다. 이때, 상기 고온저압산화막(4)은 상기 고온저압산화막(1), 다결정실리콘(2), 텅스텐실리사이드(3) 적층구조와 그 적층구조의 측면간에 단차가 발생하게 된다.First, as shown in FIG. 1A, the high temperature low pressure oxide film 4 is deposited on the common plate structure on which the high temperature low pressure oxide film 1, the polycrystalline silicon 2, and the tungsten silicide 3 are laminated. At this time, the high temperature low pressure oxide film 4 has a step between the high temperature low pressure oxide film 1, the polycrystalline silicon 2, and the tungsten silicide 3 stacked structure and the side surfaces of the stacked structure.
그 다음, 상기 단차영역이 발생된 고온저압산화막(4)의 상부전면에 질화막(5)과 절연층인 다결정실리콘(6)을 순차적으로 증착한다. 이때, 역시 상기 고온저압산화막(6)의 단차영역에 의해 단차가 발생하게 된다.Next, the nitride film 5 and the polysilicon 6 as an insulating layer are sequentially deposited on the upper surface of the high temperature low pressure oxide film 4 in which the stepped region is generated. At this time, the step is also generated by the step region of the high temperature low pressure oxide film (6).
그 다음, 도1b에 도시한 바와 같이 상기 다결정실리콘(6)과 질화막(5)을 건식식각하여 상기 고온저압산화막(4)의 단차영역 측면에 질화막(5) 측벽을 형성한다. 이때, 상기 건식식각은 ECR 플라즈마 소스를 이용한 건식식각이며, 이와 같은 식각공정으로 형성되는 질화막(5) 측벽의 측면에는 상기 다결정실리콘(6)이 잔존하게 된다.Next, as shown in FIG. 1B, the polysilicon 6 and the nitride film 5 are dry etched to form sidewalls of the nitride film 5 on the sidewall region of the high temperature low pressure oxide film 4. In this case, the dry etching is dry etching using an ECR plasma source, and the polysilicon 6 remains on the side surface of the nitride film 5 sidewall formed by the etching process.
이와 같이 다결정실리콘이 잔존하게 되면, 이는 이후의 커패시터 형성공정에서 커패시터 하부전극과 쇼트될 수 있으며, 이는 소자의 특성을 열화시키는 요소가된다.As such, when the polysilicon remains, it may be shorted with the capacitor lower electrode in a subsequent capacitor formation process, which becomes a factor deteriorating the characteristics of the device.
상기한 바와 같이 종래 반도체 소자의 단차영역에서 다결정실리콘의 식각방법은 단차가 형성된 영역의 상부에 증착된 다결정실리콘을 식각하는 과정에서 ECR 플라즈마 소스를 사용하는 건식식각으로 식각하여 단차영역의 측면부에 다결정실리콘이 잔존하게 되며, 이는 이후의 공정에서 다른 도전성막과의 쇼트를 유발하여 소자의 특성을 열화시키는 문제점이 있었다.As described above, the method of etching polycrystalline silicon in a stepped region of a conventional semiconductor device is etched by dry etching using an ECR plasma source in the process of etching polycrystalline silicon deposited on the top of the stepped region. Silicon remains, which causes a short with another conductive film in a subsequent process, thereby deteriorating the characteristics of the device.
이와 같은 문제점을 감안한 본 발명은 단차영역가 발생한 영역의 상부에 증착된 다결정실리콘을 식각하여 그 단차영역의 측면부에 그 다결정실리콘이 잔존하지 않도록 하는 반도체 소자의 단차영역에서 다결정실리콘의 식각방법을 제공함에 그 목적이 있다.In view of the above problems, the present invention provides a method of etching polycrystalline silicon in a stepped region of a semiconductor device in which a polysilicon deposited on top of a stepped region is etched so that the polycrystalline silicon does not remain on the side surface of the stepped region. The purpose is.
도1a 및 도1b는 종래 반도체 소자의 단차영역에서 다결정실리콘의 식각방법을 보인 일실시예도.1A and 1B illustrate an embodiment of a method of etching polysilicon in a stepped region of a conventional semiconductor device.
도2a 내지 도2c는 본 발명 반도체 소자의 단차영역에서 다결정실리콘의 식각방법을 보인 일실시예도.2A to 2C illustrate an embodiment of an etching method of polysilicon in a stepped region of a semiconductor device of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
1,4:고온저압산화막 2,6:다결정실리콘1,4 high temperature low pressure oxide film 2,6 polycrystalline silicon
3:텅스텐실리사이드 5:질화막3: tungsten silicide 5: nitride film
상기와 같은 목적은 반도체 소자의 특정 구조의 형성으로 단차가 형성된 절연막의 상부에 증착된 다결정실리콘을 ECR 소스를 사용하여 식각하는 반도체 소자의 단차영역에서 다결정실리콘의 식각방법에 있어서, 상기 식각으로 단차가 높은 영역의 측면에 잔존하는 다결정실리콘을 SF6가스를 이용하여 식각하는 후처리공정을 더 포함하여 구성함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is a method of etching polycrystalline silicon in a stepped region of a semiconductor device in which a polysilicon deposited on top of an insulating film on which a step is formed by forming a specific structure of the semiconductor device is etched using an ECR source. It is achieved by further comprising a post-treatment step of etching the polysilicon remaining on the side of the high region using SF 6 gas, described in detail with reference to the accompanying drawings, the present invention.
도2a 내지 도2c는 반도체 메모리의 공통 플래이트를 형성하는 본 발명 반도체 소자의 단차영역에서 다결정실리콘의 식각방법의 일실시예도로서, 이에 도시한 바와 같이 고온저압산화막(1), 다결정실리콘(2), 텅스텐실리사이드(3) 적층구조의 상부에 고온저압산화막(4)을 증착하고, 상기 고온저압산화막(4)의 상부에 질화막(5)과 절연층인 다결정실리콘(6)을 순차적으로 증착하는 단계(도2a)와; 상기 다결정실리콘(6)과 질화막을 ECR 플라즈마 소스를 이용한 건식식각으로 식각하여 상기 고온저압산화막(4)의 상부면을 노출시키며, 그 고온저압산화막(4)의 측면에 질화막(5) 측벽을 형성하는 단계(도2b)와; 상기 질화막(5) 측벽의 측면에 잔존하는 다결정실리콘(6)을 SF6가스를 이용하여 등방성식각하여 제거하는 단계(도2c)로 구성된다.2A to 2C are diagrams illustrating one embodiment of a method of etching polycrystalline silicon in a stepped region of a semiconductor device according to an embodiment of the present invention to form a common plate of a semiconductor memory. As shown therein, a high temperature low pressure oxide film 1 and a polycrystalline silicon 2 are illustrated. And depositing a high temperature low pressure oxide film 4 on the tungsten silicide layer 3 stacked structure, and sequentially depositing a nitride film 5 and an insulating layer polycrystalline silicon 6 on the high temperature low pressure oxide film 4. (FIG. 2A); The polysilicon 6 and the nitride film are etched by dry etching using an ECR plasma source to expose the upper surface of the high temperature low pressure oxide film 4, and a sidewall of the nitride film 5 is formed on the side surface of the high temperature low pressure oxide film 4. (Step 2b); The polycrystalline silicon 6 remaining on the side surface of the nitride film 5 is removed by isotropic etching using SF 6 gas (FIG. 2C).
즉, 종래와 같은 방법으로 건식식각을 이용하여 단차영역의 측면에 질화막(5) 측벽을 형성하고, 그 질화막(5) 측벽의 측면에 잔존하는 다결정실리콘(6)을 압력조건을 1pa로 하고, 마그네트론 파워를 450W, 챔버 상중하의 코일에 각각 19, 19, 5A의 전류를 인가한 상태에서 SF6가스를 50ccm 정도 유입시켜 선택적으로 잔존하는 다결정실리콘(6)만을 제거함으로써, 이후의 공정에서 쇼트의 발생을 우려할 필요가 없다.That is, the sidewalls of the nitride film 5 are formed on the side surface of the stepped region by dry etching in the same manner as the conventional method, and the pressure condition is 1pa for the polycrystalline silicon 6 remaining on the side surface of the nitride film 5 sidewall. With the magnetron power of 450 W and the chamber upper and lower coils with currents of 19, 19, and 5 A respectively, SF 6 gas was introduced by about 50 ccm to selectively remove only the remaining polycrystalline silicon 6, thereby eliminating the short There is no need to worry about the occurrence.
또한, 도2a와 도2b의 실시로 단차영역의 측면에 형성한 질화막(5) 측벽의 측면에 잔존하는 다결정실리콘(6)을 식각하는 다른 방법은 인가 전력을 550W의 TCP(TRANSFORMER COUPLED PLASMA)로 하여, 상기 일실시예와 같이 SF6가스를 50ccm의 유량으로 인가하여 식각하며, 이때의 식각공정은 상온에서 실시가 가능하다.In addition, another method of etching the polysilicon 6 remaining on the side of the sidewall of the nitride film 5 formed on the side of the stepped region by the implementation of FIGS. 2A and 2B is applied to a 550 W TCP (TRANSFORMER COUPLED PLASMA). Thus, as in the above embodiment, the SF 6 gas is etched by applying a flow rate of 50 ccm, and the etching process may be performed at room temperature.
상기한 바와 같이 본 발명은 단차영역의 측면부에 불필요하게 잔존하는 다결정실리콘을 SF6가스를 이용하여 제거하는 후속공정을 더 포함하여 이후의 공정에서 발생할 수 있는 잔존하는 다결정실리콘과 도전막의 쇼트를 방지하여 반도체 소자의 특성이 열화되는 것을 방지하는 효과가 있다.As described above, the present invention further includes a subsequent step of removing unnecessary polycrystalline silicon remaining on the side portion of the stepped region using SF 6 gas to prevent short-circuit of the remaining polycrystalline silicon and the conductive film that may occur in a subsequent process. Therefore, there is an effect of preventing deterioration of characteristics of the semiconductor device.
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| KR1019980043119A KR100273313B1 (en) | 1998-10-15 | 1998-10-15 | Etching method of polysilicon in the stepped region of semiconductor device |
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| KR1019980043119A KR100273313B1 (en) | 1998-10-15 | 1998-10-15 | Etching method of polysilicon in the stepped region of semiconductor device |
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