KR20000020953A - Path memory unit of viterbi decoder - Google Patents

Abstract

PURPOSE: A path memory unit of Viterbi decoder is provided to reduce a power consumption and a chip size by utilizing a RAM as a path memory. CONSTITUTION: A path memory unit of Viterbi decoder comprises a first selector(11), a second selector(12), a trace back calculator(14), a data converter(15), a memory controller, and a path memory(10). The first selector selects one of outputs from the path memory and generates a path selection signal. The second selector selects a minimum state number from an addition comparison selection unit when a start clock is an active state and selects an output from the trace back calculator when the start clock is not the active state. The trace back calculator combines logically the outputs from the first and the second selectors. The data converter decodes the output from the trace back calculator. The memory controller outputs an address signal and a write/read control signal. The path memory stores the path selection signal to a corresponding address and reads and outputs the stored data.

Description

Path memory device of Viterbi decoder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a path memory device of a Viterbi decoder. In particular, a path memory essential for a trace back of a Viterbi decoder is required by implementing a random access memory. The present invention relates to a path memory device of a Viterbi decoder which reduces power consumption and reduces chip size.

In general, a Viterbi decoder for data decoding used in a communication system such as a mobile telephone includes an input unit for accessing data from a demodulator; Addition comparison unit that calculates the current state metric (CSM) and repeats the process of calculating the current state metric in the next state by using the result of the calculation as the previous state metric (PSM). (Adder-Compare-Selector, ACS); The add comparison selector is composed of a traceback that receives the comparison information, searches for an error in the input data, decodes the output data, and describes the details in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a path memory device of a conventional Viterbi decoder. As shown in FIG. A path memory 10 for performing a shift operation to a second direction; When the start clock is active, the path selection signal PS is selected from the add comparison selector ACS. When the start clock is not active, the output of the path memory 10 is output. A first selection unit 11 for selecting; A second selector 12 which selects one of the outputs of the path memory 10 according to the output of the third selector 13 and generates a path select signal corresponding to the number of current states to be tracked; Selecting a minimum number MS supplied from the addition comparison selecting unit ASC when the start clock is in an active state, and selecting an output of the traceback calculator 14 when the start clock is not in the active state. A selection unit 13; A traceback calculation unit 14 implemented as a logic combination circuit and receiving and outputting the outputs of the second selector 12 and the third selector 13 in logical combination; The data conversion unit 15 receives the output of the traceback calculation unit 14 and converts the information to a decoded information symbol based on a convolution coding scheme. The process is as follows.

As shown in FIG. 1, the path memory 10 is in the form of a shift register having a th + 1 stage each having a depth of a trace back th, wherein the stages of the shift registers are configured in parallel. The path memory 10 moves in one direction according to the system clock to perform a shift operation.

The first selector 11 selects one of an output of the path memory 10 and a path selection signal applied from the add comparison selector ACS according to the start clock, and supplies the selected path to the path memory 10. That is, when the start clock is active, the path selection signal PS is selected from the addition comparison selecting unit ACS, and when the start clock is not active (non-active), the output of the path memory 10 is output. Select. The start clock (FIG. 2B) is synchronously active every symbol clock pulse (FIG. 2C), and the system clock (FIG. 2A) is active tb times in one symbol interval.

Table 1 below shows the operation of the path memory 10 according to the system clock and the start clock. The path memory 10 only stores an input signal in the initial seven symbol intervals, The actual trace back operation is performed. The output of the path memory 10 at the eighth symbol is the PS 7 corresponding to the path selection signal of the seventh time point. This signal is sent to the second selector 12 to feed back to the input of the path memory 10 via the first selector 11 as well as to generate the next trace back position.

Symbol clock System clock Memory Contents One One PS (1) 2 PS (1) 3 PS (1) … 7 PS (1) 2 One PS (2) PS (1) 2 PS (1) PS (2) … 7 PS (1) PS (2) 3 One PS (3) PS (1) PS (2) 2 PS (2) PS (3) PS (1) … 4 One PS (4) PS (1) PS (2) PS (3) … 7 One PS (7) PS (1) PS (2) PS (3) PS (4) PS (5) PS (6) … 7 PS (1) PS (2) PS (3) PS (4) PS (5) PS (6) PS (7) 8 One PS (8) PS (1) PS (2) PS (3) PS (4) PS (5) PS (6) PS (7) 2 PS (7) PS (8) PS (1) PS (2) PS (3) PS (4) PS (5) PS (6) 3 PS (6) PS (7) PS (8) PS (1) PS (2) PS (3) PS (4) PS (5) 4 PS (5) PS (6) PS (7) PS (8) PS (1) PS (2) PS (3) PS (4) …

In Table 1, PS (t) represents PS ₀ (t) -PS ₅ (t), and t represents a time point.

The output of the path memory 10 is applied to the first selector 11 and the second selector 12, wherein the second selector 12 is the path according to the output of the third selector 13. One of the outputs of the memory 10 is selected, and one of the minimum state number MS and the traceback calculator 14 is selected according to the start clock. In other words, when the start clock is in an active state, the minimum state number MS supplied from the addition comparison selecting unit ASC is selected, and when the start clock is not in an active state, the output of the traceback calculator 14 is selected. . Accordingly, the third selector 13 generates a path selection signal corresponding to the current state number to be tracked.

In addition, the traceback calculation unit 14 is implemented as a logical combination path, and Table 2 below shows the truth table of the traceback calculation unit for an ascending encoding scheme.

Third comparator output 2nd comparator output Traceback 00 (S ₀ ) 0 0 00 (S ₁ ) One One 01 (S ₂ ) 0 10 01 (S ₃ ) One 11 10 (S ₄ ) 0 0 10 (S ₅ ) One One 11 (S ₆ ) 0 10 11 (S ₇ ) One 11

The data converter 15 affects the output of the traceback calculator 14 to generate decoded information symbols every symbol period. In other words, the output of the traceback calculation unit 14 is input to change to a decoded information symbol based on the rising encoding scheme. For example, the output immediately before the last output of the traceback calculator 14 in the rising encoding can be used to generate a decoded information symbol. That is, the previous output of S ₀ or S ₁ generates a decoded information symbol of "0" while the previous output of S ₂ or S ₃ generates and outputs a decoded information symbol of "1".

As described above, in the conventional technology, the path memory is configured as a register, and when the depth of the trace back is increased, the path memory is increased exponentially, and when the path memory is implemented as a register, the size of the chip is increased as well. There is a problem in that power consumption increases because a large shift must be performed for the entire register.

Accordingly, the present invention has been made to solve the conventional problems as described above, and implements a path memory using a random access memory (RAM) to provide a device that reduces the power consumption and chip size Has its purpose.

1 is a block diagram showing a configuration of a path memory device of a conventional Viterbi decoder.

2 is a signal timing diagram of a start clock and a system clock in FIG.

3 is a block diagram showing a configuration of a path memory device of the Viterbi decoder of the present invention.

4 is a signal timing diagram of a start clock and a system clock in FIG.

*** Description of the symbols for the main parts of the drawings ***

10, 22: path memory 11, 23: first selection unit

12, 24: second selector 13: third selector

14, 25: traceback calculation unit 15, 26: data conversion unit

20: memory control unit 21: down counter

The structure of the path memory device of the Viterbi decoder according to the present invention for achieving the above object generates a path selection signal corresponding to the number of current states tracked by selecting one of the outputs of the path memory according to the output of the second selection unit. A first selection unit to perform; A second selector which selects the minimum state number MS supplied from the addition comparison selector ASC when the start clock is in an active state and selects an output of the traceback calculator when the start clock is not in an active state; A traceback calculation unit implemented as a logic combination circuit and receiving and outputting the outputs of the first and second selection units in a logical combination; A path memory device of a Viterbi decoder comprising a data converter which receives an output of the traceback calculator and converts the information into a decoded information symbol based on an ascending encoding scheme. A memory controller which outputs a write / read control signal; And a path memory configured to store a path selection signal input from the addition comparison selection unit (ACS) at the corresponding address by the address signal output from the memory controller or to read and store the stored data. .

The memory controller may further include a down counter configured to output an address signal when the system clock is low in synchronization with the system clock.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram showing the configuration of a path memory device of the Viterbi decoder according to the present invention. As shown in FIG. 3, the memory controller 20 receives a start clock and a system clock and outputs an address signal and a write / read control signal. ; A path memory (22) for storing a path selection signal input from an addition comparison selection unit (ACS) at a corresponding address or reading out and storing the stored data by the address signal output from the memory controller (20); A first selector 23 which selects one of the outputs of the path memory 22 according to the output of the second selector 24 and generates a path select signal corresponding to the number of current states to be tracked; Selecting a minimum number of states MS supplied from the addition comparison selecting unit ASC when the start clock is in an active state, and selecting an output of the traceback calculator 25 when the start clock is not in the active state. A selection unit 24; A traceback calculation unit 25 implemented as a logic combination circuit and receiving and outputting the outputs of the first selector 23 and the second selector 24 in a logical combination; And a data converter 26 which receives the output of the traceback calculator 25 and converts the information into a decoded information symbol based on an ascending encoding scheme. The memory controller 20 synchronizes with the system clock. The apparatus further includes a down counter 21 that outputs an address signal when the clock is low.

Referring to Figure 4 attached to the operation of the embodiment according to the present invention configured as described above are as follows.

The memory controller 20 of FIG. 3 receives a start clock and a system clock and outputs an address signal and a write / read control signal. The memory controller 20 is synchronized with the system clock by a down counter 21 located therein. An address signal is output when the system clock is low, which consists of one write and one read address as many as the trace back depth. In addition, as shown in FIG. 4, the write or read control signal is outputted with the write control signal in the high part of the given start clock and the read control signal in the low part.

By the address signal output from the memory controller 20, the path memory 22 stores the path selection signal PS inputted from the addition comparison selection unit ACS at the corresponding address or reads out the stored data. (I.e. all memory cells do not need to be accessed sequentially, only the necessary values are read).

Since the operations of the first selector 23, the second selector 24, the traceback calculator 25, and the data converter 26 are the same as in the related art, detailed descriptions thereof will be omitted.

As described above, the path memory device of the Viterbi decoder of the present invention implements the path memory using RAM so that only the necessary values are read without all memory cells being continuously accessed, thereby consuming the required power. It has the effect of improving the integration by reducing the size of the chip.

Claims (2)

A first selector which selects one of the outputs of the path memory according to the output of the second selector and generates a path select signal corresponding to the current state number tracked; A second selector which selects the minimum state number MS supplied from the addition comparison selector ASC when the start clock is in an active state and selects an output of the traceback calculator when the start clock is not in an active state; A traceback calculation unit implemented as a logic combination circuit and receiving and outputting the outputs of the first and second selection units in a logical combination; A path memory device of a Viterbi decoder comprising a data converter which receives an output of the traceback calculator and converts the information into a decoded information symbol based on an ascending encoding scheme. A memory controller which outputs a write / read control signal; And a path memory configured to store a path selection signal input from an addition comparison selection unit (ACS) at a corresponding address by the address signal output from the memory controller or to read and store the stored data. Path memory device for Viterbi decoder. The Viterbi decoder path memory device of claim 1, wherein the memory controller further comprises a down counter configured to output an address signal when the system clock is low in synchronization with the system clock.