KR20000019002A - Semiconductor package dedicated printed circuit board for electrostatic prevention - Google Patents

Semiconductor package dedicated printed circuit board for electrostatic prevention Download PDF

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Publication number
KR20000019002A
KR20000019002A KR1019980036897A KR19980036897A KR20000019002A KR 20000019002 A KR20000019002 A KR 20000019002A KR 1019980036897 A KR1019980036897 A KR 1019980036897A KR 19980036897 A KR19980036897 A KR 19980036897A KR 20000019002 A KR20000019002 A KR 20000019002A
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KR
South Korea
Prior art keywords
resin substrate
circuit board
printed circuit
solder mask
ground
Prior art date
Application number
KR1019980036897A
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Korean (ko)
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KR100298689B1 (en
Inventor
김성진
Original Assignee
마이클 디. 오브라이언
앰코 테크놀로지 코리아 주식회사
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Application filed by 마이클 디. 오브라이언, 앰코 테크놀로지 코리아 주식회사 filed Critical 마이클 디. 오브라이언
Priority to KR1019980036897A priority Critical patent/KR100298689B1/en
Priority to JP10334667A priority patent/JP3020201B2/en
Priority to JP10346145A priority patent/JP2997746B2/en
Priority to US09/240,422 priority patent/US6246015B1/en
Priority to US09/240,423 priority patent/US6214645B1/en
Publication of KR20000019002A publication Critical patent/KR20000019002A/en
Application granted granted Critical
Publication of KR100298689B1 publication Critical patent/KR100298689B1/en

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0254High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H05K1/0257Overvoltage protection
    • H05K1/0259Electrostatic discharge [ESD] protection
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0224Patterned shielding planes, ground planes or power planes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/429Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Abstract

PURPOSE: A semiconductor package dedicated printed circuit board is provided to make an electrostatic of a semiconductor chip become an outflow into a metal mold by contacting a ground dedicated protrusion to the metal mold at molding. CONSTITUTION: The semiconductor package dedicated printed circuit board comprises: a chip loading portion formed to load a semiconductor chip on an upper part of a resin substrate; circuit patterns (12) formed at all directions of the chip loading portion; a solder mask (15) coated on the upper part of the resin substrate so as to protect the circuit patterns; a via hole for connecting the circuit patterns to an upper part and a lower part of the resin substrate; a solder ball land connected to the lower part of the resin substrate, for forming an area where the solder ball is melt and attached; a solder mask coated at an area except the solder ball land; a gold gate formed at the resin substrate toward the chip loading portion to protect the semiconductor chip, wherein two lead lines are extracted from bus lines (50) to be removed after this and are merged by one lead line; wherein by coating the merged part opening the solder mask, a ground dedicated protrusion part (22) is formed by an excessive current issued at coating and has a thickness larger than that of the solder mask.

Description

정전기 방지를 위한 반도체패키지용 인쇄회로기판Printed circuit board for semiconductor package to prevent static

본 발명은 정전기 방지를 위한 반도체패키지용 인쇄회로기판에 관한 것으로, 보다 상세하게 설명하면 몰딩중 발생하는 인쇄회로기판이나 반도체칩으로부터의 정전기를 금형쪽으로 용이하게 유출시킬 수 있는 인쇄회로기판에 관한 것이다.The present invention relates to a printed circuit board for a semiconductor package for preventing static electricity, and more particularly to a printed circuit board that can easily discharge static electricity from a printed circuit board or a semiconductor chip generated during molding to the mold. .

최근에 개발되는 반도체칩은 통상 구동 전압이 낮고 또한 허용되는 전압의 오차가 작으며, 회로패턴이 미세하게 형성되어 있음으로써, 반도체칩을 어셈블링하는 패키징 공정에서 반도체칩에 정전기가 축적된 후 일시에 방전되어 반도체칩을 파손시키는 문제가 빈번히 발생하고 있다. 이러한 문제점은 특히 인쇄회로기판의 몰딩 공정후 인쇄회로기판을 금형에서 빼내거나 또는 빼낸후 인쇄회로기판이 다른 자재에 접촉될 때 갑작스런 정전기의 방전으로 반도체칩이 쉽게 파손되곤 한다.Recently developed semiconductor chips have a low driving voltage, a small allowable error of the voltage, and a fine circuit pattern. Thus, in a packaging process of assembling a semiconductor chip, the semiconductor chip is temporarily stored after static electricity is accumulated. The problem of frequently discharging the chip to damage the semiconductor chip occurs. Such a problem is that the semiconductor chip is easily damaged by sudden discharge of static electricity, especially when the printed circuit board is removed from the mold or the printed circuit board is in contact with other materials after the molding process of the printed circuit board.

종래에는 이를 방지 하기 위해, 인쇄회로기판의 저면에 소정의 그라운드용 평판(22')을 형성하였는데 이를 첨부된 도1a 내지 도2를 참조하여 설명하면 다음과 같다.Conventionally, in order to prevent this, a predetermined ground plate 22 'is formed on the bottom surface of the printed circuit board, which will be described below with reference to FIGS. 1A to 2.

먼저 상기 인쇄회로기판(10)의 전체적인 구조를 설명하면, 수지기판(도시되지 않음)과, 상기한 수지기판의 상면에 반도체칩이 실장될 수 있도록 형성된 칩탑재부(16)와, 상기한 칩탑재부(16)의 주변에 방사상으로 형성된 회로패턴(12)과, 상기 회로패턴(12)을 보호하도록 수지기판의 상부에 코팅된 솔더마스크(15)와, 상기한 회로패턴(12)을 수지기판의 상,하부로 연결하는 전도성 비아홀(13)과, 상기한 비아홀(13)에 의해 수지기판의 하부에 연결되어 솔더볼이 융착되도록 형성된 솔더볼랜드(14)와, 상기한 수지기판의 하부에 솔더볼랜드(14)를 제외한 영역에 코팅된 솔더마스크(15)와, 상기 반도체칩의 그라운드 신호가 연결되며, 봉지재가 투입되도록 상기 수지기판의 상면에 형성된 골드게이트(17)와, 상기한 인쇄회로기판(10)의 상하부에 코팅된 솔더마스크(15)가 한정적으로 개방되고, 이 개방된 영역을 통해 솔더마스크(15)의 높이 보다 약간 높게 형성되며, 상기한 반도체칩의 그라운드 신호와 연결되는 대략 직사각형 모양의 그라운드용 평판(22')으로 이루어져 있다.First, the overall structure of the printed circuit board 10 will be described. A resin substrate (not shown), a chip mounting portion 16 formed so that a semiconductor chip can be mounted on an upper surface of the resin substrate, and the chip mounting portion are described above. The circuit pattern 12 formed radially around the periphery 16, the solder mask 15 coated on the upper surface of the resin substrate so as to protect the circuit pattern 12, and the circuit pattern 12 are formed on the resin substrate. Conductive via holes 13 connected to the upper and lower portions, solder bores 14 connected to the lower part of the resin substrate by the via holes 13 so that the solder balls are fused, and solder ball lands below the resin substrate. A solder mask 15 coated in a region excluding 14, a ground signal of the semiconductor chip is connected, a gold gate 17 formed on an upper surface of the resin substrate so that an encapsulant is introduced, and the printed circuit board 10 The solder mask 15 coated on the upper and lower parts of the It is limitedly open and is formed slightly higher than the height of the solder mask 15 through this open area, and is composed of a substantially rectangular ground flat plate 22 'connected to the ground signal of the semiconductor chip.

도면중 미설명 부호 25는 칩탑재부(16)의 외주연에 형성된 그라운드링이며, 이는 반도체칩의 모든 그라운드용 와이어가 연결되어 골드게이트(17)쪽으로 그라운드용 회로패턴(21)을 통하여 전달된다. 이와 같이 골드게이트(17)에 반도체칩의 그라운드 신호를 전달하는 이유는 차후에 회로패턴(12)과 반도체칩의 와이어본딩 불량 여부를 판정하거나 또는 공통의 그라운드 영역을 형성하여 필요한 회로패턴을 최대한 확보하기 위함이다.Reference numeral 25 in the figure is a ground ring formed on the outer periphery of the chip mounting portion 16, which is connected to all the ground wires of the semiconductor chip is transferred to the gold gate 17 through the ground circuit pattern 21. The reason for transmitting the ground signal of the semiconductor chip to the gold gate 17 is to determine whether the wire pattern of the circuit pattern 12 and the semiconductor chip is poor in the future or to form the common ground area to secure the necessary circuit pattern as much as possible. For sake.

이러한 구조의 인쇄회로기판(10)은 도2에 도시된 바와 같이 반도체 패키지의 제조 공정중 몰딩단계에서 상기한 인쇄회로기판(10)을 몰드금형(30a, 30b)에 안착시키는 것에 의해서 간단하게 그라운딩된다. 즉, 상기한 인쇄회로기판(10)의 저면에 그라운드용 평판(22')이 솔더마스크(15)의 높이 보다 약간 높게 형성됨으로써, 이 그라운드용 평판(22')이 몰드금형에 접지된다.The printed circuit board 10 having such a structure is simply grounded by placing the printed circuit board 10 on the mold molds 30a and 30b in the molding step of the semiconductor package manufacturing process as shown in FIG. do. That is, the ground plate 22 'is formed slightly higher than the height of the solder mask 15 on the bottom of the printed circuit board 10, so that the ground plate 22' is grounded to the mold mold.

도면중 미설명 부호 40은 반도체칩이고, 42는 전도성와이어이다.In the figure, reference numeral 40 is a semiconductor chip, and 42 is a conductive wire.

따라서, 몰딩단계에서 봉지재의 주입시 봉지재가 반도체칩(40), 와이어(42) 및 인쇄회로기판(10)과 마찰되는 것에 의해 발생되는 전하가 반도체칩에 축적되지 않고, 상기한 그라운드용 평판(22')을 통해 금형(30b)으로 유출됨으로서, 갑작스런 정전기 방전에 의한 반도체칩의 파손을 미연에 방지하도록 도모하고 있다.Therefore, the charge generated by the encapsulant rubbing with the semiconductor chip 40, the wire 42 and the printed circuit board 10 during the injection of the encapsulant in the molding step is not accumulated in the semiconductor chip, 22 ') flows into the mold 30b to prevent damage to the semiconductor chip due to sudden electrostatic discharge.

그러나 이러한 종래의 인쇄회로기판은 상기 그라운드용 평판을 형성하기 위해, 인쇄회로기판의 제조 공정시 추가 공정 즉, 2번의 도금을 별도로 더 실시하여야 함으로서 제조 시간이 오래 걸리고, 제조 단가가 비싸지는 문제점이 있다.However, such a conventional printed circuit board has a problem in that it takes a long manufacturing time and a high manufacturing cost by additionally performing two additional plating processes during the manufacturing process of the printed circuit board, in order to form the ground flat plate. .

또한 상기 그라운드용 평판을 넓게 형성함으로서 그 두께를 일정하게 조절하기가 매우 곤란하며, 동시에 수율이 낮기 때문에 대량 생산을 기반으로 하는 반도체패키지 제조 공정에 직접 적용하는 것이 불가능한 문제점이 있다.In addition, it is very difficult to constantly control the thickness by forming the ground flat plate, and at the same time there is a problem that it is impossible to apply directly to the semiconductor package manufacturing process based on mass production because the yield is low.

본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 인쇄회로기판의 제조시 별도의 공정을 추가하지 않은채 그 일면에 그라운드용 돌기부가 형성되도록 함으로써, 몰딩시 상기 그라운드용 돌기부가 금형에 접촉되어 반도체칩 등으로부터의 정전기를 금형으로 용이하게 유출시킬 수 있는 정전기 방지를 위한 반도체패키지용 인쇄회로기판을 제공하는데 있다.The present invention has been made to solve the above-mentioned conventional problems, by forming a ground projection on one side of the printed circuit board without adding a separate process, the ground projection during molding the mold The present invention provides a printed circuit board for a semiconductor package for preventing static electricity, which is in contact with and can easily discharge static electricity from a semiconductor chip to a mold.

도1a는 종래 인쇄회로기판을 도시한 평면도이고, 도1b는 그 저면도이며, 도1c는 도1b의 A부분 확대도이다.1A is a plan view showing a conventional printed circuit board, FIG. 1B is a bottom view thereof, and FIG. 1C is an enlarged view of portion A of FIG. 1B.

도2는 종래 인쇄회로기판이 금형에 접촉되는 상태를 도시한 상태도이다.2 is a state diagram illustrating a state in which a conventional printed circuit board is in contact with a mold.

도3a는 본 발명에 의한 인쇄회로기판의 저면도이고, 도3b는 도3a의 B부분 확대도이며, 도3c는 도3b의 C-C'선 단면도이다.FIG. 3A is a bottom view of the printed circuit board according to the present invention, FIG. 3B is an enlarged view of a portion B of FIG. 3A, and FIG. 3C is a sectional view taken along the line CC 'of FIG. 3B.

- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-

10 ; 인쇄회로기판 11 ; 수지기판10; Printed circuit board 11; Resin board

12 ; 회로패턴 13 ; 전도성 비아홀12; Circuit pattern 13; Conductive via hole

14 ; 솔더볼랜드 15 ; 솔더마스크14; Solder borland 15; Solder mask

16 ; 칩탑재부 17 ; 골드게이트16; Chip mounting part 17; Gold gate

18 ; 툴링홀 19 ; 싱귤레이션홀18; Tooling holes 19; Singulation Hall

20 ; 그라운드용 비아홀 21,24 ; 그라운드용 회로패턴20; Via hole for ground 21,24; Ground Circuit Pattern

22 ; 그라운드용 돌기부 25 ; 그라운드링22; Ground projection 25; Ground ring

30a ; 상금형 30b ; 하금형30a; Prize mold 30b; Lower mold

40 ; 반도체칩 42 ; 전도성와이어40; Semiconductor chip 42; Conductive Wire

50 ; 버스라인 51,52,53 ; 리드선50; Bus lines 51,52,53; Lead wire

상기한 목적을 달성하기 위해 본 발명에 의한 정전기 방지를 위한 반도체패키지용 인쇄회로기판은, 수지기판과; 상기한 수지기판의 상면에 반도체칩이 실장될 수 있도록 형성된 칩탑재부와; 상기한 칩탑재부의 사방에 방사형으로 형성된 회로패턴과; 상기한 회로패턴을 보호하도록 수지기판의 상부에 코팅된 솔더마스크와; 상기한 회로패턴을 수지기판의 상하부로 연결하는 비아홀과; 상기한 비아홀에 의해 수지기판의 하부로 연결되어 솔더볼이 융착될 수 있는 영역을 형성하는 솔더볼랜드와; 상기한 수지기판의 하부에 솔더볼랜드를 제외한 영역에 코팅된 솔더마스크와; 상기 반도체칩을 보호하기 위해 칩탑재부쪽을 향하여 수지기판상에 형성된 골드게이트로 이루어진 인쇄회로기판에 있어서, 상기 인쇄회로기판의 회로패턴에 연결되어 있되, 차후 제거되는 버스라인에는 수지기판상으로 두개의 분기된 리드선이 형성되어 있고, 상기 두개의 리드선은 다시 하나의 리드선으로 합치된채 그라운드 신호가 출력되는 그라운드용 회로패턴에 연결되어 있으며, 상기 두개의 리드선이 합치된 부분에는 솔더마스크가 개방된채 그 솔더마스크의 두께보다 두껍게 그라운드용 돌기부가 형성됨으로써, 몰딩중 상기 도금영역이 금형에 접촉되도록 하여 반도체칩 및 인쇄회로기판에 형성되는 정전기가 금형쪽으로 유출되도록 한 것을 특징으로 한다.In order to achieve the above object, a printed circuit board for a semiconductor package for preventing static electricity according to the present invention includes a resin substrate; A chip mounting part formed on the upper surface of the resin substrate so that a semiconductor chip can be mounted; A circuit pattern formed radially on all sides of the chip mounting part; A solder mask coated on the resin substrate to protect the circuit pattern; A via hole connecting the circuit pattern to the upper and lower parts of the resin substrate; A solder ball land connected to the lower portion of the resin substrate by the via hole to form an area in which solder balls may be fused; A solder mask coated on a region of the resin substrate except for solder ball lands; In the printed circuit board consisting of a gold gate formed on the resin substrate toward the chip mounting portion to protect the semiconductor chip, which is connected to the circuit pattern of the printed circuit board, two bus lines that are removed later on the resin substrate A branched lead wire is formed, and the two lead wires are connected to a ground circuit pattern to which a ground signal is output while being matched with one lead wire, and a solder mask is opened at a portion where the two lead wires coincide. The ground projection is formed thicker than the thickness of the solder mask, so that the plating area is in contact with the mold during molding, so that static electricity formed on the semiconductor chip and the printed circuit board is discharged to the mold.

이와 같이 하여, 도금 작업시 버스라인을 통하여 두개의 리드선으로 흐르던 전류가 하나로 합치된 리드선에 흐르게 된다. 그러면, 상기 하나로 합치된 리드선에는 과전류가 흐르게 되고, 또한 상기 합치된 리드선에는 그라운드용 돌기가 형성되도록 솔더마스크가 개방되어 있음으로써, 상기 과전류에 의해 두께가 비교적 큰 그라운드용 돌기부가 형성된다.In this way, the current flowing through the bus lines during the plating operation to the two lead wires flows into the lead wires matched with one. Then, an overcurrent flows through the lead wire matched with the one, and the solder mask is opened to form a ground protrusion in the matched lead wire, whereby a ground protrusion having a relatively large thickness is formed by the overcurrent.

한편, 상기 인쇄회로기판의 칩탑재부에 반도체칩을 접착하고, 그 반도체칩과 회로패턴을 전도성와이어로 연결한 후, 상기 인쇄회로기판을 금형에 탑재하여 몰딩을 하게 되면, 상기 금형에 인쇄회로기판의 그라운드용 돌기부가 접촉하게 된다. 그러면, 몰딩공정중 봉지재와 상기 반도체칩, 전도성와이어, 인쇄회로기판 등의 마찰에 의해 반도체칩 등으로부터 유기는 정전기가 상기 그라운드용 돌기부를 통하여 금형으로 유출됨으로써, 정전기의 갑작스런 방전에 의해 반도체칩이 파손되는 것을 미연에 방지할 수 있게 된다.On the other hand, after bonding a semiconductor chip to the chip mounting portion of the printed circuit board, connecting the semiconductor chip and the circuit pattern with a conductive wire, and mounting the printed circuit board to a mold to be molded, the printed circuit board in the mold The ground projection of the contact comes in contact. Then, during the molding process, static electricity that is induced from the semiconductor chip due to friction between the encapsulant, the semiconductor chip, the conductive wire, and the printed circuit board flows out into the mold through the ground protrusion, and thus the semiconductor chip is suddenly discharged. This damage can be prevented beforehand.

이하 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하며, 종래 기술과 중복된 내용은 그 설명을 생략하고 도면 부호는 동일하게 사용한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention. The description is omitted and the same reference numerals are used.

도3a는 본 발명에 의한 인쇄회로기판(10)의 저면도이고, 도3b는 도3a의 B부분 확대도이며, 도3c는 도3b의 C-C'선 단면도이다.FIG. 3A is a bottom view of the printed circuit board 10 according to the present invention, FIG. 3B is an enlarged view of a portion B of FIG. 3A, and FIG. 3C is a cross-sectional view taken along the line CC 'of FIG. 3B.

먼저 도3a 및 도3b에 도시된 바와 같이 차후에 다수의 솔더볼이 융착될 수 있도록 인쇄회로기판(10)의 저면에 다수의 솔더볼랜드(14)가 형성되어 있고, 그 솔더볼랜드(14)들의 외주연에는 상기 솔더볼랜드(14)들을 향하여 다수의 회로패턴(12)(개략적으로 도시됨)들이 형성되어 있다. 상기 회로패턴(12)들은 수지기판(11)상의 버스라인(50)에 모두 연결되어 있으며, 이 버스라인(50)은 인쇄회로기판(10)의 제조 공정중 모두 제거되지만 설명의 편의를 의해 도면중에 도시하였다.First, as shown in FIGS. 3A and 3B, a plurality of solder bores 14 are formed on the bottom surface of the printed circuit board 10 so that a plurality of solder balls may be fused later, and the outer peripheral edges of the solder bores 14 are formed. A plurality of circuit patterns 12 (shown schematically) are formed in the solder ball lands 14. The circuit patterns 12 are all connected to the bus lines 50 on the resin substrate 11, and the bus lines 50 are removed during the manufacturing process of the printed circuit board 10. Shown.

상기한 버스라인(50)에는 회로패턴(12)의 일측면에 두개의 분기된 리드선(51,52)이 역삼각형 모양으로 형성되어 있고, 상기 두개의 리드선(51,52)은 다시 하나의 리드선(53)으로 합치된채 그라운드 신호가 출력되는 그라운드용 비아홀(20)에 연결되어 있다. 이 비아홀(20)은 또한 골드게이트(17)에 연결되어 있으며, 상기 골드게이트(17)는 종래에서와 같이 그라운드링(25)에 연결되어 있다.In the bus line 50, two branched lead wires 51 and 52 are formed in an inverted triangle shape on one side of the circuit pattern 12, and the two lead wires 51 and 52 are one lead wire again. The ground signal is connected to the ground via hole 20 to which the ground signal is output. The via hole 20 is also connected to the gold gate 17, which is connected to the ground ring 25 as in the prior art.

상기 리드선(51,52,53)들은 회로패턴(12)과 마찬가지로 모두 솔더마스크(15)로 코팅되어 있지만, 상기 두개의 리드선(51,52)이 합치된 부분 즉, 하나의 리드선(53)에는 솔더마스크(15)가 개방된 채, 그 솔더마스크(15)의 두께보다 두껍게 그라운드용 돌기부(22)가 형성되어 있다.The lead wires 51, 52, and 53 are all coated with a solder mask 15 like the circuit pattern 12, but the lead wires 51, 52, and 53 are joined to each other, that is, one lead wire 53. With the solder mask 15 open, the ground protrusions 22 are formed thicker than the thickness of the solder mask 15.

또한 상기 그라운드용 돌기부(22)에 연장되어서는 골드게이트(17)에 연결되어 있는 그라운드용 비아홀(20)까지 그라운드용 회로패턴(25)이 형성되어 있음으로써, 반도체칩(40)의 그라운드 신호가 골드게이트(17), 그라운드용 비아홀(20), 회로패턴(25), 돌기부(22)를 통하여 금형으로 유출되도록 되어 있다.In addition, since the ground circuit pattern 25 is formed to the ground via hole 20 connected to the gold gate 17 when the ground protrusion 22 extends, the ground signal of the semiconductor chip 40 is generated. The gold gate 17, the ground via hole 20, the circuit pattern 25, and the protrusion 22 flow out into the mold.

여기서, 상기 두개의 리드선(51,52)은 버스라인(50)보다 두께 및 폭이 작고, 상기 두개의 리드선(51,52)이 합치된 하나의 리드선(53)은 상기 두개의 리드선(51,52)보다 두께 및 폭이 작게 형성됨으로써, 도금 작업시 상기 두개의 리드선(51,52)이 합치된 리드선(53)에는 과전류가 흐르게 되어 그라운드용 돌기부(22)의 도금형성시 그 두께가 솔더마스크(15)보다 두껍게 형성된다.Here, the two lead wires 51 and 52 are smaller in thickness and width than the bus line 50, and one lead wire 53 in which the two lead wires 51 and 52 coincide is the two lead wires 51, Since the thickness and width are smaller than those of 52, overcurrent flows through the lead wires 53 in which the two lead wires 51 and 52 coincide during the plating operation, and the thickness of the solder mask when the ground protrusion 22 is plated is formed. It is formed thicker than (15).

이러한 그라운드용 돌기부(22)는 회로패턴의 본드핑거(도시되지 않음), 골드게이트(17) 및 그라운드링(25)을 도금시 동시에 실시함으로써 종래와 같이 별도의 추가 공정이 필요없게 된다.The ground protrusion 22 may simultaneously perform a bonding process (not shown) of the circuit pattern, the gold gate 17 and the ground ring 25 at the same time as plating, thereby eliminating the need for a separate additional process as in the prior art.

또한 상기 그라운드용 돌기부(22)는 금(Au)으로 형성하였는데 이것에만 한정되지 않고 다양한 도전성 금속을 이용할 수 있다.In addition, the ground protrusion 22 is formed of gold (Au), but not limited thereto, and various conductive metals may be used.

이와 같이 하여, 상기한 그라운드용 돌기부(22)는 인쇄회로기판(10)의 저면으로 돌출되어 있음으로써, 몰딩 작업시 금형의 표면에 접촉되고, 따라서 반도체칩(40)이나 인쇄회로기판(10)의 회로패턴(12) 등에서 유기되는 정전기를 금속성의 금형쪽으로 모두 유출시키게 된다. 즉, 반도체칩(40)이나 인쇄회로기판(10)의 회로패턴(12)들은 모두 골드게이트(17)에 연결되어 있음으로서, 상기 반도체칩 등으로부터 유기되는 정전기는 골드게이트(17), 그라운드용 비아홀(20), 회로패턴(25), 돌기부(22), 금속성의 금형을 통하여 외부로 유출됨으로써 정전기의 급격한 방전에 의한 반도체칩(40)의 파괴를 미연에 방지할 수 있게 된다.In this way, the above-described ground protrusion 22 protrudes to the bottom surface of the printed circuit board 10, thereby contacting the surface of the mold during the molding operation, and thus the semiconductor chip 40 or the printed circuit board 10. All of the static electricity induced in the circuit pattern 12, etc. of the outflow to the metallic mold. That is, since the circuit patterns 12 of the semiconductor chip 40 or the printed circuit board 10 are all connected to the gold gate 17, the static electricity induced from the semiconductor chip or the like is used for the gold gate 17 and the ground. By leaking to the outside through the via hole 20, the circuit pattern 25, the protrusion 22, and the metallic mold, it is possible to prevent the semiconductor chip 40 from being destroyed by the sudden discharge of static electricity.

여기서, 상기 그라운드용 돌기부(22)는 인쇄회로기판(10)의 저면에 형성하였지만, 상면에도 형성할 수 있으며, 그 위치는 봉지재가 몰딩되는 영역의 외주연으로 함이 바람직하다.Here, the ground protrusion 22 is formed on the bottom surface of the printed circuit board 10, but may also be formed on the upper surface, the position is preferably the outer periphery of the region in which the encapsulant is molded.

이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기에만 한정되지 않으며, 본 발명의 범주와 사상을 벗어나지 않는 범위내에서 당업자에 의해 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto, and various modifications may be made by those skilled in the art without departing from the scope and spirit of the present invention.

본 발명에 의한 정전기 방지를 위한 반도체패키지용 인쇄회로기판에 의하면, 차후에 제거되는 버스라인에서 두개의 리드선을 인출하여, 하나의 리드선으로 합치고, 그 합쳐진 부분에는 솔더마스크를 개방하여 도금을 실시함으로써, 도금시 발생되는 과전류에 의해 상기 솔더마스크의 두께보다 두껍게 그라운드용 돌기부가 형성되게 한다.According to the printed circuit board for the semiconductor package for preventing static electricity according to the present invention, by drawing the two lead wires from the bus line to be removed later, combine them into a single lead wire, the soldered part is opened by plating the combined parts, The overcurrent generated during plating causes the ground protrusion to be formed thicker than the thickness of the solder mask.

따라서, 한번의 도금작업으로 일정 두께 이상의 그라운드용 돌기부를 용이하게 형성할 수 있고, 또한 상기 그라운드용 돌기부의 두께를 용이하게 제어하는 동시에 수율이 대폭 향상되는 효과가 있으며, 또한 반도체칩의 정전기를 금형으로 용이하게 유출시킴으로써 반도체칩의 파손을 미연에 방지할 수 있는 장점이 있다.Therefore, it is possible to easily form the ground protrusions having a predetermined thickness or more by one plating operation, and also to easily control the thickness of the ground protrusions, and to greatly improve the yield, and also to prevent static electricity from the semiconductor chip. By easily flowing out, the damage of the semiconductor chip can be prevented in advance.

Claims (3)

수지기판과; 상기한 수지기판의 상면에 반도체칩이 실장될 수 있도록 형성된 칩탑재부와; 상기한 칩탑재부의 사방에 형성된 회로패턴과; 상기한 회로패턴을 보호하도록 수지기판의 상부에 코팅된 솔더마스크와; 상기한 회로패턴을 수지기판의 상하부로 연결하는 비아홀과; 상기한 비아홀에 의해 수지기판의 하부로 연결되어 솔더볼이 융착될 수 있는 영역을 형성하는 솔더볼 랜드와; 상기한 수지기판의 하부에 솔더볼 랜드를 제외한 영역에 코팅된 솔더마스크와; 상기 반도체칩을 보호하기 위해 칩탑재부쪽을 향하여 수지기판상에 형성된 골드 게이트로 이루어진 인쇄회로기판에 있어서,A resin substrate; A chip mounting part formed on the upper surface of the resin substrate so that a semiconductor chip can be mounted; Circuit patterns formed on all sides of the chip mounting portion; A solder mask coated on the resin substrate to protect the circuit pattern; A via hole connecting the circuit pattern to the upper and lower parts of the resin substrate; A solder ball land connected to a lower portion of the resin substrate by the via hole to form an area in which solder balls may be fused; A solder mask coated on a region of the resin substrate except for solder ball lands; In the printed circuit board made of a gold gate formed on the resin substrate toward the chip mounting portion to protect the semiconductor chip, 상기 인쇄회로기판의 회로패턴에 연결되어 있되, 차후 제거되는 버스라인에는 수지기판상으로 두개의 분기된 리드선이 형성되어 있고, 상기 두개의 리드선은 다시 하나의 리드선으로 합치된채 그라운드 신호가 출력되는 그라운드용 회로패턴에 연결되어 있으며, 상기 두개의 리드선이 합치된 부분에는 솔더마스크가 개방된채 그 솔더마스크의 두께보다 두껍게 그라운드용 돌기부가 형성됨으로써, 몰딩중 상기 도금영역이 금형에 접촉되도록 하여 반도체칩 및 인쇄회로기판 등에 형성되는 정전기가 금형쪽으로 유출되도록 한 것을 특징으로 하는 정전기 방지를 위한 반도체패키지용 인쇄회로기판.The bus line, which is connected to the circuit pattern of the printed circuit board, is subsequently removed, and two branched lead lines are formed on the resin substrate, and the two lead wires are matched with one lead line again to output a ground signal. A ground protrusion is formed at a portion where the two lead wires coincide with the solder mask and is thicker than the thickness of the solder mask so that the plating region contacts the mold during molding. Printed circuit board for a semiconductor package for preventing static electricity, characterized in that the static electricity formed in the chip and the printed circuit board to be discharged to the mold. 제1항에 있어서, 상기 두개의 리드선은 버스라인보다 두께 및 폭이 작고, 합치된 하나의 리드선은 상기 두개의 리드선보다 두께 및 폭을 작게 함으로써, 도금시 합치된 리드선에서 과전류가 흐르게 하여 도금 두께가 두꺼워지도록 한 것을 특징으로 하는 정전기 방지를 위한 반도체패키지용 인쇄회로기판.2. The method of claim 1, wherein the two leads are smaller in thickness and width than the bus lines, and the one matched lead is smaller in thickness and width than the two leads, so that an overcurrent flows in the matched leads during plating. Printed circuit board for a semiconductor package for preventing static electricity, characterized in that the thickened. 제1항에 있어서, 상기 그라운드용 돌기부는 금으로 형성된 것을 특징으로 하는 정전기 방지를 위한 반도체패키지용 인쇄회로기판.The printed circuit board of claim 1, wherein the ground protrusion is formed of gold.
KR1019980036897A 1998-05-27 1998-09-08 Printed Circuit Boards for Semiconductor Packages to Prevent Static KR100298689B1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019980036897A KR100298689B1 (en) 1998-09-08 1998-09-08 Printed Circuit Boards for Semiconductor Packages to Prevent Static
JP10334667A JP3020201B2 (en) 1998-05-27 1998-11-25 Molding method of ball grid array semiconductor package
JP10346145A JP2997746B2 (en) 1998-05-27 1998-12-04 Printed circuit board
US09/240,422 US6246015B1 (en) 1998-05-27 1999-01-29 Printed circuit board for ball grid array semiconductor packages
US09/240,423 US6214645B1 (en) 1998-05-27 1999-01-29 Method of molding ball grid array semiconductor packages

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KR1019980036897A KR100298689B1 (en) 1998-09-08 1998-09-08 Printed Circuit Boards for Semiconductor Packages to Prevent Static

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100559512B1 (en) * 2000-07-08 2006-03-10 앰코 테크놀로지 코리아 주식회사 Circuit board and mold for semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100559512B1 (en) * 2000-07-08 2006-03-10 앰코 테크놀로지 코리아 주식회사 Circuit board and mold for semiconductor package

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