KR20000016804A - Image pick-up method and apparatus using image pick-up method - Google Patents

Abstract

PURPOSE: An image pick-up apparatus is provided which can achieve a decrease in cost and in circuit size and a decrease in dissipation power. CONSTITUTION: In a recording mode, YUV data of one frame output at a given period from a YUV signal processing circuit (11) is periodically written to a DRAM (14) through a DRAM transfer route via a DMA(Direct Access Memory) controller (12). The writing-in of YUV data of one frame is done by a predetermined map. The DMA controller allows YUV data which is periodically developed onto the DRAM to be read out/output from the YUV signal processing circuit to a video encoder (15) in a way to correspond to the image map. Thus, in accordance with the periodic updating, on the DRAM of image information picked up by a CCD(Charge Coupled Device) (6), the video encoder creates a video signal on the basis of automatically updated information and a current image can be displayed on a display device (16) without using a VRAM controller and VRAM.

Description

Image pickup method and apparatus using this method

The present invention relates to an image pickup device, an image pickup method, and a display method for picking up an image of an object and performing and recording the display based on the image data.

The structure and operation of the conventional image pickup apparatus are configured to select a recording mode for picking up and recording an image of an object and a reproduction mode for reproducing and displaying already picked up image data.

In the recording mode, the image data picked up from the CCD (charge coupling element) are handled in the following sequence.

First, the CCD generates a photoelectric conversion output as one corresponding image for the predetermined cycle. This output is sampled / held by the sampling / holding circuit and converted into digital data by the A / D converter. This digital signal is converted by the YUV signal processing circuit into a multiplexed signal including digital luminance and color difference (a signal containing at least one luminance signal and color difference, hereinafter referred to as YUV data), and DMA (direct storage access) Output to the control device.

The DMA controller writes the input YUV data into an internal buffer and DMA-transmits this data to the DRAM (dynamic ram) via the DRAM I / F (dynamic ram interface).

After this YUV data is DMA-transmitted to the DRAM, the CPU can read this YUV data from the DRAM through the DRAM I / F and write this data to the VRAM (video RAM) through the VRAM controller.

A digital video encoder (hereinafter simply referred to as video encoder = VE) periodically reads YUV data from the VRAM through a VRAM controller, from which the video signal is generated and output to the display device. By doing so, the display device displays an image based on the image information just obtained from the CCD.

With the current image displayed on the display, the shutter key is activated and triggers at a timing at which the user records / stores it. Following this trigger, after DMA-transferring YUV data of one image just obtained from the CCD to the DRAM (dynamic RAM), the CPU (central processing unit) blocks the passage from the CCD to the DRAM and executes the shift in the recording / saving state. Let's do it. In this write / preserve state, the CPU can read one frame of YUV data written to the DRAM through the DRAM I / F, and write this data to a compander circuit. The CPU can read code data compressed in the comparator circuit from the comparator circuit and write the data to a flash memory composed of a nonvolatile memory. With one frame of compressed-processed YUV data and fully compressed data written to flash memory, the CPU can resume data transfer from the CCD to the DRAM.

In the state of the reproduction mode, the image data stored in the flash memory is displayed on the display device in the following sequence.

When the image pickup device is switched from the recording mode to the playback mode, the CPU blocks the passage from the CCD to the DRAM, and reads the code data of one specific frame from the flash memory as the user presses an image selection key or the like. Can be recorded in the comparator circuit. The CPU then executes decompression processing by the compensator circuit, and develops one frame of YUV data into the VRAM through the VRAM controller. The video encoder then generates a video signal from one frame of YUV data enveloped in the VRAM, which is displayed on the display.

However, in such a conventional digital camera, one frame of YUV data is developed in the DRAM in the recording and playback mode as described above, and at each completion of the YUV data development in the DRAM, the YUV data is video. It is transferred from DRAM to VRAM by the encoder and displayed. That is, since the display of an image is performed while using DRAM as an operating memory and VRAM as a display memory, these different memories for operation and display exist, thus resulting in an increase in cost and circuit size. do. In addition, if the two memories are present separately, at each update of the image information obtained from the CCD in the recording mode and at each extension of the compressed YUV data in the playback mode, the YUV data developed in the DRAM must be transferred to the VRAM. And thus causes an inevitable loss of power.

The entire contents of Japanese Patent Application No. 9-118764, filed April 22, 1997, are incorporated herein by reference.

1A is a schematic diagram illustrating an appearance of a digital camera according to an aspect of the present invention.

1B is a schematic diagram showing a digital camera viewed from another direction.

2 is a schematic block diagram of a digital camera.

3 is a schematic block diagram showing the details of the DMA controller and its connection with other blocks;

4 is a diagram showing an image map of YUV data corresponding to one frame.

5A to 5D show the relationship between the YUV data recording line of the YUV signal processing circuit and the YUV data reading line of the video encoder, respectively.

Fig. 6 is a diagram showing the relationship between the YUV data write line of the YUV signal processing circuit and the YUV data read line of the video encoder in the second aspect of the present invention.

Fig. 7A is a diagram showing a movement path of data in a recording mode.

Fig. 7B is a diagram showing a movement path of data when receiving an image in the recording mode.

Fig. 7C is a diagram showing a movement path of data in the reproduction mode.

<Explanation of symbols for main parts of drawing>

1: body 2: display 3: lens

4: shutter key 5: guitar key 6: CCD

7: Time Generator 8: Vertical Driver 9: Sample / Hold Circuit

10: A / D converter 11: YUV signal processing circuit 12: DMA controller

13: comparator circuit 14: DRAM 15: digital video encoder

16: Display 17: CPU 18: Flash memory

19: Key section 20: First-in first-out 21: DMA control circuit

22: DRAM interface 23: second first in first 24: third first in first

Accordingly, it is an object of the present invention to provide an image pickup apparatus and an image pickup method capable of achieving a small size circuit and a reduction in cost and a reduction in power loss.

Preferred aspects of the invention include: image pick-up means for picking up an image of an object and generating a corresponding signal;

Generating means for generating image data of the object image based on this signal generated from the image pickup means;

Recording means for recording image data generated from the generating means in response to a pickup operation;

Display control means for displaying an object image based on the image data generated from the generating means, and displaying the image in response to a reproduction operation based on the image data stored in the recording means;

Memory means for operation; And

Transmission means for transferring the image data from the generating means and the recording means to the memory means in the predetermined format while transferring the image data in the predetermined format to the display control means.

By doing so, the cost and the circuit size can be reduced, and furthermore, it is also unnecessary to perform data transfer to the VRAM, so that the loss of power loss can be avoided. In addition, the image stored in the storage memory can be displayed on the display screen of the display device.

Another preferred aspect of the present invention comprises: image pickup means for picking up an image of an object and generating image data corresponding to the object;

Temporary storing memory for temporarily storing image data from the image pickup means;

Display means for displaying image data of the temporary storage memory; And

And transfer means for transferring the image data of the image pickup means to the temporary storage memory and the display means.

Therefore, the cost and the circuit size can be reduced, and it is also unnecessary to perform data transfer to the VRAM, so that the loss of power loss can be avoided. In addition, since this data transmission does not go through the control means, there is a small load on the control means.

Another preferred aspect of the invention is an image pick-up element for picking up image data;

Temporary storage memory for temporarily storing image data from the image pickup element;

A compression circuit for compressing image data stored in the temporary storage memory;

A preservation memory for storing the image data compressed by the compression circuit;

Display means for displaying image data stored in the temporary storage memory; And

And transfer means for transferring the image data in the temporary storage memory to the compression circuit and the display means.

Therefore, the image stored in the storage memory can be displayed on the display screen of the display device without using the VRAM control device and the VRAM of the conventional device. In addition, it is possible to reduce the data transmission through the control means, so that less load is placed on the load.

Another preferred aspect of the invention comprises the steps of: picking up image data by means of an image pickup element (S1);

Storing image data from the image pickup element in the temporary storage means (S2); And

Reading the image data of the temporary storage memory and transmitting the image data to the display means (S3, S4) during the overlapping of the above steps.

Therefore, the cost and the circuit size can be reduced, and it is also unnecessary to perform data transfer to the VRAM, so that the loss of power loss can be avoided. Since this data transmission does not go through the control means, a small load is placed on the control means.

Another preferred aspect of the invention comprises the steps of: picking up image data by means of an image pickup element (S1);

Storing image data from the image pickup element in the temporary storage memory (S2);

Compressing the image data stored in the temporary storage memory by a compander circuit (S5);

Storing image data compressed by the comparator circuit in a storage memory (S6); And

And displaying (S8) the image data stored in the temporary storage memory by the display means while being overlapped with the step (S5).

Therefore, the image stored in the storage memory can be displayed on the display screen of the display device without using the VRAM control device and the VRAM of the conventional device. In addition, it is possible to reduce the data transmission through the control means, so that less load is placed on the control means.

Yet another preferred aspect of the present invention comprises the steps of: transmitting the compressed image data from the storage memory to the expander circuit (S9); And

And transmitting the image data extended by the decompression circuit to the temporary storage memory and transmitting the image data stored in the temporary storage memory to the display means (S10-S12).

Therefore, the image stored in the storage memory can be displayed on the display screen of the display device without using the VRAM control device and the VRAM of the conventional device. In addition, since data transmission through the control means can be reduced, less load is placed on the control means.

One embodiment of the present invention will be described below with reference to the drawings. 1A and 1B are outline views showing a digital camera according to an aspect of this embodiment. As shown in these figures, the digital camera has a display screen 2 on the back of the body 1, a lens 3 on the front corner portion, and a shutter key 4 and an image selection key on the image face. It has a body 1 of rectangular parallelepiped configuration in which the keys are arranged.

2 is a block diagram of a digital camera according to an aspect of the present embodiment. The CCD 6 is arranged behind the lens 3 and driven by the time generator 7 and the vertical driver 8 to generate the photoelectric conversion output as a corresponding image at each given frequency. The photoelectric conversion output is sampled / holded by the sample / hold circuit 9 and converted into digital data by the A / D converter 10. The multiplexed signal including the digital luminance and the color difference (a signal including at least one luminance signal and the color difference signal, hereinafter referred to as YUV data) is controlled by the YUV signal processing circuit 11 to control DMA (Direct Memory Access). Is output to the device 12. The comparator circuit 13, the DRAM (dynamic ram) 14, and the video encoder 15 are connected to the DMA controller 12. The display device 16 having the display image screen 2 is connected to the video encoder 15. The CPU 17 and the flash memory 18 are connected to the DMA controller 12 via the bus line. The operation information is input to the CPU 17 from the key section 19 including the shutter key 4 and the other keys 5.

3 is a block diagram showing a connection state between the DMA controller 12 and the DMA controller 12 and other blocks. The YUV data output of the YUV signal processing circuit 11 is written to the first FIFO (first-in-first-out) 20 and DMA to the DRAM 14 via the DRAM I / F 22 by the DMA controller circuit 21. -Sent. In addition, by the DMA transfer from the DRAM 14 to the video encoder 15 via the DRAM I / F 22, the DMA control circuit 21 writes YUV data to the second FIFO 23, and the video encoder ( Output in response to the read-control signal of 15). In addition, the DMA control circuit 21 extracts 8 × 8 basic blocks of YUV data from the DRAMs 14 through the DRAM I / F 22 and extracts these blocks by the DMA transfer to the third FIFO 24. To be sent). The DMA control circuit 21 then outputs YUV data from the third FIFO 24 to the comparator circuit 13 in accordance with the read control signal of the comparator circuit 13.

Regarding the aspect of this embodiment arranged, the following will be described with respect to the data movement path in the recording mode with reference to Figs. 7A (S1-S4).

First, as described above, image data obtained from the CCD is made corresponding to YUV data of one frame output from the YUV signal processing circuit 11 at a given frequency (S1). This data is recorded in the DRAM 14 through the DMA controller 12 in a periodic manner by the DMA transfer (S2).

In addition, the DMA controller 12 periodically reads YUV data developed from the YUV signal processing circuit 11 into the DRAM 14 from the DRAM 14 in a manner corresponding to an image map. The data is transmitted to the video encoder 15 (S2-S3). In accordance with the periodic update on the DRAM 14 of the image information obtained by the CCD 6, the video encoder 15 automatically generates a video signal based on the updated information, so that the VRAM controller provided on the conventional apparatus And the current image can be displayed on the display screen 2 of the display device 16 without using the VRAM.

In this way, cost can be reduced, circuit size can be reduced, and power loss can be avoided since there is no need to execute data transfer to the VRAM.

Although a series of operations S1-S4 are made by the instructions of the CPU 17, this data does not pass through the CPU 17 so that it can move at high speed.

With respect to Fig. 7B, the passage where the data has moved will be described below when the operator presses the shutter key 4 on the digital camera at the imaging time, i.e., the recording mode (S1 to S4). The CPU 17 shifts to the image recording / hold state, and stops the DMA controller 12 from obtaining YUV data upon completion of the transfer of the frame from the YUV signal processing circuit 11 to the DRAM 14. At the same time as this stop, the comparator circuit 13 starts and the DMA controller 12 starts the compensator circuit 13 from the DRAM 14 in 8 × 8 basic block units corresponding to an image map of YUV data of one frame. DMA-transfer toward (S5). The CPU 17 continuously reads the compressed data generated in the comparator circuit 13 from the comparator circuit 13 and writes it to the flash memory 18 (S6).

At this time, also during data compression in the comparator circuit 13, the YUV data transfer S7 of the DMA controller 12 to the video encoder 15 can continue. In addition, it is also possible for the display device 16 to display the same image as the image information is compressed-processed by the video signal from the video encoder 15 (S8).

The difference from reading data from the comparator circuit 13 and writing data to the flash memory 18 is made by the DMA controller or the like under the command of the CPU 17.

In addition, in the playback mode, this data moves as shown in Fig. 7C. That is, the YUV signal processing circuit 6 and its progression step are set to the stopped state by the instruction of the CPU 17. In accordance with the operation of the image selection key among other keys by the operator, the sign data of the specific image is read from the flash memory 18 and written in the comparator circuit 13 (S9). Then, the data in 8x8 basic block units obtained by the decompression-processing of the comparator 13 is DMA-controlled by the DMA controller under the instruction of the CPU 17 in a manner corresponding to the image map for the DRAM 14. It is transmitted (S10). At the same time, the DMA controller 12 executes DMA-transfer to the video encoder 15 in a manner corresponding to the image map, whereby the expanded image is automatically displayed on the display screen 2 of the display device 16. do. Thus, in the same manner as described above, the image selected by the operation of the image selection key stored in the flash memory 18 is displayed on the display screen 2 of the display device 16 without using the VRAM control device and the VRAM of the prior art device. May be displayed on the screen.

The data read from the flash memory 18 and the data written to the comparator circuit 13 are different from those of the DMA controller or the like under the command of the CPU 17. Since the data does not go through the CPU 17, high-speed data movement is executed. Can be.

In an aspect of the invention, the periodic development area of the YUV data in the YUV signal processing circuit 11 into the memory area and the read area of the YUV data into the memory of the video encoder 15 are the same area on the DRAM 14. Matches with. However, since the frame development period of the YUV data in the YUV signal processing circuit 11 and the frame reading period of the YUV data in the video encoder 15 are not necessarily synchronized with each other, if the two periods access the same region in this way, The image display on the display device 16 often degenerates according to a periodic relationship as shown in Figs. 5A to 5D.

That is, when the development area of the YUV data in the YUV signal processing circuit 11 and the read area of the YUV data of the video encoder 15 are the same, FIGS. 5A to 5C show the YUV data recording line of the YUV signal processing circuit 11. And the YUV data read line of video encoder 15 based on time. Here, the line means the horizontal line of the image, the horizontal line of the image is indicated by the vertical axis and the time is set on the abscissa. In addition, in Figs. 5A to 5C, the dashed lines show the development of the YUV signal processing circuit 11, and the interval between adjacent dashed lines is the development period. In addition, the solid line corresponds to the reading of the first field of the video encoder 15 and the dotted line corresponds to the reading of the second field. Thus, the spacing between adjacent solid lines and the spacing between adjacent dashed lines is the reading period of video encoder 15. In addition, in Figs. 5A to 5C, the relationship between the development period of the YUV signal processing circuit 11 and the reading period of the video encoder 15 is the development period in Fig. 5A where development period = reading period. 5 corresponds to the reading cycle and the development period to the reading cycle of FIG. 5C.

5A and 5C result in the intersection between the development line and the read line at each time t1, t2 and t3, and in FIG. 5B with the development line at each time t1, t2, t3 and t4. There is an intersection between the read lines. In this way, the occurrence of the intersection point between the development line and the read line results in a mixed state between the updated images before and after the development frame in the field (1/2 frame) displayed on the display screen 2. Means that. If the image of any moving object is illuminated, the displayed object image is displayed on the display screen.

As shown in Fig. 5D, when there is an intermittent relationship between the development timing of the YUV signal processing circuit 11 and the read timing of the video encoder 15, intersection points t1 and t2 occur, but this is not the case. The time interval is extended and a displacement occurs on the displayed object image as in the case of FIGS. 5A-5C. However, this displacement is not significant for the eyes' senses. Although the outer surface of the CCD 6 or the YUV signal processing circuit 11 is driven by the time generator 7 to obtain such an intermittent relationship, the same area is made by the YUV signal processing circuit 11 and the video encoder 15. It is possible to inhibit displacement on the displayed object image as soon as it is accessed and picked up the image from the moving object.

6 shows an aspect of another embodiment of the present invention as any displacement on the displacement object image is removed using two regions. In other words, the relationship between the development period of the YUV signal processing circuit 11 and the reading period of the field (1/2 frame) of the video encoder 15 is set to the development period &gt; In addition, the area A and the area B are provided in the DRAM 14, and by the DMA control circuit 21, the YUV signal processing circuit 11 performs alternating development on the areas A and B. As shown in FIG. At this time, the YUV signal processing circuit 11 generates the area control signal S in the DMA control device circuit 21 which rises upon completion of the development on the area A and falls upon completion of the development on the area B. The video encoder 15 executes a signal read from the area B when the area control signal S is in the low-level state, and a signal read from the area A when the area control signal S is in the high-level state. By doing so, no intersection point occurs between the development line and the read line on the same area, and any displacement of the object displayed on the display screen generated when the moving object image is taken can be eliminated.

As described above, the image pickup method and apparatus according to the present invention can achieve a small circuit, a cost reduction, and a power loss, and thus the use thereof in the future is noted.

Claims (21)

Image pick-up means for picking up an image of the object and generating a corresponding signal; Generating means for generating image data of the object image based on the signal generated from the image pickup means; Recording means for recording image data generated from the generating means in response to a pickup operation; Display control means for displaying an object image based on the image data generated from the generating means, and for displaying an image based on the image data stored in the recording means in response to the reproducing operation; Memory means for operation; And And transfer means for transferring image data from the generating means and the recording means to the memory means in the predetermined format while transferring the image data from the memory means to the display control means in the predetermined format. The method of claim 1, The memory means includes a pair of areas in which image data generated by the generating means are alternately recorded, and the transmitting means transmits the image data on one area of the paired areas set to the unrecorded state to the display control means. Image pickup apparatus, characterized in that. Image pickup means for picking up an image of the object and generating image data corresponding to the object; Temporary storing memory for temporarily storing image data from the image pickup means; Display means for displaying image data of the temporary storage memory; And And transfer means for transferring the image data of the image pickup means to the temporary storage memory and the display means. The method of claim 3, wherein And image pickup means, video encoder and control means for controlling the transmission means. The method of claim 3, wherein The transfer means transfers the data to the temporary storage memory to alternately record the data of the image picked up in the pair of areas of the temporary storage memory, and the unpaired state of the area pair to transfer the imaged data to the display means. And image data is read from the raw memory. The method of claim 3, wherein And a video encoder for encoding the data of the temporary storage memory into a video signal and transmitting the video signal to the display means. An image pick-up element for picking up image data; Temporary storage memory for temporarily storing image data from the image pickup element; A compression circuit for compressing image data stored in the temporary storage memory; A preservation memory for storing the image data compressed by the compression circuit; Display means for displaying image data stored in the temporary storage memory; And And transfer means for transferring the image data in the temporary storage memory to the compression circuit and the display means. The method of claim 7, wherein And control means for controlling the transmission means and for transmitting the image data compressed by the compression circuit to the storage memory. The method of claim 7, wherein And a video encoder for encoding the image data stored in the temporary storage memory into a video signal and supplying the signal to the display means. A storage memory for storing compressed image data; An expanding circuit for expanding the compressed image data of the storage memory; A temporary storage memory for storing image data expanded by the decompression circuit; Display means for displaying data encoded by the video encoder; And And transfer means for transferring the image data extended by the decompression circuit to the temporary storage memory and the display means. The method of claim 10, And a control means for controlling the transfer means and transferring the image data of the storage memory to the decompression circuit. The method of claim 10, And a video encoder for encoding the image data stored in the temporary storage memory into a video signal and supplying the signal to the display means. The method of claim 10, The transfer means further transfers the picked-up data to the temporary storage memory, alternately writes the data to a pair of areas in the temporary storage memory, and reads image data from the memory of the unrecorded area of the area pair. And transmitting the image data to the display means. Picking up image data by the image pickup element (S1); Storing image data from the image pickup element in a temporary storage memory (S2); And And (S3, S4) reading the image data of the temporary storage memory and transmitting the image data to the display means while the step is duplicated. The method of claim 14, The steps S3 and S4 include: encoding image data from the temporary storage memory by the video encoder (S3); And And transmitting the data encoded by the video encoder to the display means (S4). Picking up image data by the image pickup element (S1); Storing image data from the image pickup element in a temporary storage memory (S2); Compressing the image data stored in the temporary storage memory by a compander circuit (S5); Storing image data compressed by the comparator circuit in a storage memory (S6); And And (S8) displaying the image data stored in the temporary storage memory by the display means while the step (S5) is duplicated. The method of claim 16, And (S7) for encoding the image data stored in the temporary storage memory by the video encoder. Transmitting the compressed image data from the storage memory to the companding circuit (S9); And And transmitting the image data extended by the comparator circuit to the temporary storage memory, and transmitting the image data stored in the temporary storage memory to the display means (S10-S12). The method of claim 18, The step of transmitting the image data extended by the comparator circuit to the temporary storage memory reads the image data extended by the expander circuit into the transmission means, and transmits this data to the temporary storage memory (S10). Image recording / display method, characterized in that. The method of claim 18, The step (S9) of sending the compressed image data from the storage memory to the compensator circuit reads the compressed image data from the storage memory into the control means and transmits this data to the decompression circuit (S9). Image recording / display method comprising a. The method of claim 18, The steps S10-S12 of transmitting the image data stored in the temporary storage memory to the display means read the image data stored in the temporary storage memory into the transmission means and transmit the data to the encoding means ( S11).