4 497 3 9 A7 經滴部中央標準局員工消費合作社印" B7五、發明説明（1 ) [產桊上之利用領域] 本發明為有關一種攝影裝置、攝影方法及顯示方法， 其係對目標景物攝影後，依據其圈像資枓做顯示或記錄 者0 [普知之技術] 首先，說明先前之攝影裝置的構成及其動作。 攝影裝置是具有可選擇對目標景物攝影後予Μ記錄的 記錄模式；和將已被記錄的攝影資料予Μ再生顯示的再 生模式可予選擇之構成。 而在記錄模式的狀態中，由電荷耦合器件〔Κ下稱CCD (Charge Coupled device)〕所攝取的攝影資料，會被 依如下之順序處理。 首先，CCD會在每一定周期輸出一畫面份的光電轉換 輸出。該输出是由取樣保持電路將其取樣保持，由類比 /數位（Μ下稱A/D )轉換器轉換為數位資料並由至少 含有輝度信號與色差信號之信號（以下稱YUV )信號處 理電路轉換為數位式的含有輝度和色差之YiJV資料，输 出於直接記憶體存取〔Μ下稱DMA(direct meiBory access]控制器。 DMA控制器將所輸入的上述YUV資料寫入於其内部的 鍰衝器，並經由動態随機存取記憶體接口 〔M下稱DRAMI/F (dynamic randoat access menory interface)〕對動態 隨機存取記億體〔M下稱DRAMfdynaifiic random access memory)]做DMA轉送工作。 -3- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Λ4規枱（210X297公犛） 經濟部中央標隼局員工消費合作社印^ 4497 3 9_B7__五、發明説明（2 ) 中央處理機（M下稱CPU)於上述YUV資料，MDHA 轉送於DRAM完了之後，經由DRAMI/F將該YUV資料從 DRAM讓出，經由視頻随機存取記憶體（M下稱VRAM)倥 制器寫人於V R A Μ。 接著，數位視頻煸碼器（Κ下稱VE)將上述YUV資料 經由VRAM控制器從VRAM周期性的謓出，由這些資料產生 視頻信號，輪出於顯示裝置。由此，在顯示裝置上可顯 示Μ當時由CCO攝取的圖像資訊為依據之圖像。 而在於這種當時的圖像被顯示於顯示裝置上之狀態下 ,使用者在於所要記錄保存的時刻操作快門鍵，使其產 生觸發脈衝。於是CPU就按照該觸發脈衝，在當時從CCD 擷取的一盡面份之YUV資料對DRAM的DMA轉送完了之後 ，停it C C D到D R A Μ之路徑，轉移到記錄保存之狀態。在 該記錄保存狀態時，CPU將寫人在DRAM的一畫格份之YUV 資料經DRAM I/F譲出，寫入於壓縮擴展電路.而將壓縮 擴展電路所壓縮的符號資料，從該壓縮擴展電路讀出， 寫入於非易失性記憶體之瞬時記憶體。然後，隨著一盡 格份的YUV資料的壓縮處理及全壓縮資料寫入於瞬時記 憶體之终了，CPU再開始將資料由CCD轉送於DRAM。 又，在再生横式狀態時，會將記錄在瞬時記憶體的圖 像資料，依如下之順序顯示於顯示裝置。 攝影裝置從記錄模式被轉換到再生模式時，C P U會將 CCD到DRAM的路徑停止，按照使用者所按下的圖像選擇 鐽時，從瞬時記憶體謓出特定的一畫格份之符號資料寫 4 — (請先閲讀背面之注意事項再填寫本頁 訂 本紙張尺度適用中國國家標隼（〔阳）以規枋（210>；297公釐） 4 4 9 7 3 9 ΑΊ Β7五、發明説明（々） 入於壓縮擴展電路，在壓縮擴展電路做擴展處理，並經 由VRAM控制器，將一番格份的YUV資料展開於VRAM,接 箸，視頻编碼器由展開在VRAM的一盡格份之YUV資料， 産生視頻信號，在顯示裝置上進行顯示。 [發明欲解決之問題1 然而，像這種以往的數位式攝影機中，如上述之在於 記錄模式及再生模式時，是將一畫格份的γυν資料展開於 DRAM,每於該YUV資料展開於DRAM完了之後，將該YUV 資料由DRAM轉送於VRAM,由視頻编碼器讀出VRAM的YUV 資料，以進行顯示。即，將M A Μ作為作業用的記億體使 用，並將VRAM—面作為顯示用的記憶體使用，一面進行 圖像的顯示，因而作業用的記憶體和顯示用的記憶體是 梅別的存在，會招致成本的增加及電路規模的大型化 又，有兩個記憶體値別的存在時，在記錄模式中，對於 由CCf)所擷取的圖像資訊之更新，或在再生模式中，每 於將所壓縮的OV資料擴展時，必須將展開在DRAM的YUV 資料轉送到VRAM,其結果是不可避免的會産生消耗電力 之損失。 [發明之解決手段] 本發明之理想形態之一是包含： 對目標景物攝影，以産生對應於目標景物影像的信號 之攝影裝置；依據該攝影裝置所産生的信號，作成上述目 標景物影像的圖像資料之作成裝置；按照擷取操作，将上 述作成裝置所作成的圖像資料予以記錄之記錄裝置；依據 (請先閱讀背面之注意事項再填苟本I) Λ^·- 訂 本纸张尺度適州屮:標绛（) Λ4现梠（210Χ297公f ) 4 4 9 7 3 9 A7 B7 經濟部中央標準局員工消費合作社印^ 五、發明説明（ 4 ) 1 1 上 述 作 成 裝 置 所 作 成 的 画 像 資 料 » 使 標 景 物 影 像 顯 示 1 1 I 或 按 昭 再 生 操 作 » 使 記 錄 在 上 述 之 記 錄 裝 置 的 依 據 圖 1 ! 像 資 料 之 圖 像 顯 示 之 顯 示 控 制 裝 置 ; 作 業 用 記 憶 裝 置 ; 請 1 I 1 以 及 Μ 讀 ! 背 1 將 上 述 作 成 裝 置 及 上 述 記 錄 裝 置 來 的 圖 像 資 料 以 所 定 Τ& 之 格 式 轉 送 於 上 述 作 業 用 記 憶 裝 置 1 並 由 該 記 憶 裝 置 將 上 注 意 1 事 1 述 圖 像 資 料 Μ 上 述 格 式 轉 送 於 上 述 顯 示 控 制 裝 置 之 轉 送 項 再 1 1 裝 置 者 〇 填 寫 本 1 由 此 J 不 僅 可 減 低 成 本 和 壓 縮 電 路 規 模 f 且 不 必 將 資 頁 1 料 轉 送 到 V R A Μ 而 可 迴 避 消 耗 電 力 之 損 失 〇 又 也 可 不 必 1 用 到 以 注 裝 置 所 具 備的VRAM控制器或VRAM • 仍 可 將 儲 存 1 在 保 存 用 記 憶 體 的 圖 像 顯 示 於 顯 示 裝 置 之 顯 示 晝 面 上 0 1 訂 又 » 本 發 明 之 另 —' 理 想 形 態 是 包 含 ： ! 1 對 g 標 景 物 攝 影 4 以 產 生 對 應 於 S 標 景 物 影 像 的 圃 像 1 1 資 料 之 攝 影 裝 置 t 將 由 上 述 攝 影 裝 置 來 的 圆 圖 像 資 料 暫 畤 1 I m 存 之 暫 時 儲 存 記 憶 體 * 將 上 述 暫 時 儲 存 B 憶 體 的 圖 像 1 賁 料 顯 示 之 顯 示 裝 置 ♦ 及 將 上 述 攝 影 裝 置 的 圖 像 資 料 轉 送 於 上 述 暫 時 儲 存 記 憶 體 和 上 述 顯 示 裝 置 之 轉 送 裝 置 者0 1 由 此 » 不 僅 可 減 低 成 本 和 m 減 電 路 規 模 9 且 ) 不 必 將 t 資 料 轉 送 到 VRAM 9 而 可 m 避 消 耗 電 力 之 損 失 〇 又 1 也 可 1 1 不 必 經 xW, m 控 制 裝 置 轉 送 資 料 t 因 而 可 減 少 控 制 裝 置 的 負 1 1 載 0 i 1 又 > 本 發 明 之 另 一 理 想 形 態 是 包 含 ； 1 ! 攝 取 阚 像 資 料 之 攝 影 元 件 » 將 由 上 述 攝 影 元 件 來 的 圖 1 I -6 1 1 1 1 本纸張尺度ii用中國國家標準（CNS ) Λ4規格（210X 297公梦） 449739 經消部中次標嗥局oil消贤合作印ϊ?< 五、發明説明（ ) 1 1 I 像 資 料 暫 時 儲 存 之 暫 時 儲 存 記 億 體 ; 將 儲 存 在 上 述 暫 時 1 1 I 記 憶 體 的 圖 像 資 料 加 以 壓 縮 之 壓 编 電 路 將 上 述 壓 缩 電 1 路 所 壓 縮 的 圓 像 資 料 予 以 保 存 之 保 存 用 記 億 體 ’· 將 儲 存 讀 先 1 i 在 上 述 暫 時 儲 存 記 億 jut m 的 _ 像 資 料 予 以 顯 示 之 顯 示 裝 置 閱 讀 1 背 I » 及 將 上 述 暫 時 儲 存 記 憶 體 的 圖 像 資 料 轉 送 於 上 逑 壓 縮 之 ! I 電 路 和 上 述 顯 示 裝 置 之 轉 送 裝 置 者 Ο 意 1 1 由 此 * 不 必 用 到 以 往 裝 置 所 具 備 的 VRAM控制器 或 VRAM 項 再 1 填 i ， ft 可 使 儲 存 在 保 存 用 記 憶 體 的 圖 像 顯 示 於 顯 示 裝 置 之 % 本 顯 示 盡 面 上 〇 又 * 可 減 少 經 過 控 制 裝 置 的 資 料 轉 送 5 因 頁 、· 1 1 而 Pj 減 少 控 制 裝 置 的 負 載 〇 1 1 又 * 本 發 明 之 % 一 理 想 形 態 是 包 含 1 1 保 存 被 壓 縮 的 圖 像 資 料 之 保 存 用 記 億 體 i 將 上 述 保 存 1 訂 用 記 億 體 的 被 壓 縮 資 料 擴 展 之 擴 展 電 路 將 上 逑 擴 展 電 ! 1 路 所 擴 展 的 圖 像 資 料 儲 存 之 暫 時 儲 存 記 億 體 * 將 上 述 視 1 ! 頻 m 碼 器 所 编 碼 的 資 料 顯 示 之 顯 示 裝 置 又 將 上 述 擴 展 1 I 電 路 所 擴 展 的 圖 像 資 料 轉 送 於 上 述 暫 時 儲 存 記 億 體 和 上 1 述 顯 示 裝 置 之 轉 送 裝 置 者 〇 由 此 » 不 必 用 到 以 注 裝 置 所 具 備 的 VRAM控制器或VRAM 1 1 也 可 使 儲 存 在 保 存 用 記 憶 體 的 圖 像 顯 示 於 顯 示 裝 置 之 1 1 I 顯 示 畫 面 上 〇 又 Ϊ 可 減 少 經 過 控 制 裝 置 的 資 料 轉 送 因 1 1 而 可 減 少 控 制 裝 置 的 負 載 〇 ! I 又 > 本 發 明 之 另 一 理 想 形 態 是 包 含 1 I 由 摄 影 元 件 攝 取 圖 像 資 料 之 步 驟 (S 1 ) * 使 上 述 攝 影 元 1 1 件 來 的 圖 像 資 料 儲 存 於 m 時 儲 存 記 憶 體 之 步 驟 { S2 ); 及 1 I - 7 1 1 1 i 4 497 3 9 A7 經濟部中央標準局員工消費合作社印製 B7五、發明説明（6 ) 與上述步驟（S2)併行的纊出上逑暫時儲存記憶體之圖像 資料，送到顯示裝置之步驟（S 3 , S 4 >者。 由此，不僅可減低成本和縮減電路規模，而且，不必 將賣料轉送到VRAM,而可迺遊消耗電力之損失。又，不 必經過控制裝置轉送資料，因而可減少控制裝置的負載， 又，本發明之另一理想形態是包含： 由攝影元件攝取圖像資料之步驟（S1);使上述攝影元 件來的圖像資料儲存於暫時儲存記憶體之步驟（S2);將 儲存在上述暫時儲存記憶體的圖像資料由壓縮擴展電路 壓縮之步驟（S5);使上述壓縮電路所壓縮的圖像資料儲 存於保存用記憶體之步驟（S6);及與上述步驟（S5)併行 的使儲存在上述暫時儲存記憶體之圖像資料，由顯示裝 置顯示之步驟（S8)者。 由此，不必用到Μ往裝置所具備的V R A Μ控制器或V R A Η ，也可使儲存在保存用記憶體的圖像顯示於顯示裝置上 之顯示畫面上。又，可減少經過控制裝置的資料轉送， 因而可減少控制裝置之負載。 又，本發明之另一理想形態是包含： 從保存用記憶體中，將被壓縮的圖像資枓轉送到擴展 電路之步软（S9);及將上述擴展電路所擴展的圖像資料 送到暫時保存記億體，並將儲存在暫時儲存記憶體的圖 像資料送到顯示裝置之步驟（S10〜S12)者。 由tt,可不必用到Κ往裝置所具備的VRAM控制器或 VRAM,也可使儲存在保存用記憶體的圖像顯示於顯示裝 (誚先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標牟（CNS ) Λ4規格（210X 297公釐） 4 497 3 9 A7 B7 五、發明説明（7 ) ---------'裝-- (請先閱讀背面之注意事項再填寫本頁) 置之顯示盡面上。又，可減少經過控制裝置的資料轉送 ，因而可減少控制裝置之負載。 {實施例） 參照圖面說明本發明之一實施例。 第1園Α及第1圖Β是有關本實施例的數位式攝影機之外 觀圖。如同圖中所示，數位式攝影機偽具有長方體形狀 之主體1 ,在該主體1的背面設有顯示盡面2 ,其前面 角落設有透鏡3 ,而其上面設有快門鍵4及由圖像選擇 键等構成之多數其他鍵5 。 第2圖是有關本實施例的數位式攝影機之構成方塊圖 。配置在上述透鏡3後方的CCD6受定時信號産生器7和 垂直驅動器8所驅動，於每一定周期，输出一畫面份的 光電轉換輪出。該光電轉換輪出由取樣保持電路9所取 樣和保持，由A/D (類比/數位）轉換器10轉換為數位資料 ，並經YUV信號處理電路11處理成為數位的含有輝度和 色差之YUV信號（至少含有輝度信號和色差信號之信號） ,輸出於DMA (直接記憶體存取）控制器12。該DMA控 制器12連接有壓縮擴展電路U、DRAM (動態随機存取記 憶體）14、及視頻编碼器15,而該視頻编碼器15並連 接於具上述顯示畫面2之顯示裝置16。上述DMA控制器 12並經由總線連接於CPU (中央處理機）17和瞬時記憶 -9 - 本紙张尺度ίΐ用屮W F.: ( d <'NS丨AWOS ( 2 I Ο 公釐） 449739 A7 B7 ______________ 五、發明説明（ί ) 醱丨8，CPU 17是從上述快門鍵4及其他鍵5所構成的鍵 部1 9輪入操作資訊》 第3圖是上述DMA控制器12及該DAM控制器12與其他 方塊的連接狀態之構成方塊_。上述Yl)V信號處理電路 11的YUV資料输出會被寫入於第一先進先出電路（以下 稱FIFO) 20 ,而且DMA控制電路21經由DKAMI/F (接口） 2 2被轉送到上迷〇1^»14。又^4控制電路21會结由 DRAHI/F 22從DRAH14以DMA轉送將YUV資料寫人於第二 FIF023,並按照視頻编碼器15的讀出控制信號，從第二 FIF023將YUV資料輪出。又DMA控制電路21會經由 DRAH/P 22從DRAM14裁出YUV資料的8X8基本處，以DMA 轉送到第三FIF024,並按照壓縮擴展電路13的讀出控制 信號，從第三FIF024將YUV資料輪出於暖縮擴展電路13。 有關如上述構成的本實施例中，以第7A_(S卜S4)説 明其在記錄模式時之資料移動路徑。 首先，如上迷由CCD所攝取的攝影資料，會被作成為 由γυν信號處理電路11以一定固期輪出的一畫面份之 YUV資料（S1),經由DMA控制器12以DMA轉送，周期性 的寫人於DRA14 (S2)。 又，DHA控制器12會從DRAM14將由YDV信號處理電路 11所固期性展開於DRAM14上之YUV資料，按照画像髑釀 -1 0 - 本紙认尺度泷川(rNS)A‘1¾格t M0 X2<?7公楚） (請先閱讀背面之注意事項再填鸡本頁) T ，-» 44973 9 a7 B7 五、發明说明（，） 出，輪出於視頻缠碼器15(S2-S3) β因而，隨箸CCD6所 攝取的圆像資訊在DRAM 14上的周期性之更新，視頻编碼 器15會自動的，以被所更新的資訊為基礎而産生視頻信 號。由此，不必用到以往裝置所具備的VRAM控制器或 VRAH,也可在顯示裝置16的顯示畫面2上顯示當時的圖 像（S4 ) 0 由此，不僅可減低成本和縮減電路規模，而且不必將 資料轉送到VRAM,因而可迺避消耗電力之損失。 又，這一連串的動作（S1-S4)是由CPU 17的指示來進 行，但資料並不辞過C P U 1 7 ,因而資料可高達的移動。 又，攝影時，即在記錄模式時（S1-S4)由操作者按下 該數位式攝影的快門鍵時的資料之移動路徑，以第7圖B 説明。C P U i 7會推移到圖樣的記錄保持狀態，在於由Y U V 信號處理電路11轉送到DRAM14的畫格轉送完了之時刻， 使DHA控制器12停止擷取YUV資料又於停止之同時起 動壓縮擴展電路13, DMA控制器12會從DRAM 14將一盡格 份的i U V資料，按照上逑圖像圖以8 X δ基本塊單位向壓 縮擴展電路13進行DHA轉送（S5)。CPU 17從壓縮擴展電 路]3中，依次讀出該壓縮擴展電路13所作成的壓縮資料 ，寫入於瞬時記億體18(S6)。 此時，在於睹縮擴展電路13的記億體壓縮中，控 一 1 1 - (讀先閱讀背而之注意事項再填窍本頁) \—. --6. 本紙張尺度迖圯十家標彳{ (’NS ) i ::<>.· 公# ) ΑΊ 4 497 3 9 五、發明説明（、。） 制器12也可繼纊將YUV資料轉送於視頻编碼器15(S7>t 顯示裝置16¾可由視頻编碼器15來的視頻信號，顯示出 和壓縮處理進行中的圖像資訊相同之圖像（S8)。 又，除了從輊縮擴展電路13讀出資料和將資料寫入於 瞬時記億體18之外，其餘的都是由DHA控制器12等受CPU 1 7的指示所進行，因而，資料不經過C P U 1 ?，可使資料 快速移動。 又，在於再生模式中，資料的移動為如第7圖C所示。 卽，由CPU 17的指示，YUV信號處理電路6及其前段會 被置於停止狀態^ CPU 17會依照操作者對其他鍵5中的 圖像選擇鍵之操作，從瞬時記億體18中讀出特定圖像的 符號資料，寫入於壓縮擴展霍路（S3)。然後，由CPU的 指示，經壓縮擴展電路13的壓縮處理所得的8X 8基本塊 單位的資料，會由DMA控制器12向DRAM14進行按照上述 _像圖的DMA轉送（S1G)，同時，DMA控制器12也向視 頻编碼器15進行按照該圖像圖之DMA轉送，由此被擴展 的圖像會自動的顯示於顯示裝置16之顯示盡面2上（S11 -S 1 2 ) 因此，和上逑同樣，不必用到以往裝置所具備 的VRAM控制器或VRAM,也可使由圖像選擇鍵的操作而從 儲存在瞬時記憶體18中被選出的圖像顯示於顯示装置16 之顯示蜜面2上。 又，除了從瞬時記憶體18讀出資料和將資料寫入於暖 縮擴展電路13之外，其餘的都是由DMA控制器12等受CPU 1 7的指示所進行，因而資料不經過C P U 1 7，可使資料快 -1 2 - (誚先閱讀背面之注意事項再填寫本頁) 丁 •-1' :l';:"ir't"^;fiooi-T-^fr<tft^,w 4 497 3 9 a7 B7五、發明説明（"） 速移動 又，在於像這種實施例中，YUV信號處理電路的YUV 資料在記憶體上之周期性展開區域，和視頻编碼器15在 記億體上之謓出區域都在於DRAM14中的同一區域。然而 ,YUV信號處理電路的YUV資料之畫格展開周期，和視 頻编碼器15的YUV資料之軎格讀出，周期不一定是在於 同步狀態，因而雙方要在同一區域存取時，由於如第5圖 Α〜第5圖D所示的雙方之周期性關係，會有使顯示裝置 1 6的顯示圖像劣化之情形。 即，第5圖A〜第5圖C是使YUV信號處理電路11的YUV 資料之展開區域和視頻编碼器1 5的Y U V資料之謓出區域 成為相同時，將YUV倍號處理電路11的YUV資料之寫入 線和視頻编碼器15的YUV資料之讀出線以時間軸所表現 者。其中，線是指圖像的水平線，以該圖像的水平線為 縱軸，而時間設定在横軸。又第5圖A〜第5圖C中的一點 鍵線是表示信號電路11的展開，因而相鄰的一點鏈 線之間隔就是展開周期。又，實線是表示視頻编碼器15 的第一區段之讀出，虛線是表示第二區段的讀出，因此 ，相鄰實線的間隔及相鄰虛線的間隔就是視頻编碼器15 的讀出周期。又，在第5_A〜第5圖c中，iruv信號處理 電路11的展開周期和視頻编碼器15的讀出周期之翻傜為 ，第5圖A是展開周期=讀出周期，第5圖B是展開周期 >讀 出周期，而第5圖C是展開周期 < 讀出周期之情形。 由此可知在第5_A及第5圖C中的t2、t3各時點， (讀先閱讀背面之注意事項再填寫本頁)4 497 3 9 A7 Printed by the Consumers ’Cooperative of the Central Standards Bureau of the Ministry of Distillation " B7 V. Description of the invention (1) [Usage fields on the production industry] The present invention relates to a photographing device, photographing method and display method, After the target scene is photographed, it will be displayed or recorded according to its circle image resources. [General Technology] First, the structure and operation of the previous photographic device will be described. The photographing device has a recording mode in which the recording of the target scene can be selected and recorded in M; and a reproduction mode in which the recorded photographic data is reproduced and displayed in M can be selected. In the recording mode, the photographic data captured by the charge coupled device (hereinafter referred to as CCD (Charge Coupled device)) will be processed in the following order. First, the CCD will output a photoelectric conversion output in one frame every certain period. The output is sampled and held by a sample and hold circuit, converted by an analog / digital (M hereinafter referred to as A / D) converter into digital data, and converted by a signal processing circuit containing at least a luminance signal and a color difference signal (hereinafter referred to as YUV). It is digital YiJV data containing brightness and color difference, and it is output to direct memory access [M hereinafter referred to as DMA (direct meiBory access) controller. The DMA controller writes the input YUV data into the internal buffer. And perform DMA transfer to dynamic random access memory [M DRAMfdynaifiic random access memory] via dynamic random access memory interface [M DRAMI / F (dynamic randoat access menory interface)]. -3- (Please read the precautions on the back before filling this page) This paper size is applicable to Chinese National Standards (CNS) Λ4 Regulations (210X297 gong) Printed by the Staff Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs ^ 4497 3 9_B7__ 五2. Description of the invention (2) After the above-mentioned YUV data is transmitted to the central processing unit (M), the MDHA is transferred to the DRAM, and the YUV data is withdrawn from the DRAM via DRAMI / F, and the video random access memory (M The VRAM) controller was written in VRAM. Next, the digital video codec (hereinafter referred to as VE) periodically extracts the above-mentioned YUV data from the VRAM through the VRAM controller, generates video signals from these data, and turns it out of the display device. As a result, an image based on image information captured by the CCO at that time can be displayed on the display device. However, in such a state that the image at that time is displayed on the display device, the user operates the shutter button at the time to be recorded and saved to generate a trigger pulse. Then the CPU according to the trigger pulse, after the DMA DRAM transfer to the DRAM of the full-faced YUV data retrieved from the CCD at that time, stops the path from CD C D to DR A M, and transfers to the state of record keeping. When the record is saved, the CPU writes out the YUV data of one frame in the DRAM through the DRAM I / F and writes it into the companding circuit. The symbol data compressed by the companding circuit is compressed from the compression. The expansion circuit reads and writes the non-volatile memory's transient memory. Then, with the end of the YUV data compression processing and the full compression data written to the transient memory, the CPU starts to transfer the data from the CCD to the DRAM. When the horizontal mode is reproduced, the image data recorded in the transient memory is displayed on the display device in the following order. When the camera is switched from the recording mode to the playback mode, the CPU stops the path from the CCD to the DRAM, and selects the time according to the image pressed by the user, and generates a specific frame of symbol data from the instant memory. Write 4 — (Please read the notes on the back before filling in this page. The size of the paper applies to the Chinese national standard ([yang] to the standard (210 >; 297 mm)) 4 4 9 7 3 9 ΑΊ Β7 V. Invention Explanation (々) Enter the compression and expansion circuit, perform expansion processing on the compression and expansion circuit, and expand a certain amount of YUV data to VRAM through the VRAM controller. Then, the video encoder is expanded to the end of VRAM. The qualified YUV data is used to generate a video signal and display it on a display device. [Problem 1 to be solved by the invention 1 However, in the conventional digital video camera like this, when the recording mode and the reproduction mode are described above, The γυν data of the frame is expanded in the DRAM, and after the YUV data is expanded in the DRAM, the YUV data is transferred from the DRAM to the VRAM, and the YUV data of the VRAM is read out by the video encoder for display. MA Μ is used as a memory for work, and VRAM is used as display memory, and images are displayed at the same time. Therefore, the work memory and display memory are Meibei's existence, which will cause When the cost increases and the circuit scale increases, and there are two memories, in the recording mode, the image information captured by CCf) is updated, or in the reproduction mode, every time the When the compressed OV data is expanded, the YUV data expanded in DRAM must be transferred to VRAM. As a result, the loss of power consumption is unavoidable. [Solving Means of the Invention] One of the ideal forms of the present invention includes: a photographing device that photographs a target scene to generate a signal corresponding to the target scene image; and creates a picture of the target scene image based on the signal generated by the photographing device Recording device for image data; Recording device for recording the image data created by the above device according to the capture operation; based on (Please read the precautions on the back before filling in this booklet I) Λ ^ ·-Order the paper size Shizhou: Standard () 4 current (210 × 297 male f) 4 4 9 7 3 9 A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs ^ V. Description of the invention (4) 1 1 Data »Make the target scene image display 1 1 I or according to the reproduction operation» Make the recording device according to the above picture 1! Display control device for image display of image data; memory device for operation; please 1 I 1 and M Read! 1 Transfer the image data from the above-mentioned creation device and the above-mentioned recording device to the above-mentioned work memory device 1 in a predetermined format T & and the above-mentioned format of the image data M is transferred from the memory device to the above display The transfer item of the control device is 1 1 The person who fills in this 1 fills in this 1 so that J can not only reduce the cost and reduce the circuit scale f, but also does not have to transfer the materials to VRA M and can avoid the loss of power consumption. The VRAM controller or VRAM included in the injection device is used. • It is still possible to display the image stored in the storage memory on the display of the display device on the display day. 0 1 Ordering »Another aspect of the present invention-'The ideal form is Contains:! 1 Photographs of g target scenes 4 to produce garden images corresponding to S target scene images 1 1 The photographing device t will be from above The circular image data from the above-mentioned photography device is temporarily stored in the temporary storage memory of 1 Im *, and the above-mentioned temporary storage B memory image 1 is displayed on the display device. The image data of the above-mentioned photography device is transferred to The temporary storage memory and the transfer device of the display device are described above. 0 1 Therefore »Not only can reduce the cost and m, reduce the circuit size 9 and) It is not necessary to transfer t data to VRAM 9 and can avoid the loss of power consumption. It is possible to transfer data 1 1 without having to transfer the data through the xW, m control device, thereby reducing the load on the control device. 1 1 load 0 i 1 > Another ideal form of the present invention is to include; 1! Photographic elements that capture image data »will be composed by Figure 1 from the above photographic elements I -6 1 1 1 1 This paper size ii uses the Chinese National Standard (CNS) Λ4 specification (210X 297 public dream) 449739 Cooperative seal?? V. Description of the invention () 1 1 I Temporary storage of image data is recorded in 100 million volumes; Compression circuit that compresses image data stored in the above temporary 1 1 I memory to compress the above The image data for saving the circular image data compressed by Dian 1 Road is used to save the image data. The display device that reads the image data recorded in the above temporary storage of 100 million jut m will be read 1 back I »and the above The image data of the temporary storage memory is transferred to the upper compression! I circuit and the transfer device of the above display device 0 Note 1 1 Therefore * It is not necessary to use the VRAM controller or VRAM item of the previous device, then 1 fill in i , Ft allows the image stored in the storage memory to be displayed on the display device% 〇 Again * Can reduce the data transfer through the control device 5 Due to pages, · 1 1 Pj reduces the load on the control device 〇 1 1 * *% of the invention An ideal form is to include 1 1 to save the compressed image data Use the memory device i to expand the above-mentioned saved 1 subscription memory device. The expansion circuit that expands the compressed data will be uploaded to the extension system! 1 channel of the expanded image data storage will temporarily store the memory device. * View the above 1 video! The display device displayed by the data encoded by the m coder transfers the image data extended by the above-mentioned extended 1 I circuit to the above-mentioned temporary storage memory device and the above-mentioned display device ’s transfer device. Therefore »it is not necessary The VRAM controller or VRAM 1 1 included in the injection device can also display the image stored in the storage memory on the 1 1 I display screen of the display device. The data transfer through the control device can be reduced due to 1 1 and the load on the control device can be reduced! I Again> Another preferred form of the present invention is to include a step (S 1) of taking image data from a photographic element. The steps of storing the image data from the above 11 photographic elements in the memory at m {S2); and 1 I-7 1 1 1 i 4 497 3 9 A7 6. Description of the invention (6) The image data of the memory is temporarily stored in parallel with the above step (S2), and is sent to the display device (S3, S4 >). This not only reduces the cost and circuit scale, but also eliminates the need to transfer sales materials to VRAM, which can mitigate the loss of power consumption. In addition, it is not necessary to transfer data through the control device, so the load on the control device can be reduced. In addition, another preferred form of the present invention includes: a step (S1) of capturing image data by a photographing element; and making an image from the photographing element Step of storing data in temporary storage memory (S2); Step of compressing image data stored in the temporary storage memory by a compression and expansion circuit (S5); storing image data compressed by the compression circuit in storage Step (S6) of the memory; and step (S8) of causing the image data stored in the temporary storage memory to be displayed by the display device in parallel with the step (S5). Thereby, it is not necessary to use a VR controller or VRA, which is provided in the M device, and it is possible to display the image stored in the storage memory on the display screen of the display device. In addition, the data transfer through the control device can be reduced, so the load on the control device can be reduced. In addition, another preferred form of the present invention includes: a step of transferring compressed image data from the storage memory to the expansion circuit (S9); and transmitting the image data expanded by the expansion circuit. Steps (S10 ~ S12) of temporarily storing the memory of the billion and sending the image data stored in the temporary storage memory to the display device. From tt, it is not necessary to use the VRAM controller or VRAM included in the device, and the image stored in the storage memory can be displayed on the display device (诮 Please read the precautions on the back before filling this page) This paper The scale is applicable to the Chinese National Standards (CNS) Λ4 specification (210X 297 mm) 4 497 3 9 A7 B7 V. Description of the invention (7) --------- 'Installation-(Please read the note on the back first) Please fill in this page again. In addition, the data transfer through the control device can be reduced, so the load on the control device can be reduced. [Embodiment] An embodiment of the present invention will be described with reference to the drawings. The first circle A and the first figure B are external views of the digital camera according to this embodiment. As shown in the figure, the digital camera pseudo-cuboid-shaped body 1 is provided with a display end surface 2 on the back of the body 1, a lens 3 on the front corner, and a shutter button 4 on the top and an image. Most other keys, such as selection keys, 5. FIG. 2 is a block diagram showing the configuration of the digital camera according to this embodiment. The CCD 6 disposed behind the lens 3 is driven by a timing signal generator 7 and a vertical driver 8, and outputs a picture of a photoelectric conversion wheel every certain period. The photoelectric conversion wheel is sampled and held by the sample-and-hold circuit 9, and converted into digital data by the A / D (analog / digital) converter 10, and processed by the YUV signal processing circuit 11 into digital YUV signals containing brightness and color difference. (A signal containing at least a luminance signal and a color difference signal) is output to a DMA (direct memory access) controller 12. The DMA controller 12 is connected to a companding circuit U, a DRAM (Dynamic Random Access Memory) 14, and a video encoder 15, and the video encoder 15 is connected to a display device 16 having the display screen 2 described above. . The above DMA controller 12 is connected to a CPU (Central Processing Unit) 17 and an instantaneous memory-9 via a bus. F-: (d < 'NS 丨 AWOS (2 I 〇 mm) 449739 A7 B7 ______________ V. Description of the Invention () CPU 丨 8, CPU 17 is the key part 19 composed of the shutter key 4 and other keys 5 and 9-round operation information. Figure 3 shows the DMA controller 12 and the DAM control. Of the connection state of the controller 12 and other blocks _. The above Yl) YUV data output of the V signal processing circuit 11 will be written in the first FIFO circuit (hereinafter referred to as FIFO) 20, and the DMA control circuit 21 via DKAMI / F (Interface) 2 2 is forwarded to the fans 〇1 ^ »14. ^ 4 The control circuit 21 will write the YUV data to the second FIF023 by DMA transfer from DRAHI / F 22 from DRAH14, and rotate the YUV data from the second FIF023 according to the read control signal of the video encoder 15. . In addition, the DMA control circuit 21 cuts the 8X8 base of the YUV data from the DRAM 14 via the DRAH / P 22, and transfers it to the third FIF024 by DMA, and according to the read control signal of the companding circuit 13, the YUV data is rotated from the third FIF024. Out of the warm shrink expansion circuit 13. In this embodiment configured as described above, the data movement path in the recording mode will be described with reference to 7A_ (S1 and S4). First, the photographic data captured by the CCD as described above will be made into one piece of YUV data (S1) that is rotated out by the γυν signal processing circuit 11 at a fixed period, and transmitted by the DMA controller 12 in DMA, periodically. Written by DRA14 (S2). In addition, the DHA controller 12 will develop the YUV data that is fixedly developed by the YDV signal processing circuit 11 on the DRAM 14 from the DRAM 14 and brew it according to the portrait. ;? 7 Gongchu) (Please read the precautions on the back before filling the chicken page) T,-»44973 9 a7 B7 V. Description of the invention (,), the wheel is out of the video encoder 15 (S2-S3) β Therefore, as the circular image information captured by the CCD 6 is periodically updated on the DRAM 14, the video encoder 15 automatically generates a video signal based on the updated information. Therefore, it is not necessary to use a VRAM controller or VRAH provided in the conventional device, and the current image (S4) can be displayed on the display screen 2 of the display device 16. As a result, not only the cost and the circuit scale can be reduced, but also It is not necessary to transfer the data to VRAM, so the loss of power consumption can be avoided. In addition, this series of actions (S1-S4) is performed by the instruction of the CPU 17, but the data does not pass C P U 1 7, so the data can be moved up to. In addition, in the case of photography, that is, in the recording mode (S1-S4), when the operator presses the shutter button of the digital photography, the data movement path is described with reference to FIG. 7B. The CPU i 7 will move to the record-keeping state of the pattern. At the time when the frame transfer from the YUV signal processing circuit 11 to the DRAM 14 is completed, the DHA controller 12 stops acquiring YUV data and starts the compression expansion circuit 13 at the same time as the stop. The DMA controller 12 forwards a full amount of i UV data from the DRAM 14 to the compression-expansion circuit 13 in units of 8 X δ basic blocks according to the upper image map (S5). The CPU 17 sequentially reads out the compression data created by the compression and expansion circuit 13 from the compression and expansion circuit] 3, and writes the compression data to the instant memory 18 (S6). At this time, it is in the compression of the billion-body compression of the expansion and contraction circuit 13, which is controlled by 1 1-(read the precautions before filling in this page) \ —. --6. There are ten paper sizes Standard {('NS) i :: < >. · ## ΑΊ 4 497 3 9 V. Description of the invention (, ...) The controller 12 can also forward the YUV data to the video encoder 15 ( S7 > t display device 1625 can display the same image information as the image information in the compression process from the video signal from the video encoder 15 (S8). The data is written outside the instant memory body 18, and the rest are performed by the DHA controller 12 and other instructions from the CPU 17. Therefore, the data can be moved quickly without passing through the CPU 1? In the mode, the movement of the data is as shown in Figure 7C. 由, under the instruction of the CPU 17, the YUV signal processing circuit 6 and its previous section will be put into a stop state. The operation of the image selection key reads out the symbol data of a specific image from the instant memory 18 and writes it into the compression and expansion hall (S3). After that, according to the instruction of the CPU, the data of 8 × 8 basic block units obtained by the compression processing of the compression and expansion circuit 13 will be transferred by the DMA controller 12 to the DRAM 14 according to the above-mentioned DMA image (S1G). The encoder 12 also performs a DMA transfer to the video encoder 15 according to the image map, and thus the expanded image is automatically displayed on the display end 2 of the display device 16 (S11-S 1 2). Therefore, and Similarly, it is not necessary to use a VRAM controller or a VRAM provided in a conventional device, and an image selected from the flash memory 18 can be displayed on the display device 16 by the operation of an image selection key. Surface 2. In addition to reading data from the transient memory 18 and writing data to the warm shrink expansion circuit 13, the rest are performed by the DMA controller 12 and other instructions from the CPU 17 Faster data without going through CPU 1 7-1-(诮 Please read the notes on the back before filling this page) Ding -1 ': l';: " ir't "^; fiooi-T- ^ fr < tft ^, w 4 497 3 9 a7 B7 V. Description of the invention The YUV data of the YUV signal processing circuit is periodically expanded on the memory, and the video encoder 15 is recorded in the memory area of the same area in the DRAM14. However, the YUV signal processing circuit of the YUV data is The frame expansion period and the YUV data of the video encoder 15 are read out in a grid. The period is not necessarily in a synchronized state. Therefore, when both parties want to access the same area, as shown in Figure 5A to Figure 5D The periodic relationship between the two parties may deteriorate the display image of the display device 16. That is, in FIGS. 5A to 5C, when the expanded area of the YUV data of the YUV signal processing circuit 11 and the extracted area of the YUV data of the video encoder 15 are the same, the YUV multiplication processing circuit 11 is The writing line of YUV data and the reading line of YUV data of the video encoder 15 are represented by the time axis. Here, the line refers to the horizontal line of the image, with the horizontal line of the image as the vertical axis, and the time is set on the horizontal axis. Furthermore, the one-point key lines in Figs. 5A to 5C indicate the unfolding of the signal circuit 11, so the interval between adjacent one-point chain lines is the unfolding period. The solid line indicates the reading of the first segment of the video encoder 15, and the dotted line indicates the reading of the second segment. Therefore, the interval between adjacent solid lines and the interval between adjacent dotted lines is the video encoder. 15 read cycles. In FIGS. 5_A to 5C, the unfolding period of the iruv signal processing circuit 11 and the readout period of the video encoder 15 are changed as follows: FIG. 5A is the unfolding period = reading period, and FIG. 5 B is a development period > readout period, and Fig. 5C is a case where a development period < readout period. From this, we can know that at t2 and t3 in Figures 5_A and 5C, (Read the precautions on the back before filling this page)
、1T 本紙张尺度適用中围困家標隼（cm ) Λ4規格（2丨0X297公釐） 449739 A7 B7五、發明説明（‘> ) 及在第中的ti、t2、t3、t4各時點會産生展開線與 讀出線的交叉。這種會産生展開線與讀出線交叉之事， 乃意味箸顯示於顯示畫面2的匾段（1/2畫格）中，混雜 箸展開軎格的更新前與更新後之圖像，而當在於攝取動 態的目標景物的圖像時，目標景物的影像會在顯示垂面 2内産生交錯潁示之情形。 然而，如第5圖D所示，YUV信號處理電路11的展開時 段對於視頻编碼器15的讀出時段成為間歇性時，雖然也 會産生交叉（tl、 t2),也會産生和第5_A〜第5圖C同樣 的目標景物的影像之交錯，但由於其時間間隔拉長，該 交錯影像在視覺上不易顯眼。因此，由定時信號産生器 7對於C C D 6的周邊或Y II V信號處理電路ί 1的驅動，以使 YUV信號處理電路11的展開時段成為如第5圖1)的間歇性 時，雖然在同一區域上由YUV信號處理電路11和視頻编 碼器〗5所存取，其在於攝取動態目標景物的圖像時，也 可抑制目標景物圖像的交錯顯示c 第6圖是本發明之另一實施例，是將目檫景物影像的 顯示交錯，利用二値區域將其消除者。卽，由時間倍號 産生器7將YUV信號處理電路11的展開周期和視頻编碼 器15的區段（1/2軎格）讀出周期之關偽，設定為展開周 期〉讀出固期。又，在DRAH14中形成區域A和匾域B , 由DAH控制電路21，使YUV信號處理電路11交替的展開 於區域A和區域B上。此時，在D A Μ控制罨路2 1中作成 於Y1IV倍號處理電路U對區域Α的展開終了時會上升， -1 4 - (請先閱讀背面之注意事項再填寫本頁) 本紙伕尺度迖川屮W W 車（C'NS ) A4規格（210X 297公釐） 好沪部中次標苹局只^消贽合竹社印繁 4 4 9 7 3 9 Λ7 B7 五 '發明説明（Η ) 而 對 於 m 域 B 的 展 開 终 了 時 會 下 降 之 區 域 控 制 信 號 S t 視 頻 编 m 器 1 5於 該 匾 域 控 制 信 號 S 為 低 電 平 狀 態 時 * 從 區 域 B 進 行 讀 出 9 於 高 電 平 時 從 區 域 A 進 行 讀 出 〇 因 此 » 不 iSit 在 同 __. 區 域 上 産 生 展 開 線 和 讀 出 線 的 交 叉 可 消 除 在 於 攝 取 動 態 g 標 景 物 的 圖 像 時 之 S 標 景 物 的 影 像 在 顯 示 裘 而 2 上 之 交 錯 顯 示 〇 [發明之效果1 如 上 說 明 t 本 發 明 是 將 圖 像 資 料 以 共 同 的 格 式 轉 送 於 各 部 門 * 以 作 為 顯 示 之 用 * 因 而 可 削 減 顯 示 用 的 記 億 體 或 控 制 器 > 由 此 而 可 削 減 成 本 及 使 電 路 規 模 縮 小 化 並 可 削 減 記 late 憶 體 間 的 資 料 轉 送 以 滅 低 消 耗 電 力 > 進 而 可 提 高 處 理 速 度 〇 又 將 所 作 成 的 圖 像 資 料 交 替 的 寫 入 於 — 對 區 域 中 > 而 從 不 在 於 寫 入 狀 態 的 m 域 J 將 圖 像 資 料 轉 送 到 顯 示 裝 置 « 因 而 宜 入 與 轉 送 不 發 生 在 同 — 區 域 * 可 解 除 在 同 —~* m 域 同 一 時 點 進 行 寫 入 與 轉 送 時 所 引 起 的 顯 示 圖 像 之 交 錯 情 形 〇 [附圖簡單説明 第 1圖A 本 發 明 一 實 施 例 之 數 位 式 攝 影 機 外 觀 斜 視 圖 第 1圖B 同 上 數 位 式 攝 影 機 之 另 一 方 向 斜 視 圖 〇 第 2 _ 同 上 數 位 式 攝 影 tMt 概 之 構 成 方 塊 圖 〇 第 3 圖 DH A 控 制 器 的 詳 細 及 與 其 他 的 連 接 狀 態 之 構 成 方 塊 _ 〇 第 4 Bel 圖 * 一 衋 格 份 的 YU V 資 料 之 圖 像 圖 〇 第 5圖A *Vr 第 5圖D ： 各 別 表 示 YU V 信 號 處 理 電 路 的 YU V -15- (請先閱讀背V0之注意事項再填寫本筲) .丨W衣_、 1T This paper size is applicable to the besieged house standard 隼 (cm) Λ4 specification (2 丨 0X297 mm) 449739 A7 B7 V. Description of the invention ('>) and ti, t2, t3, t4 The intersection of the unfolded line and the read line is generated. The fact that the unfolded line and the readout line intersect means that the 箸 is displayed in the plaque segment (1/2 frame) of the display screen 2, and the pre-update and updated images of the 箸 expanded frame are mixed, and When an image of a dynamic target scene is taken, an image of the target scene may be staggered in the display vertical plane 2. However, as shown in FIG. 5D, when the unfolding period of the YUV signal processing circuit 11 is intermittent with respect to the readout period of the video encoder 15, although crossover (tl, t2) will also occur, it will also generate the 5th_A ~ Figure 5C The interlaced images of the same target scene, but due to the long time interval, this interlaced image is not easy to be visually noticeable. Therefore, the timing signal generator 7 drives the periphery of the CCD 6 or the Y II V signal processing circuit ί 1 so that the unfolding period of the YUV signal processing circuit 11 becomes intermittent as shown in FIG. 5 and FIG. 1). The area is accessed by the YUV signal processing circuit 11 and the video encoder 5, which can suppress the interlaced display of the target scene image when capturing the image of the dynamic target scene. FIG. 6 is another aspect of the present invention. In the embodiment, the display of the target scene image is interlaced, and the second scene area is used to eliminate it. Alas, by the time multiplier generator 7, the unfolding period of the YUV signal processing circuit 11 and the readout period of the section (1/2 frame) of the video encoder 15 are set to the unfolding period> readout fixed period. . In addition, a region A and a plaque region B are formed in the DRAH 14, and the DAH control circuit 21 causes the YUV signal processing circuit 11 to be alternately developed on the regions A and B. At this time, in the DA M control path 21, the Y1IV-folded processing circuit U is used to expand the area A when it ends, -1 4-(Please read the precautions on the back before filling this page)迖 川 屮 WW car (C'NS) A4 size (210X 297 mm) Good Shanghai Ministry of Standards Ping Bureau only ^ Eliminated by Hezhusha Yinfan 4 4 9 7 3 9 Λ7 B7 Five 'invention description (Η) For the area control signal S t which will decrease at the end of the expansion of the m-domain B, the video encoder 15 will read from the area B when the domain control signal S is at a low level * 9 from the area at a high-level A reads it out. Therefore, »iSit does not cross the expansion line and readout line in the same __. Area, which can eliminate the image of the S target object when displaying the image of the dynamic g target object on the display 2 Interlaced display 0 [Effect of the invention 1 As explained above t The present invention is to transfer image data to various departments in a common format * for For display purposes * Therefore, it is possible to reduce the number of memory devices or controllers used for display> This can reduce costs and circuit size, and reduce the data transfer between memory devices to eliminate low power consumption> It can increase the processing speed. It also writes the created image data alternately in — to the area> and the m-field J, which is never in the writing state, transfers the image data to the display device « Occurs in the same-area *, which can release the interlaced display image caused by writing and transferring at the same time in the same- ~ * m domains. [Simplified illustration of the drawing, FIG. 1A, Digital format of an embodiment of the present invention Camera appearance oblique view Figure 1B The same perspective view of the digital camera in the other direction. 2nd _ Same as the digital camera tMt block diagram. 3 Details of the DH A controller and the constituent blocks of other connection states _ 4th Bel picture * Image of a single YU V data file 0 5th picture A * Vr 5th picture D: each shows YU YU V -15- for V signal processing circuit (Please read the precautions of back V0 before filling in this card). 丨 W 衣 _
,tT 本紙張尺度適用中®國家樣苹（CNS > A4規格（210X297公釐〉 ίΜ 97 3 9 Α7 Β7 五、發明説明（14 ) 資料寫入線和視頻編碼器的YUV資料讀出線之闞係圖。 第6圖：本發明另一實施行之YUV信號處理電路的YUV 資料寫入線和視頻編碼器的OV資料謓出線之關係圖。 第7圖A:在於記錄横式時的資料移動路徑圖。 第7圖B:在於記錄模式時的攝影時之資料移動路徑圖。 第7圓C:在於再生模式時的資料移動路徑圖。 (請先閲讀背面之注意事項再填寫本頁 訂 經濟部中央標隼局員Η消費合作社印製 -16- 本紙張尺度適用中國國家標莩（C\S :1 A"UttA· ( 21DX 297公;| ) 經濟部中央標準局員工消費合作社印裝 44973 9 a7 B7 五、發明説明（15 ) 1 主 體 2 顯 示 畫 面 3 透 鏡 4 快 門 鐽 5 其 他 鍵 6 電 荷 耦 合 器 (CCD ) 7 定 時 信 號 產 生 器 8 垂 直 驅 動 器 9 取 樣 保 持 電 路 10 類 比 /數位u/a V· 轉 換器 1 1 VU V 信 號 處 理 電 路 12 直 接 記 憶 體 存 取 (D Μ A )控制器 13 嬲 線 擴 展 電 路 14 動 態 随 機 存 取 記 憶 體（DRAM) 15 視 頻 m 碼 器 16 顯 示 裝 置 17 中 央 處 理 機 (CPU ) 18 瞬 時 記 億 體 19 鍵 部 20 第 一 先 進 先出 電 路 (FIFO) 21 DMA 控 制 電 路 22 DRAM I/F 2 3 第 二 FIFO 24 第 FIFO — 17- (請先閱讀背面之注意事項再填筠本頁) 本紙張尺度適用中國國家標準（CNS ) Λ4煶格（210X 297公f ), tT This paper size is suitable for China National Samples (CNS > A4 specification (210X297 mm) ί 97 3 9 Α7 Β7 V. Description of the invention (14) Data writing line and YUV data reading line of video encoder Figure 6. Figure 6: The relationship between the YUV data write line and the OV data output line of the video encoder in another embodiment of the YUV signal processing circuit of the present invention. Figure 7: A in the horizontal recording mode Data movement path diagram. Figure 7B: Data movement path diagram during photography in recording mode. Round 7: Data movement path diagram during playback mode. (Please read the precautions on the back before filling this page. Ordered by the Central Bureau of Standards of the Ministry of Economic Affairs and printed by the Consumer Cooperatives -16- This paper size applies to China's national standard (C \ S: 1 A " UttA · (21DX 297); |) Printed by the Consumer Standards of the Central Standards Bureau of the Ministry of Economic Affairs 44973 9 a7 B7 V. Description of the invention (15) 1 Main body 2 Display screen 3 Lens 4 Shutter 鐽 5 Other keys 6 Charge coupled device (CCD) 7 Timing signal generator 8 Vertical driver 9 Take Sample holding circuit 10 Analog / digital u / a V · converter 1 1 VU V signal processing circuit 12 Direct memory access (D Μ A) controller 13 Wireless expansion circuit 14 Dynamic random access memory (DRAM) 15 Video m encoder 16 Display device 17 Central processing unit (CPU) 18 Instant memory 19 million keys 20 First first-in first-out circuit (FIFO) 21 DMA control circuit 22 DRAM I / F 2 3 Second FIFO 24th FIFO — 17- (Please read the notes on the back before filling in this page) This paper size applies to Chinese National Standard (CNS) Λ4 煶 (210X 297mm f)