KR20000015062A - Circuit for simultaneously embodying european and north american type interoffice connection - Google Patents

Abstract

PURPOSE: A circuit for simultaneously embodying European and North American type interoffice connection capable of embodying an E1 trunk connection and a T1 trunk connection in a one board by changing a transmission line matching circuit, a network sync circuit, a PCM sub highway is provided. CONSTITUTION: A circuit for simultaneously embodying European and North American type interoffice connection, the circuit comprising: a plurality of transmission connectors(100) for matching an electric transmission line; a PCM channel switch(200) for switching each PCM channel connected to the transmission connectors(100) and being connected to a PCM sub highway; a dividing circuit(300) for extracting a reference clock for a system synchronism from a clock received from the plurality of transmission connectors(100); a phase sync and jitter attenuating circuit(500) for producing a system clock based on the reference clock extracted from the dividing circuit(300); a recovering clock selecting and transmission line type selecting section(600) for performing a function which selects one reference clock from a plurality of clocks and a function which designates an E1 interface and a T1 interface; and a clock dividing circuit(400) for providing a divided clock to each terminal or PCM sub highway, or a recovering clock selecting and transmission line type selecting section.

Description

Circuit for implementing European and North American connections simultaneously

The present invention relates to a method for simultaneously implementing a connection between a European (E1) and a North American (T1) station on one board, and particularly, a method useful in a small capacity system requiring a trunk connection.

In general, there is a large number of E1 trunk connections in Europe and T1 trunk connections in North America, and the T1 connection and the E1 connection are used interchangeably in Korea.

Referring to the E1 trunk connection and the T1 trunk connection, first, for the E1 trunk connection, a transceiver 10 and an E1 frame for transmitting / receiving a physical transmission line and a signal as shown in FIG. It consists of a framer 20 for creating and extracting. In addition, the network synchronization block 30 generates a network synchronization clock 2.048 MHz necessary for the system by using a 2.048 MHz clock recovered from the transceiver 10 for network synchronization of the system, thereby generating a framer 20 and a pulse code modulation (Pulse). Code Modulation (hereinafter, referred to as PCM) is used as a reference clock of a sub-highway.

For the T1 trunk connection, a physical transmission line connection and a transceiver 40 for transmitting / receiving a signal as shown in FIG. 2 and a framer 50 for generating and extracting a T1 frame are configured. In the network synchronization block 60, a network synchronization clock 1.544 MHz necessary for the system is generated by using a clock of 1.544 MHz recovered from the transceiver 40 for network synchronization of the system, and used as a reference clock of the framer 50. The reference clock of the PCM sub highway uses 2.048 MHz.

Since the basic clocks of the E1 trunk and the T1 trunk are different, they have been implemented and used on different boards. The problems of this prior art are as follows.

In a high-capacity system, several trunk boards are used, so it is not a problem to implement separate E1 board and T1 board, but in a small-capacity system that requires only a few trunks, at least two trunk boards can be used simultaneously. Two boards are required, resulting in space problems.

Accordingly, the present invention was devised to solve the above problems, and the E1 trunk connection and the T1 trunk connection in one board are changed for each port by changing transmission line matching circuit, network synchronization circuit, and PCM subhighway. An object of the present invention is to provide a circuit for simultaneously implementing a European-American-North American inter-station connection that can be implemented separately.

Another object of the present invention is to implement the E1 trunk connection and T1 trunk connection differently for each terminal in one board, so that the E1 transmission line and T1 transmission line can be flexibly selected and used in the system installation, European and North American It is an object of the present invention to provide a circuit for simultaneously implementing the inter-station connection of the scheme.

The above and other objects and novel features of the present invention will become more apparent from the following detailed description of the invention and the accompanying drawings.

1 is a configuration diagram of a conventional E1 interface applied to the present invention.

2 is a configuration diagram of a conventional T1 interface applied to the present invention.

3 is a schematic diagram of an E1 / T1 interface according to the present invention;

4 is a transmission line connecting circuit diagram according to the present invention;

5 is a dispensing circuit diagram according to the present invention;

6 is a phase locked and jitter attenuation circuit diagram in accordance with the present invention.

7 is a clock distribution circuit diagram in accordance with the present invention.

8 is a recovery clock selection and transmission line type selection circuit diagram in accordance with the present invention.

<Description of the symbols for the main parts of the drawings>

10: E1 transceiver

20: E1 Framer

30, 60: network synchronization block

40: T1 transceiver

50: T1 Framer

100: transmission line connection

110: impedance matching circuit

120: transceiver

130: framer

200: PCM channel switching unit

300: division circuit

310: reference clock selection circuit

320: division ratio selection circuit

330 1/256 division circuit

340: 1/193 division circuit

400: clock distribution circuit

410: backbone clock distribution circuit

420: transmission clock selection circuit

500: phase locked and jitter attenuation circuit

510: digital phase synchronization circuit

520 jitter attenuation circuit

600: recovery clock selection and transmission line type selection unit

610: recovery clock selection circuit

620: transmission line type selection circuit

In order to achieve the above object, a preferred embodiment of a circuit for simultaneously implementing a connection between a European system and a North American system according to the present invention, which is designed to achieve the above object, includes a plurality of transmission line connection units for electrical transmission line matching and the transmission line connection unit. A PCM channel switching unit for switching each PCM channel to be connected to the PCM sub highway, a divider circuit for extracting a reference clock for network synchronization of the system from clocks received from the plurality of transmission line connection units, and a reference extracted from the divider circuit Recovery clock selection and transmission lines with phase-lock and jitter attenuation circuitry that generates the backbone clocks needed by the system from the clock, the ability to select one reference clock from multiple clocks, and the ability to specify an E1 or T1 interface for each terminal A type selector, and each terminal or PCM sub This way, or comprises a recovery clock selection and clock distribution circuitry for distributing a clock to the transmission line type selection unit.

The present invention implements the E1 connection and the T1 connection at the same time on the E1 connection and T1 connection with different electrical characteristics and transmission speeds on one board. Here, the electrical characteristics are designed to be changed using a jumper and an integrated circuit socket (IC SOCKET), and a reference clock of 8 MHz is extracted from the E1 speed and the T1 speed, respectively, to obtain a digital loop lock. The clock was generated using the PLL) as a reference clock to ensure that the clock used in the system is in phase synchronization.

In order to process E1 PCM data and T1 PCM data on one board at the same time, a function that can systematically synchronize between E1 connection and T1 connection is required.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is an E1 / T1 interface configuration diagram. Looking at the configuration of the present invention with reference to this, as follows.

The present invention is to switch the PCM channel connected to the transmission line connecting portion 100, the transmission line connecting portion 100 for electrical transmission line matching in order to implement the European and North American method of trunk connection at the same time on a single board to the PCM sub highway PCM channel switching unit 200 to connect, the division circuit 300 for extracting the reference clock for the network synchronization of the system from the clock received from the transmission line, the club distribution circuit 400 for distributing the clock, the extracted reference clock Phase-synchronizing circuit 510 for generating the network synchronization clock of the system, jitter attenuation circuitry 520 for attenuating jitter for the 1.544 MHz clock T1, and selecting one reference clock from multiple receive clocks. A recovery clock selection and transmission line type selection unit 600 having a function and a function of specifying an E1 interface or a T1 interface for each terminal. It is made.

The transmission line connector 100 includes an impedance matching circuit 110, a transceiver 120, and a framer 130. The impedance matching circuit 110 allows the transmission line protection and transformer circuits to be used together at E1 and T1 to match the electrical characteristics of the E1 connection and the T1 connection. In order to match the transmission line impedance, the impedance resistance of E1 and the impedance resistance of T1 are separated by a jumper and designed to be connected. The transceiver 120 and the framer 130 use parts that can perform both functions at the same time, so that the electrical characteristics of the E1 connection and the T1 connection can be replaced by the replacement of these parts, and the IC can be easily replaced. A socket was used. The components used were manufactured by DALAS, using the DS2153Q for the E1 connection and the DS2151 for the T1 connection. The reception block of the transceiver 120 extracts a reception clock and reception data from a received reception transmission line, and transmits transmission data to the transmission transmission line in synchronization with the transmission clock. The framer 130 extracts and generates an E1 frame and a T1 frame, respectively, and transmits and receives PCM data for each channel to the PCM terminal.

The PCM channel recovered from the framer 130 of the transmission line connection unit is 32 channels in the E1 connection and 24 channels in the T1 connection. The PCM terminal between the framer 130 and the PCM channel switching unit 200 has a 2.048bps transmission rate of 32 channel structure. Therefore, in the T1 connection, eight channels are not used as idle. These unused channels do not use 1, 5, 9, 13, 17, 21, 25, 29 channels to distribute traffic. The PCM channel switching unit 200 switches the channels of each PCM terminal to the PCM subhighway to be connected. The PCM subhighway is connected to other blocks for processing PCM data so that the PCM data is processed. This is accomplished using a time switch component.

The division circuit 300 includes a reference clock selection circuit 310, a division ratio selection circuit 320, a 1/256 division circuit 330, and a 1/193 division circuit 340. The reference clock selection circuit 310 selects one specific clock from among the reception clocks RxCLK [1: n] input from a plurality of transmission lines in order to generate a reference clock required for system synchronization. In the division ratio selection circuit 320, if the selected clock is the reception clock of the E1 terminal, it is sent to the 1/256 division circuit 330 to divide the signal by 256 to make an 8KHz clock, and if the reception clock of the T1 terminal is the 1/193 division circuit 340 193 is divided into 8KHz clock and used as the reference clock. Selection of one specific clock among the received clocks (RxCLK [1: n]) uses the SEL_CLK_D [1: n] signal of the recovery clock selection and transmission line type selection unit 600, and selection of the E1 / T1 terminals is performed by the SEL_E1 / T1 signal. Use This circuit is implemented in logic using EPLD.

In order to generate a backbone clock required for the system, the phase lock and jitter attenuation circuit 500 drives the digital phase lock circuit 510 using a reference clock of Rec_8KHz. In this way, an 8KHz PCM_SYNC signal and a 16.384MHz oscillator clock are input to generate an E1 speed clock of 2.048MHZ, and a 12.352MHz oscillator clock is input to create a 1.544MHz T1 clock. The 1.544MHz clock contains a lot of jitter, which causes the clock to be out of sync with Frame Sync. In order to attenuate this jitter component, the jitter attenuation circuit 520 is passed through and used. The digital phase-lock circuit 510 is implemented using Mitel's MT8941 component, and the jitter attenuation circuit 520 is implemented using LevelOne's LXP604 component.

The clock distribution circuit 400 includes a backbone clock distribution circuit 410 and a transmission clock selection circuit 420. The backbone clock distribution circuit 410 receives the PCM_SYNC, CLK_2.048MHz, and CLK_1.544MHz from the phase lock and jitter attenuation circuit 500 to receive the FS [1; n] and CLK_2.048MHz [1: n] signals required as the backbone clocks. It is supplied to the framer 130, the PCM channel switching part 200, and the PCM sub highway of each terminal. The transmission clock selection circuit 420 supplies the TxCLK [1: n] clock necessary for transmission of each terminal to CLK_2.048MHz for the E1 connection and to CLK_1.544MHz for the T1 connection, depending on the state of each terminal. Here, the E1 / T1 connection selection for each terminal is selected using the SEL_E1 / T1_D [1: n] signal.

The recovery clock selection and transmission line type selection circuit 600 includes a recovery clock selection circuit 510 and a transmission line type selection circuit 520. The recovery clock selection circuit 510 selects a reception clock of a stable transmission line without error for the longest time after checking the state of the transmission line in the program of the CPU. The selected value is written to the recovery clock selection register SEL_CLK_D [1: n] using the CPU_DATA [0: 7] and CPU_SEL_CLK signals. The transmission line type selection circuit 520 writes the status value of each terminal to the terminal status storage register SEL_E1 / T1_D [1: n] using the CPU_DATA [0: 7] and CPU_SEL_E1 / T1 signals. Save it. The stored values are used to select a reference clock for backbone clock recovery and to provide the clock required for each terminal. The division circuit, recovery clock selection, transmission line type selection circuit, and clock distribution circuit are implemented in EPLD.

The basic operation of the present invention configured as described above selects whether to have an E1 connection or a T1 connection for each terminal in a system initial configuration step. In each transmission line connection part, the electrical characteristics of the E1 connection are 120ohm impedance matching, the E1 transceiver and the E1 framer are mounted, and the corresponding E1 drive program is executed. For the T1 connection, match the electrical characteristics to 100 ohm impedance, mount the T1 transceiver and T1 framer, and run the corresponding T1 drive program. The program of the CPU records the selected state (E1 / T1) of each terminal in the transmission line type selection section, and selects the reference clock to find the terminal with the best error free status among several terminals and use it as the reference clock for system network synchronization. One reference clock is selected for the part. In the divider circuit, if the selected reference clock has an E1 clock, it has a frequency of 2.048 MHz. If the selected reference clock has a frequency of 1.544 MHz, it is divided into 193 and divides 193 if the selected reference clock has a frequency of 1.544 MHz. And use it as the reference clock of the phase-lock circuit. In the phase-lock circuit, an 8KHz reference clock is created and used as the reference clock of the phase-lock circuit. The phase-lock circuit uses a digital phase-lock circuit for the 16.384 MHz oscillator clock based on an 8-KHz reference clock to create a frame-locked frame-synchronized clock and a 2.048-MHz clock to supply the clock distribution circuit. Using a digital synchronous phase circuit to the oscillator clock, a clock-sharing circuit is created by compensating frame synchronization and jitter by passing a jitter attenuation circuit to reduce the jitter of the 1.544 MHz clock by creating a 1.544 MHz clock that is phase-locked to the selected reference clock. To feed. In the clock distribution circuit, the transmission clock TxCLK is sent to the transceiver of each terminal when the E1 connection is made, and 1.544 MHz is sent to the transceiver of each terminal when the T1 connection is established. A backbone clock for use in the system, which provides frame sync and 2.048MHz clocks to the framer, channel switching portion, and PCM subhighway at each terminal. In this way, E1 and T1 terminals with different speeds can be accommodated on one board.

While the invention is susceptible to various modifications and alternative forms, the disclosure thereof has been described with reference to specific embodiments only. It is to be understood, however, that the present invention is not limited to the specific forms referred to in the specification, but rather that the invention is intended to cover all modifications, equivalents, and substitutions within the spirit and scope of the invention as defined by the appended claims. It should be understood to include.

In the present application operating as described above, the effects obtained by the representative ones of the disclosed inventions will be briefly described as follows.

In Korea, North American E1 connection and European T1 connection coexist in trunk connection. Thus, a separate converter is required for the connection between different systems. And a separate system or board was needed to accommodate both.

By allowing E1 and T1 connections to be accommodated on one board at the same time, it is easy to change the port configuration of the E1 and T1 connections in one system, especially a small capacity system, and reduce the system price and size.

Claims (20)

A plurality of transmission line connections for electrical transmission line matching; A PCM channel switching unit for switching each PCM channel connected to the transmission line connection unit to be connected to a PCM sub highway; A division circuit for extracting a reference clock for network synchronization of a system from clocks received from the plurality of transmission line connections; A phase locked and jitter attenuating circuit for generating a backbone clock required for the system from the reference clock extracted by the division circuit; A recovery clock selection and transmission line type selection unit having a function of selecting one reference clock from multiple clocks and a function of designating an E1 interface or a T1 interface for each terminal; And And a clock distribution circuit for distributing a clock to each terminal or to a PCM subhighway or a recovery clock selection and a transmission line type selection unit. The method of claim 1, wherein the transmission line connecting portion, An impedance matching circuit for matching the E1 connection and the T1 connection and matching the transmission line impedance; A transceiver comprising a reception block for extracting a reception clock and reception data from a received reception transmission line and a transmission block for transmitting transmission data to the transmission transmission line in synchronization with the transmission clock; And And a framer for extracting and generating an E1 frame and a T1 frame to transmit and receive PCM data for each channel to a PCM terminal. 3. The circuit according to claim 2, wherein the transmission line protection and modification circuits can be used in E1 and T1 together to match the E1 connection and the T1 connection. 3. The circuit of claim 2, wherein the connection between the impedance resistance of E1 and the impedance resistance of T1 is separated by a jumper so as to match the transmission line impedance. 3. The circuit according to claim 2, wherein the transceiver and the framer are interchangeable. 6. The circuit according to claim 5, wherein a European-American-North American station-to-station connection is simultaneously used using an IC socket when the transceiver and the framer are replaced. The method of claim 1, wherein the PCM channel switching unit, A circuit for simultaneously implementing a European-American-North American interface between the channels of each PCM terminal recovered from the framer of the transmission line connection unit by switching to the PCM subhighway. 8. The circuit of claim 7, wherein the PCM channel recovered from the framer is 32 channels in an E1 connection and 24 channels in a T1 connection. 8. The circuit according to claim 7, wherein the PCM terminal between the framer and the PCM channel switching unit has a 2.048 bps transmission rate of 32 channel structure. 8. The method of claim 7, wherein the PCM subhighway is connected to another block for processing the PCM data so that the PCM data is processed, and simultaneously implements a connection between the European and North American stations, which are implemented using a time switch component. Circuit for doing so. 8. The European and North American methods of claim 7, wherein eight channels, i.e., 1, 5, 9, 13, 17, 21, 25, 29 channels, are not used as idles in a T1 connection to distribute traffic. Circuit for simultaneously connecting stations. The method of claim 1, wherein the frequency divider circuit, A reference clock selection circuit for selecting one specific clock from among the reception clocks (RxCLK [1: n]) input from the plurality of transmission lines; A division ratio selection circuit for selecting a 1/256 division circuit if the selected clock is a reception clock of an E1 terminal and a 1/193 division circuit for a reception clock of a T1 terminal; A 1/256 frequency divider circuit for dividing the selected clock 256 to produce a reference clock of 8 KHz; And And a 1/193 divider circuit for dividing the selected clock into 193 to form a reference clock of 8 kHz. 13. The method of claim 12, wherein one specific clock selection of the reception clock RxCLK [1: n] uses a recovery clock selection and a SEL_CLK_D [1: n] signal of a transmission line type selection unit. Circuitry for simultaneously implementing the circuit. The circuit of claim 1, wherein the phase locked and jitter attenuating circuit comprises: A digital phase synchronizing circuit for generating a network synchronizing clock of the system from a reference clock Rec_8KHz made by the division circuit; And A circuit for simultaneously implementing a European-American-North American station connection, comprising a jitter attenuation circuit for attenuating jitter for a 1.544 MHz clock which is a T1 clock. The method of claim 14, wherein the digital phase synchronization circuit, The European and North American methods produce 848Hz PCM_SYNC signal and 16.384MHz oscillator clock for E1 speed clock input, and 12.352MHz oscillator clock for 1.544MHz T1 speed input. Circuit for simultaneously implementing station-to-station connections. The method of claim 1, wherein the clock distribution circuit, Framer, PCM channel switching part of each terminal receives FS [1; n] and CLK_2.048MHz [1: n] signals required for the backbone clock by receiving PCM_SYNC, CLK_2.048MHz, and CLK_1.544MHz from the phase-lock and jitter attenuation circuit. A backbone clock distribution circuit for supplying the PCM sub highway; And The TxCLK [1: n] clock required for transmission of the respective terminals is provided with a transmission clock selection circuit for supplying 2.048 MHz for the E1 connection and 1.544 MHz for the T1 connection, depending on the state of each terminal. Circuit for simultaneously implementing North American inter-station connection. 17. The circuit of claim 16, wherein the E1 / T1 connection selection for each terminal is selected using a SEL_E1 / T1_D [1: n] signal. The circuit of claim 1, wherein the recovery clock selection and transmission line type selection circuit comprises: After checking the status of the transmission line in the program of the CPU, select the reception clock of the stable transmission line without error for the longest time, and use the CPU_DATA [0: 7] and CPU_SEL_CLK signals to recover the SEL_CLK_D [1: n] A recovery clock selection circuit for recording a value selected in the circuit; And Transmission line type selection circuit that records the state value of each terminal in the terminal state storage register SEL_E1 / T1_D [1: n] by using the CPU_DATA [0: 7] and CPU_SEL_E1 / T1 signals. A circuit for implementing a European and North American connection at the same time comprising a. 19. The method of claim 18, wherein the European-North American connection between the European and North American stations that selects a reference clock for backbone clock recovery using the values stored in the transmission line type selection circuit and controls the supply of the necessary clock to each terminal is simultaneously performed. Circuitry to implement. The circuit of claim 1, wherein the division circuit, the recovery clock selection circuit, and the clock distribution circuits are implemented in EPLD.