KR20000014356A - Clock control method and apparatus of a bus communication system - Google Patents

Abstract

PURPOSE: A clock control apparatus of a bus communication system is provided to improve an efficiency of a bus communication by making the bus using machines recognize an exchange speed of a clock automatically. CONSTITUTION: The clock control apparatus of a bus communication system comprises: a bus matching part (421) for matching data received by a bus clock; a clock counting part (423) for counting the bus clock to judge a speed of the clock; and a bus matching control part (422) for compensating the speed of the bus clock by a clock speed judge signal to store the matched data to a memory. The clock counting part (423) includes a counter for counting the bus clock to generating a count value corresponding to a clock speed; and a clock speed judging part for analyzing the clock count value to judge the clock speed and for generating a select control signal of memory write control signals of the bus matching control part.

Description

Clock control device and method of bus communication system

The present invention relates to an apparatus and method for controlling a bus clock, and more particularly, to an apparatus and method capable of automatically recognizing and changing a clock of a bus.

In general, a communication system such as an exchange performs a bus communication between modules. 1 is a diagram illustrating a configuration of an apparatus for controlling a clock of a bus in a conventional communication system. Referring to FIG. 1, a communication start signal is output to the main bus controller 100, and the bus device 110 outputs a response signal thereto. The bus using device 110 is connected to the main bus controller 100 through a bus to perform a bus matching function of the bus using device 110. Then, the main bus controller 100 initiates data transmission in response to the response signal of the bus using device 120.

3 is a view for explaining a bus signaling method between the main bus controller 100 and the bus using device 110. Referring to FIG. Referring to FIG. 3, the main bus controller 100 transmits a clock with data to the bus using device 110 using a memory. Then, the start signal is transmitted to start communication, and the bus-operated device 110 waits for a response. When the response signal is received, data synchronized with the response signal is transmitted. Then, the receiving side converts the data in parallel with the bus clock. When the conversion is completed, the receiving side is stored in the memory by the memory write permission signal.

2 shows a configuration of the bus matching unit 111 of the bus using device 120. As shown in FIG. Referring to FIG. 2, the parallel data output from the memory 214 is applied to the converter 216. The converter 216 converts the parallel data received by the clock output from the bus clock generator 212 into serial data and outputs the serial data. At this time, the bus clock is also transmitted to the bus.

The converter 224 connected to the bus then receives serial data on the bus and converts the serial data received by the clock on the bus into parallel data. The memory 222 stores parallel data output to the converter 224. The memory write control unit 226 inputs a clock on the bus to generate a memory write permission signal 1 and a memory write permission signal 2, and controls the switch 228 to apply one of the permission signals to the memory 222.

In such communication, it is necessary to increase the speed of the bus clock when it is necessary to improve the speed of the bus in order to change functions or improve performance. At this time, when the clock speed increases, the write permission signal needs to be corrected by the delay of the response signal. For this purpose, the memory write permission signal varies depending on the type of clock. Normally, the main bus controller 100 is designed to adjust the clock speed, and the bus-use device 120 has to be manually changed by using jumpers or switches to match the clock speed of the bus.

Accordingly, an object of the present invention is to provide an apparatus and method for automatically recognizing and changing a bus clock when a clock speed changes in a bus communication system in which a main controller supplies a clock.

A clock control apparatus for a bus communication system according to an embodiment of the present invention for achieving the above object includes a bus controller for supplying a clock, a bus matching unit for matching data received by the bus clock, and the bus clock. And a bus matching control unit configured to determine a clock speed by counting a signal, and a bus matching controller configured to compensate for the clock speed by the clock speed determination signal and to store matched data in a memory.

1 is a diagram showing the configuration of a conventional bus clock control apparatus.

FIG. 2 is a diagram showing the configuration of the bus matching section of FIG. 1. FIG.

3 is a view for explaining a method of using a bus signal using a communication start signal and a response signal;

4 is a diagram illustrating a configuration of an apparatus for recognizing and changing a bus clock according to an exemplary embodiment of the present invention.

FIG. 5 is a diagram showing the configuration of the bus matching section of FIG. 4. FIG.

In the bus communication system according to an exemplary embodiment of the present invention, when the clock speed is changed when the main controller of the bus supplies a clock, devices using the bus automatically recognize the clock speed and perform smooth communication. To this end, the bus communication system includes a bus matching unit that uses a start signal and a response signal. The bus matching unit provides a clock counting function capable of detecting a clock speed to a device using a bus, and outputs a clock counter. By controlling the bus matching section, it automatically compensates for factors such as delay due to clock change and eliminates manual control of each device for ease of use.

4 is a diagram illustrating a structure of a bus communication system according to an exemplary embodiment of the present invention, in which a main bus controller 400 includes a bus clock generator and controls communication with a bus using device 420. The bus using device 420 is connected to a bus and performs a function of matching with a bus to communicate with the main bus controller 400. The bus matching controller 422 controls the operation of the bus matching section 421. The clock counting unit 423 is connected to the bus matching unit 421 to count a bus clock and output the counted bus clock to the bus matching control unit 422.

In the bus communication system having the configuration as shown in FIG. 4, the bus using device 420 counts the clock output through the bus to the main bus controller 400, and automatically compensates for factors such as delay due to clock change.

5 is a view illustrating in detail the operation between the main bus controller 400 and the bus using device 420. Referring to FIG. 5, the parallel data output from the memory 521 is applied to the converter 523. The converter 523 converts the parallel data received by the clock output from the bus clock generator 522 into serial data and outputs the serial data on the bus. At this time, the bus clock is also transmitted to the bus. The converter 523 may be a parallel to serial converter.

The converter 524 connected to the bus then receives serial data on the bus and converts the serial data received by the clock on the bus into parallel data. In this case, the converter 524 may be a serial to parallel converter. The memory 525 stores parallel data output to the converter 524. The above configuration is equivalent to the bus matching section 421.

Counter 528 inputs a clock on the bus and counts the clock by a counter control signal to generate a clock speed signal. In this case, the counter control signal uses a clock generator in the bus using device 420, not the bus clock, and generates a signal so that no overflow occurs when the maximum speed of the bus clock is counted. The clock speed determiner 529 analyzes the count value output from the counter 528 to determine the speed of the bus clock, and generates a clock selection control signal to the selection circuit 527 according to the determination result. The above configuration corresponds to the clock coefficient unit 423.

In addition, the memory write control unit 226 inputs a clock on the bus to generate a memory write permission signal 1 and a memory write permission signal 2. The selection circuit 527 inputs the memory write permission signal 1 and the permission signal 2, selects a signal corresponding to the clock control signal, and supplies the selected signal to the clock of the memory 525. The above configuration corresponds to the bus matching controller 422.

Referring to FIGS. 4 and 5, the operation of the bus communication system according to an exemplary embodiment of the present invention will be described. When the clock output from the main bus controller 400 is supplied to the bus using device 420 through a bus, the bus matching unit 221 may be used. It is input to the clock counting unit 423 through. At this time, when a change of the clock output from the main bus controller 400 occurs, the output of the clock coefficient unit 423 is changed to be input to the bus matching controller 422, and the Sykes bus matching controller 422 uses the bus matching unit 421 according to the change of the clock. Control to perform communication function.

Therefore, the bus communication system according to the embodiment of the present invention adds the functions of the clock coefficient unit 423 and the bus matching controller 422 to count the bus clocks to the internal functions of the bus using device 420 when the clock speed of the main bus controller 400 is changed. This automatically detects and handles bus clock changes.

As described above, when the clock speed is changed in a bus communication system in which the main controller of the bus supplies a clock, bus-using devices automatically recognize the clock change speed to perform a bus matching function, thereby reducing delay factors due to clock changes. It can be eliminated, which has the advantage of improving the efficiency of bus communication.

Claims (4)

A clock control apparatus for a bus communication system having a main controller for supplying a clock, A bus matching unit for matching data received by the bus clock; A clock counting unit for counting the bus clock to determine a clock speed; And a bus matching controller for compensating the clock speed by the clock speed determination signal and storing matched data in a memory. The method of claim 1, wherein the clock coefficient unit, A counter for counting the bus clock and generating a count value corresponding to a clock speed; And a clock speed determiner for analyzing a clock coefficient value and determining a bus clock, and generating a selection control signal of memory write control signals of the bus matching controller. In the clock control method of a bus communication system having a main controller for supplying a clock, Matching data received by the bus clock and counting the bus clock to determine a clock speed; Compensating the clock speed by the clock speed determination signal to store the matched data in the memory. The method of claim 3, wherein the determining of the clock speed comprises: Counting the bus clock to generate a coefficient value corresponding to a clock speed; And determining a bus clock by analyzing the clock coefficient value, and generating a selection control signal of memory write control signals of the bus matching controller.