KR20000014185A - Semiconductor device manufacturing method - Google Patents

Abstract

PURPOSE: Because dies are established in the whole area, every die has the same surrounding condition. So step portion among dies is prevented after the chemical mechanic polishing. Because the dies which is located in the edge of a wafer also have even layers, the inferior of a via is prevented and the yield of an element is increased. CONSTITUTION: A metal film is formed on the whole area and even the edge of a wafer. The metal film is patterned and a metal wiring with the same width of line is performed on the wafer. By plasma, an oxidation layer is formed on the whole area. Then an oxidation layer is polished chemically and mechanically.

Description

Semiconductor device manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing generation of steps by changing a die arrangement on a wafer.

Each die holding a complete semiconductor device is bounded by adjacent scribe lines in the vertical and horizontal directions and formed on the wafer.

1 shows a die structure plan view, which shows that a die is composed of a cell array block A11 and a peripheral circuit A12. In general, a pattern of the same size is formed regularly in the cell array block, and the pattern width is larger and irregularly formed in the peripheral circuit than the cell array block.

2 is a die layout on a wafer according to the prior art. As shown in Fig. 2, the area on the wafer is conventionally divided into a region A in which a die is formed and a region B in which a die is not formed.

Since the wafer edges have to be incompletely fabricated, the die formed at the wafer edges is useless. In addition, when the die is formed at the wafer edge, the exposure process time is increased, so that only a complete die is placed on the wafer without intentionally placing the die at the wafer edge.

3 is a cross-sectional view of a semiconductor device manufacturing process on a wafer having a conventional die arrangement. FIG. 3 shows a cross section along line A-A 'across die A1, A2, and region B in which no die is formed in FIG.

3A is a cross-sectional view after the metal wiring 11 is formed by depositing and patterning a diffusion barrier film, a metal film and an antireflection film on the wafer 10. Die A1 and die A2 are composed of cell array centers P ₁ , P ₁₁ , cell array edges P ₂ , P ₁₂ , P ₄ and peripheral circuits P ₃ , P ₁₃ , respectively.

The line widths W ₁ of the metal wires formed at the cell array centers P ₁ and P ₁₁ and the cell array edges P ₂ , P ₁₂ and P ₄ are the same, and are formed in the peripheral circuits P ₃ and P ₁₃ . The line width W _{2 of} the metal wiring is greater than the line width W ₁ of the metal wiring formed at the cell array centers P ₁ , P ₁₁ and the cell array edges P ₂ , P ₁₂ , P ₄ . In addition, the metal diffusion line, the metal film, and the anti-reflection film are formed in the region B where the die is not disposed, and then the width W ₃ is larger than the metal wiring line widths W ₁ and W ₂ formed in the die without patterning. The metal film is left.

3B is a cross-sectional view showing that a high-density plasma oxide film 12 is formed to a thickness of 15000 kPa to 18000 kPa as an interlayer insulating film on the wafer 10 on which the metallization forming process is completed. When the high-density plasma oxide film 12 is formed thicker than the thickness of the metal wires, the high-density plasma oxide film 12 is formed on each metal wire due to the characteristics of the high-density plasma deposition method in which argon sputtering is simultaneously performed while the oxide film is deposited. The thickness of depends on the line width of the metal wiring. That is, the thickness of the oxide film formed on each metal wiring increases in proportion to the line width of the metal wiring. When the line width of the metal wiring becomes twice the thickness of the metal wiring, the thickness of the oxide film becomes constant.

Accordingly, it is the same thickness (t ₁₎ of the oxide film formed on the metal wiring line width of the same cell array center (P _1, P ₁₁₎ and the edge of the cell array _{(P 2, P 12, P} 4). In addition, the line widths W ₁ , W ₂ , and W ₃ of the metal wirings in the respective regions may include the cell array centers P ₁ and P ₁₁ , the cell array edges P ₂ , P ₁₂ , and P ₄ , and the peripheral circuits P _3. , P _13), and so the die is increased in order of the size of the area (B) is not disposed, a thickness of a high density plasma oxide film formed in the respective regions _{(t 1, t 2, t} 3) FIG cell array center (P _1, P ₁₁ ) and the cell array edges P ₂ , P ₁₂ , and P ₄ , peripheral circuits P ₃ and P ₁₃ , and regions B where no die is disposed, in order of thickness.

3 (c) shows a state in which the high-density plasma oxide film 12 having a thickness of 5000 kV to 6000 kV is left at the cell array centers P ₁ and P ₁₁ by chemical mechanical polishing of the plasma oxide film 12. .

Although the thickness t ₄ of the high-density plasma oxide film 12 remaining after polishing is constant on the die A1 disposed relatively far from the region B where the die is not disposed, it is disposed relatively close to the region B where the die is not disposed. The thicknesses t ₄ and t ₅ of the high density plasma oxide film 12 remaining on the die A2 are not constant. This is because the die A2 adjacent to the region B where no die is formed has a peripheral pattern environment different from that of the die A1, so that polishing is reduced. In addition, since the high-density plasma oxide film 12 is formed thickest in the region B where the die is not disposed, the plasma oxide film 12 having the largest thickness t ₇ remains. That is, if the thickness t ₄ of the plasma oxide film 12 remaining after polishing the peripheral circuit P ₃ of the die A1 is 5000 kV to 6000 kV, the plasma oxide film 12 remaining in the peripheral circuit P ₁₃ of the die A2 The thickness t ₆ is 6000 kPa or more.

3D is a cross-sectional view of the plasma oxide film 12 being selectively etched to form vias 13 and 13 'in the peripheral circuits P3 and P13. A peripheral circuit of the die A2 around the die A1 is a relatively thin-walled high density plasma oxide film remaining as compared to (P ₁₃₎ a circuit (P _3), the complete via (via) (13) a peripheral circuit (P ₁₃ of the die A2 is formed ), The high density plasma oxide film 12 is not completely removed, causing via failure. This is because different from a via (13) a length (D ₁₎ and via the die-A2 (13 ') the length (D ₂₎ of the die A1 due to the difference in thickness of each high-density plasma oxide film 12 remaining after the polishing.

3E is a conductive film made of an adhesion improving film, a metal film, and an anti-reflection film after excessively etching the high density plasma oxide film 12 to completely form the vias in the peripheral circuit P ₁₃ of the die A2. It is sectional drawing which shows the state which formed 14). Via 13 of die A1 is completely filled with conductive film 14, but via 13 'of die A2 is relatively deep and void 15 is not completely filled with conductive film, resulting in poor vias. There is a problem that is caused.

The present invention devised to solve the above problems is to provide a method for manufacturing a semiconductor device that can prevent the generation of steps between dies.

1 is a plan view of a die structure;

Figure 2 is a die layout on a wafer according to the prior art.

3 is a cross-sectional view of the semiconductor device manufacturing process along the line AA ′ of FIG. 2;

Figure 4 is a die layout on a wafer in accordance with one embodiment of the present invention.

FIG. 5 is a cross-sectional view of the semiconductor device manufacturing process along the line CC ′ of FIG. 4; FIG.

* Description of the main parts of the drawing

A11: In-Day Cell Array Block Diagram A12: In-Die Peripheral Circuit

A: The area where a die is placed on a wafer in the prior art

B: The area where no die is placed on the wafer in the prior art

C: the area where the die is disposed in the prior art and the present invention

D: area where a die is newly placed according to the present invention

10, 20: wafer 11, 21: metal wiring

12, 22: high density plasma oxide film 13, 13 ', 23: via

14, 24: conductive film

The present invention for achieving the above object, a first step of forming a metal film on the entire surface including a wafer; Patterning the metal film to form metal wires having the same line width on the wafer; A third step of forming an oxide film using a high density plasma on the entire surface of the wafer where the second step is completed; And a fourth step of chemically mechanical polishing the oxide film.

The present invention is characterized by preventing the occurrence of steps due to the formation of a high density plasma oxide film by disposing a die to the edge of the wafer even if it is not a complete die to form metal wiring having the same line width as the center of the wafer at the edge of the wafer.

Forming a die over the entire wafer area results in all dies having the same peripheral pattern environment, the same portion within the die. That is, it is possible to prevent a step from occurring after polishing the interlayer insulating film in the cell array or the peripheral circuit, thereby ensuring uniform flatness and stable via characteristics.

Figure 4 is a die layout on a wafer according to one embodiment of the invention, showing die areas C disposed at the center of the wafer and die areas D disposed at the wafer edge in accordance with the present invention as in the prior art. .

5 is a cross-sectional view of a semiconductor device manufacturing process on a wafer with a die arrangement in accordance with the present invention. FIG. 5 shows a cross section along line C-C 'cutting the die C1, die C2 of FIG. 4 and the die region D newly arranged in accordance with the present invention.

Referring to Fig. 5, a semiconductor device manufacturing process on a wafer having a die arrangement according to the present invention will be described.

FIG. 5A is a cross-sectional view after the diffusion barrier film, the metal film and the antireflection film are deposited and patterned on the wafer 20 to form the metal wiring 21. Die C1 and die C2 are composed of cell array centers P ₂₁ , P ₃₁ , cell array edges P ₂₂ , P ₃₂ , P ₂₄ , and peripheral circuit areas P ₂₃ , P ₃₃ , respectively.

The line widths W ₁ of the metal wirings formed at the cell array centers P ₂₁ and P ₃₁ and the cell array edges P ₂₂ , P ₃₂ , and P ₂₄ are the same, and are located in the peripheral circuit areas P ₂₃ and P ₃₃ . The line width W _{2 of} the metal wires formed is larger than the line width W ₁ of the metal wires formed at the cell array centers P ₂₁ and P ₃₁ and the cell array edges P ₂₂ , P ₃₂ , and P ₂₄ . In addition, according to the present invention, the metal wirings having the same line widths W ₁ and W ₂ as those of the metal wirings formed on the dies C1 and C2 are formed, although not completely, in the region D where the die is newly placed.

5B is a cross-sectional view showing that the high-density plasma oxide film 22 has a thickness of 15000 kPa to 18000 kPa as an interlayer insulating film covering the entire structure of the wafer 20. The thickness t ₁ of the high density plasma oxide film 22 formed at the cell array centers P ₂₁ , P ₃₁ and the cell array edges P ₂₂ , P ₃₂ , P ₂₄ having the same metal wiring line width is the same. In addition, the line widths W ₁ and W ₂ of the metal wirings in the respective regions are set to the cell array centers P ₂₁ and P ₃₁ , the cell array edges P ₂₂ , P ₃₂ , and P ₂₄ , and the peripheral circuits P ₂₃ and P _33. ), The thicknesses t1 and t2 of the high-density plasma oxide films formed in the respective regions are also determined by the cell array centers P ₂₁ and P ₃₁ and the cell array edges P ₂₂ , P ₃₂ , and P ₂₄ . It increases in the order of the circuits P ₂₃ and P ₃₃ . At this time, unlike the prior art, since the die is formed at the wafer edge in the present invention, the thickness of the plasma oxide film 22 formed at the wafer edge is not thicker than the thickness of the high density plasma oxide film formed on the die C1 and die C2 regions.

5C is a cross-sectional view showing a state in which the plasma oxide film 22 is chemically mechanically polished to leave a plasma oxide film 22 having a thickness of 5000 to 6000 mV at the cell array centers P ₂₁ and P ₃₁ . After polishing, the plasma oxide film 22 having the same thickness t ₃ remains on the entire surface of the wafer.

FIG. 5D is a cross-sectional view illustrating a via 23 formed in the peripheral circuit P ₂₃ of the die C1 and the peripheral circuit P ₃₃ of the die C2 by selectively dry etching the plasma oxide film 22. to be. Since the thickness of the oxide film remaining after polishing is uniform, the length d of the via 23 is also the same, so that a complete via 23 is formed in the peripheral circuit P ₂₃ of the die C1 and the peripheral circuit P ₃₃ of the die C2. .

5E is a cross-sectional view showing a state where a conductive film 24 made of an adhesion improving film, a metal film and an antireflection film is formed. The conductive film 24 is completely filled in the vias 23 formed in each die, so that good device characteristics can be obtained.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

In the present invention as described above, since the dies are formed in the entire wafer area, each die has the same peripheral environment, and thus, it is possible to prevent the generation of the step difference between the dies after chemical mechanical polishing. In addition, it is possible to ensure a layer having a uniform thickness even in the die located at the wafer edge, and it is possible to prevent via defects generated due to different layer thicknesses, thereby improving device yield.

Claims (2)

In the semiconductor device manufacturing method, Forming a metal film on an entire surface of the wafer including an edge; Patterning the metal film to form metal wires having the same line width on the wafer; A third step of forming an oxide film using a high density plasma on the entire surface of the wafer where the second step is completed; And A fourth step of chemically mechanical polishing the oxide film A semiconductor device manufacturing method comprising a. The method of claim 1, After the fourth step, Selectively etching the oxide film to form vias exposing the metal wires; And And depositing a conductive film on the entire structure where the fifth step is completed to form a conductive film connected to the metal wiring through the via.