KR20000013037A - Data transmitting-receiving circuit and method thereof - Google Patents

Abstract

PURPOSE: A data transmitting-receiving circuit and a method thereof are provided to reduce the EMI radiation generated in data transmission. CONSTITUTION: The data transmitting-receiving circuit comprises: the first data terminal; the second data terminal; a conversion unit converting parallel data into a single pulse signal corresponding to the parallel data and the signal complementary to the parallel data to output them through said first and second data terminals during transmitting data to an outdoor circuit; and a recovery unit inputting said single pulse signal and said complementary signal through said first and second data terminals to recover to the data having the first pulse width displaying the data transmission start and the second pulse width corresponding to the absolute value of said data.

Description

DATA TRANSMISSION / RECEIPT CIRCUIT AND METHOD THEREOF

The present invention relates to a data transmission / reception circuit and a method thereof, and more particularly, to a data transmission / reception circuit and a method for displaying and transmitting transmission data according to the length of one pulse signal.

When data is transmitted serially between an integrated circuit (IC) or integrated circuits, generally, a synchronous input / output scheme, a universal asynchronous receiver / transmitter scheme, I ² C BUS system is used.

The synchronous input / output method requires a clock line for synchronizing and a data line for transmitting data. In other words, two lines are basically required for data transmission. In addition, the scheme is a redundant line for enabling / disabling a corresponding integrated circuit for data transmission / reception between several integrated circuits (ICs), and a dedicated line for transmitting and receiving data in series. It requires a control block, ie a receiver / transmitter circuit. The UART method also requires a dedicated transmit / receive circuit for transmitting and receiving data serially, and has a disadvantage in that the data transmission / reception rate is limited. In addition, the I ² C BUS method also requires a dedicated transmission / reception circuit for transmitting and receiving data in series.

As described above, the transmission and reception circuit employing the conventional communication schemes has a problem in that the area occupied by the integrated circuit is large. In addition, in an integrated circuit employing the above communication schemes, there is a problem in that electromagnetic interference (EMI) noise is emitted when a state of a clock line or a data line changes.

On the other hand, in order to confirm whether the received data is received as a valid signal from the receiving side, generally, a method of detecting an error using parity or a complementary value of data to be transmitted are received together. On the other hand, methods have been used to detect this error. However, these error detection methods can be achieved by a dedicated transmission / reception circuit having a complicated function for checking an error, and the error detection method itself has a very complicated problem.

Accordingly, an object of the present invention is to provide a data transmission / reception circuit and a method for reducing EMI radiation generated during data transmission.

It is another object of the present invention to provide a highly integrated data transmission / reception circuit.

It is still another object of the present invention to provide a data transmission / reception circuit and a method thereof capable of quickly and simply checking whether transmission data is transmitted as a valid signal.

1 is a block diagram showing a connection relationship of a data transmission / reception circuit according to the present invention;

2 is a waveform diagram showing waveforms of a pulse signal and its complementary signal representing transmission data according to the present invention;

FIG. 3 is a diagram showing a configuration of a pulse signal transmitted through the data line DL of FIG. 1;

4 shows the length of pulse signals representing respective data according to a preferred embodiment of the present invention;

5 is a block diagram showing a configuration of a data transmission circuit according to a preferred embodiment of the present invention;

6 is a block diagram showing a configuration of a data receiving circuit according to a preferred embodiment of the present invention;

FIG. 7 shows waveforms of a pulse signal output from the data transmission circuit of FIG. 5 and its complementary signal; FIG.

FIG. 8 is a view showing waveforms of input signals of the data receiving circuit of FIG. 6 and an acknowledgment signal generated when an input pulse signal is not error-processed; FIG.

9A and 9B are waveform diagrams showing an example of a method for checking for occurrence of an error; And

10 is a waveform diagram illustrating various examples of compressing and transmitting transmission data.

* Explanation of symbols on the main parts of the drawings

100: data transmission circuit 120: data receiving circuit

140, 440: data processing unit 160: encoder

180: buffer 200, 460: clock generator

220, 540: processor 240, 560: memory

260: control signal generator 280: pulse generator

300, 480: Divider 320: Switch

340, 500: counter 360, 520: register

380: comparator 400: switch deactivator

420, 420a: decoder

According to one aspect of the present invention for achieving the above object, a data transmission / reception circuit for transmitting and receiving data includes: a first data terminal; A second data terminal; Converting means for converting parallel data into a single pulse signal corresponding to the data value and its complementary signal while outputting data to the external circuit, and outputting the data through the first and second data terminals, respectively; While receiving data from the external circuit, the single pulse signal and its complementary signal are respectively input through the first and second data terminals to indicate a first pulse width and an absolute start of the data. Restoring means for restoring the data having a second pulse width corresponding to the value.

According to another aspect of the present invention, a data transmission / reception method includes: receiving transmission data in data transmission, generating and transmitting a single pulse signal by adding a number of unit pulses (Ud) corresponding to the input data; The single pulse signal is received at data reception, and the single pulse signal is divided into unit pulses and restored to the original data.

In this embodiment, the data transmission / reception method further comprises: transmitting a pulse signal having the same duration and an inverted voltage level in the single pulse signal during data transmission; If the single pulse signal and the inverted pulse signal do not have the same duration when receiving data, it is determined as a transmission error.

In this embodiment, when the same data is transmitted two or more times in succession, the single pulse signal, the pulse signal having the same duration and inverted voltage level, and the same number of repetitions of the same data having the same voltage level as the single pulse Transmit including the pulse signal to which the unit pulse is added by the number corresponding to.

(Example)

Reference drawings according to embodiments of the present invention will be described in detail with reference to FIGS. 1 to 10.

5 and 6, a data transmission / reception circuit as a preferred embodiment of the present invention includes a data transmission circuit 100 and a data reception circuit 120. The data transmission circuit 100 transmits parallel data to be transmitted in a single pulse signal (PData) corresponding to this data value and its complementary signal ( ) And convert the pulse signal (PData) and its complementary signal ( ) Is transmitted to the data receiving circuit 120. The pulse signal PData has a first pulse width D0 indicating the start of transmission of the data and a second pulse width SUd corresponding to the absolute value of the data. The second pulse width SUd has a duration that is proportional to the unit pulse signal Ud that indicates the unit data value. The first pulse width D0 may be the same as or different from the width of the unit pulse signal Ud. The data receiving circuit 120 includes the pulse signal PData and its complementary signal ( ) And restore the parallel data from the width SUd of the second pulse. Thus, the data transmission / reception circuit according to the present invention can reduce EMI radiation generated during data transmission, and the process of checking whether data is transmitted to its original value is simple and quick. In addition, since a simple hardware configuration can be designed to have a quick and easy error detection function, a highly integrated data transmission / reception circuit is provided.

1 is a block diagram showing a connection relationship of a data transmission / reception circuit according to the present invention. FIG. 2 is a diagram illustrating pulse signals of transmission data and waveforms of complementary signals thereof according to the present invention, and FIG. 3 is a diagram illustrating a configuration of a pulse signal transmitted through the data line DL of FIG. 1. 4 is a diagram illustrating lengths of pulse signals representing respective data according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the data transmitting / receiving circuit 100 and the data receiving circuit 120 respectively include first data transfer / receiver terminals T1 and T3 and second data transmission. A second data transfer / receiver terminal T2 and T4, and the corresponding terminals T1 and T3, T2 and T4 respectively correspond to the first data line DL. Second data line ( Is connected via). The data transmission circuit 100 transmits a single pulse signal PData through the first data line DL and the second data line Complementary signal of the pulse signal (PData) ) Is transmitted to the data receiving circuit 120. The data transmission circuit 100 and the data reception circuit 120 will be described in detail with reference to FIGS. 5 and 6 to be described later.

Referring to Fig. 2, reference numeral 1 is logically a high level position, and reference numeral 2 is logically a logical low level position. Reference numbers (3) and (4) logically at high level positions indicate when no data transmission is performed, and reference numbers (7) at logically low level positions indicate when data transmission is performed. Indicates. At this time, the reference number 5, i.e., the falling edge of the first data line DL, indicates the start of data transmission, and the reference number 6, i.e., the rising edge of the first data line DL, rising edge) means termination of data transmission. In other words, the actual data transmission corresponds to the section indicated by reference numeral 7 above, and the data is displayed as the length of the low level corresponding to the section. And the second data line ( ) Is a phase in which the first data line DL is inverted, and a substantial data transmission interval logically corresponds to a high level reference number (8).

Referring to FIG. 3, reference symbol D0 indicates a first pulse duration representing data '0'. Reference symbol SUd indicates a second pulse duration representing the sum SUd of the unit pulse signal Ud representing data '1'. Here, the first pulse width D0 may be the same as or different from the pulse width of the unit pulse signal Ud. Obviously true, but the second data line ( The pulse signal on C) has the same pulse duration as the phase of FIG. 3 is inverted.

As shown in Fig. 4, the data '0' is represented by the first pulse width D0, and the remaining data (1) to (n) (where n is an integer) is also the first pulse width DO. The unit pulse signal Ud corresponding to the data is added to the data. Here, the first pulse width D0 is represented by the same duration as the pulse width of the unit pulse signal Ud. In other words, when the value of data to be transmitted is 0, the second pulse width SUd is 0 and the first pulse width D0 is equal to the width of the unit pulse signal Ud. In addition, it is apparent to those skilled in the art that the first pulse D0 and the unit pulse signal Ud have the same phase but may be expressed in opposite phases to each other.

5, there is shown a block diagram showing the configuration of a data transmission circuit in accordance with a preferred embodiment of the present invention.

The data transmission circuit 100 transmits the data to be transmitted to the pulse signal PData and its complementary signal ( ) And the signals PData and ( ) Is output to the corresponding first and second data transmission terminals T1 and T2. Here, the data to be transmitted is applied from the outside of the data transmission circuit 100 and is transmitted in parallel or in series.

The pulse signal (PData) and its complementary signal ( ) Has a first pulse width D0 indicating the start of transmission of the data and a second pulse width SUd proportional to the absolute value of the data. For example, when the value of data to be transmitted is 5, the duration of the unit pulse signal Ud indicating data of 1 is 100ns, and the duration of the first pulse D0 is also 100ns, the pulse signal PData has a duration 100ns of the first pulse D0 and a duration 100ns × 5 corresponding to the value of the data to be transmitted. That is, the duration of the pulse signal PData has 600 ns. The first pulse width D0 represents data 0 when the second pulse width SUd is zero. In addition, the first pulse width DO is added to the data to be transmitted so that the pulse signal PData is stably received at the receiving side.

The data transmission circuit 100 includes a data processor 140, an encoder 160, a buffer 180, and a clock generator 200. The data processor 140 includes a processor 220 and a memory 240 and receives a data D applied from the outside and has a duration of the first pulse D0 at a value of the data D. The transmission data TD to which the value of data (0 in the preferred embodiment is added) is added. After the transmission is completed, the processor 120 detects whether an acknowledgment signal indicating that the transmission data TD has been transmitted as valid data is received from the receiving side, and the pulse signal PData and its complement are received. signal ( It is determined whether or not to retransmit. The memory 240 stores a processing program and transmission data of the processor 220.

The encoder 160 receives the clock signal CLK1 and the transmission data TD supplied from the clock generator 200 and encodes the transmission data TD into the single pulse signal PData ( encoding). The encoder 160 includes a control signal generating section 260 and a pulse generating section 280. The pulse generator 280 may include a divider 300, a switch 320, a counter 340, a register 360, and a comparator 380. And a switch disable section 400.

The control signal generator 260 is configured to switch on the switch 320 when the transmission data TD is applied from the data processor 140 and the counter 340. Generate a second control signal (Reset) to initialize the. The divider 300 receives the clock signal CLK1 and divides the clock signal CLK1 to be synchronized with the unit pulse width Ud. This operation is to adjust the communication speed of the transmitting / receiving side. That is, when the clock frequency of the transmitting side and the clock frequency of the receiving side do not coincide, smooth communication can be ensured by synchronizing the divided clocks of both sides with the unit pulse width Ud.

The counter 340 is initialized by the second control signal Reset. Thereafter, the counter 340 starts a count operation in synchronization with the clock signal DCLK1 supplied through the switch 320 activated by the first control signal SWE. The register 360 stores the transmission data 360 provided from the data processing unit 140. When the counter 340 starts a counting operation, the comparator 380 outputs a pulse signal PData that transitions from a high level to a low level, as shown in FIG. 7. Thereafter, the comparator 380 compares the value counted by the counter 340 with the value of the transmission data TD stored in the register 360 to match the values of the two data when the values of the two data coincide. Stop the occurrence of). That is, the pulse signal PData at the low level is shifted to the high level.

Subsequently, the switch deactivator 260 generates a signal SWD for switching off the switch 320 when the pulse signal PData transitions from a low level to a high level. Thus, since the switch 320 is switched off, the clock signal DCLK1, which has been supplied to the counter 340 through the switch 320, is cut off, and as a result, the pulse signal () from the comparator 380 is cut off. PData) is not output. In addition, the output unit 180 receives the pulse signal PData output from the encoder 160, and the pulse signal PData and its complementary signal ( ) Are simultaneously output to the first and second data transmission terminals T1 and T2. The output unit 180 includes one inverter IV1 and one buffer B1.

6, there is shown a block diagram showing the configuration of a data receiving circuit according to a preferred embodiment of the present invention.

The data receiving circuit 120 includes the first and second data lines DL and ( The pulse signal (PData) and its complementary signal transmitted through ) Is received through the first and second data transmission terminals T3 and T4 and recovers the transmission data TD from the width of the second pulse SUd. The data receiving circuit 120 may include the two signals PData and ( By comparing the values of the data corresponding to), it is determined whether the received pulse signal (PData) is received as a valid signal (valid signal). Subsequently, when received as a valid signal, the data receiving circuit 120 informs the transmitter 100 of the acknowledgment signal for informing that the pulse signal PData has been transmitted as a valid signal, that is, a signal that does not contain noise. transmit an acknowledgment signal through one of the first data transmission terminal T3 or the second data transmission terminal T4 (eg, the first data line DL).

The data receiving circuit 120 includes first and second decoders 420 and 420a, a data processor 440, and a clock generator 460. The first decoder 420 receives the pulse signal PData transmitted by the first data line DL through the first data transmission terminal T3 and corresponds to the pulse signal PData. Convert to a data value. In addition, the second decoder 420a uses the second data line ( Complementary signal of the pulse signal (PData) transmitted by ) Is received through the second data transfer terminal T4, so that the complementary signal of the pulse signal PData ( To the value of the corresponding data. The first decoder 420 is composed of a divider 480, a counter 500, and a register 520. Since the divider 380 is used for the same purpose as that of the data transmission circuit 100, a description thereof is omitted here.

The counter 500 is controlled by the pulse signal PData. For example, when the level of the first data line DL, to which the pulse signal PData is transmitted, transitions from a high level to a low level, that is, when information indicating transmission start is applied, the counter 500 Is initialized. The counter 500 sequentially starts counting operations according to the clock signal DCLK2 divided by the divider 480. Thereafter, when the pulse signal PData is applied from the low level to the high level, that is, the information indicating the end of the transmission, the counter 500 is deactivated, and the value RD1 finally counted by the counter 500 is applied. ) Is stored in the register 520. Since the second decoder 420a also has the same configuration as the first decoder 420, the drawings and description thereof are omitted here for convenience. The second decoder 420a also performs the above-described series of operations to perform a complementary signal of the pulse signal PData ( We will calculate the data value RD2 corresponding to).

The data processor 440 includes a processor 540 and a memory 560, and values RD1 and RD2 of the data calculated by the first and second decoders 420 and 420a. By comparing the received pulse signal (PData) or complementary signal ( ) Is determined as a valid signal. If it is determined as a valid signal, as shown in FIG. 8, the data processing unit 440 restores the transmission data TD from the width of the second pulse SUd, and receives that it is received as a valid signal. The alert generates an acknowledgment signal. In FIG. 8, a section that is maintained at a high level for a predetermined time period before the acknowledgment signal is generated represents a time required for the processor 440 to determine. On the contrary, if it is not a valid signal as a result of the determination, the received pulse signal PData is treated as an error. When the acknowledgment signal is not generated, the data transmission circuit 100 retransmits the pulse signal PData.

Next, an example of a method for detecting an error that may occur during data transmission and reception will be described in detail with reference to FIGS. 9A and 9B. 9A and 9B show waveform diagrams showing an example of a method for checking for error occurrence.

Referring to FIG. 9A, for example, in case of transmitting data '0', the transmitting side transmits a low level signal having a first pulse width DO, followed by the first pulse width DO. Transmit high level signals with the same width. Then, the low level discrimination signal 9 having a predetermined width is transmitted again, and returns to the high level again. The receiving side may determine whether an error has occurred by comparing the low level section and the corresponding high level section at the time of data reception and comparing them with each other. In the case of transmitting data '1', data may be transmitted in the same manner as described above as shown in (b). The waveform diagram shown in FIG. 7B illustrates a case where data transmission is performed in a high level period.

As described above, when the same data is repeatedly transmitted when the data transmission is transmitted in the form of a single pulse, the data can be effectively compressed. FIG. 10 is a waveform diagram illustrating various examples of compressing and transmitting transmission data.

Referring to FIG. 10, for example, when transmitting '0', the low level signal 10 having the first pulse width D0 is transmitted as in the case of (a), followed by the high level signal having the same pulse width. (11), and then again transmits a low level signal 12 of the same pulse width. In the case of transmitting '0' twice, the low level signal 10 having the first pulse width D0 is transmitted as in the case of (b), followed by the high level signal 11 having the same pulse width, and then The low level signal 13 to which the first pulse width D0 and the unit pulse width Ud are added is transmitted. In this case, when '3' is repeatedly transmitted five times, as in the case of (c), the low-level pulse signal 20 in which the first pulse width D0 and the unit pulse width Ud are added is added. Then, the high level signal 21 having the same pulse width is transmitted, followed by the low level signal 22 in which the first pulse width DO and the unit pulse width Ud are added. According to the data compression method as described above, repeated data can be effectively compressed and transmitted.

According to the embodiment of the present invention described so far, the data transmission circuit 100 converts data for transmission into a first pulse width D0 and a second pulse width SUd, and Complementary signal ( ) May be transmitted to the data receiving circuit 120. The data receiving circuit 120 may include the pulse signal PData and a complementary signal thereof. ) To restore the data. As a result, by transmitting / receiving data in a single pulse signal (PData), it is possible to reduce the EMI radiation generated by the clock and data transition in the conventional data transmission. In addition, the data receiving circuit 120 includes the signals PData and ( By simply comparing the widths of the circuits and detecting the error, error detection is easier than in the conventional data transmission / reception method. As such, the data transmission / reception circuit can be highly integrated when it is implemented as an integrated circuit because the hardware configuration for performing easy error detection is simple.

Although the data transmitting / receiving circuit of FIG. 1 described above is composed of a data transmitting circuit 100 and a data receiving circuit 120, as is well known to those skilled in the art, the data transmitting / receiving circuit Can be divided into transmit, receive, and transmit and receive. For the convenience of understanding, the data transmission / reception circuit of FIG. 1 is shown for transmission and reception, respectively. However, the technical idea or concept of the present invention can be applied to both the transmission and reception, and that they can be integrated into one chip and used as an interface for data transmission and reception. It is self-evident to those who have acquired common knowledge.

As described above, the integrated circuit for data transmission / reception according to the present invention and a method thereof include data in a single pulse signal (PData) and its complementary signal ( By transmitting / receiving), EMI radiation generated during data transmission can be reduced, and error detection of data transmitted / received is easy. In addition, the present invention can provide a highly integrated data transmission / reception circuit.

Claims (4)

In a data transmission / reception circuit for transmitting and receiving data: A first data terminal; A second data terminal; Converting means for converting parallel data into a single pulse signal corresponding to the data value and its complementary signal while outputting data to the external circuit, and outputting the data through the first and second data terminals, respectively; While receiving data from the external circuit, the single pulse signal and its complementary signal are respectively input through the first and second data terminals to indicate a first pulse width and an absolute start of the data. And recovery means for restoring data having a second pulse width corresponding to the value. In the data transmission / reception method: Receiving transmission data in data transmission, generating and transmitting a single pulse signal by adding unit pulses Ud corresponding to the input data; And receiving the single pulse signal at data reception, dividing the single pulse signal into unit pulses, and restoring the single pulse signal into original data. The method of claim 2, The data transmission / reception method is In the data transmission, the single pulse signal has the same duration and the voltage level is transmitted including the inverted pulse signal. The data transmission and reception method, characterized in that for determining the transmission error if the single pulse signal and the inverted pulse signal does not have the same duration. The method of claim 2, If you send the same data more than once in a row And transmitting the single pulse signal, the pulse signal having the same duration and inverted voltage level, and the pulse signal having the same voltage level as the single pulse and the unit pulse added with the number corresponding to the number of repetitions of the same data. How to send / receive data.