KR20000010115A - Erasing method in a flash memory device - Google Patents

Abstract

PURPOSE: An erasing method in a flash memory device is provided to have a cell have a normal erasing threshold voltage so that the cell may not be over-erased by carrying out an afterward program at regular intervals during an erasing operation. CONSTITUTION: The erasing method comprises the steps of: initializing(S300) an address; carrying out(S302) a previous program which programs in the case of an erased cell and leaves the cell as it is by changing the address of a desired sector; carrying out(S304) the previous program(S302) again if any one of overall cells is not programmed; comparing(S306) the sector address with a last sector address when the previous program is carried out normally; carrying out(S308) the previous program regarding other sectors by increasing the sector address if the sector address is the last one; initializing(S310) the address for an erasing operation if the previous program is carried out regarding the last sector; erasing(S312) by applying an erase bias to every cell of the first sector; carrying out(S314) an afterward programming which increases a threshold voltage of an over-erased cell to that of a normally erased cell by applying an afterward programming bias to cells of columns in a sector after a predetermined repetition of erasing; determining(S316) whether the cells are erased normally and carrying out(S312) the erasing operation when the cell erasion is not completed; finishing(S318) the erasing operation if the sector address is the last sector address when every cell of the sector is erased; and carrying out(S312) the erasing operation again for erasing the next sector by increasing a sector address if the sector address is not last one.

Description

How to erase flash memory

The present invention relates to a method of erasing a flash memory, and more particularly, in a case of performing a post-program after erasing all cells during erasing of a flash memory, cells that are over-erased according to cell characteristics are not post-programmed or post-programmed. The present invention relates to a method of erasing a flash memory to perform post-programming at regular intervals while erasing cells in order to solve a problem in that it does not operate normally due to a long time.

The memory refers to a device that stores data and can be read out when needed. There are various types of memory, such as semiconductor memory based on DRAM, magnetic disks, and optical disks. Among them, semiconductor memory is small, high reliability and low price, and relatively high speed operation is possible, so it is developing and disseminating very rapidly.

Compared to magnetic memory and optical memory, semiconductor memory is inferior in terms of capacity, but because of its fast operation speed, it is used as a memory for storing only frequently used data by placing closer to the CPU.

Semiconductor memories can be broadly divided into random access memory (RAM) and read only memory (ROM). RAM is a so-called volatile memory device that randomly writes, stores, and reads data. When the power is cut off, so-called volatile memory device loses data. On the other hand, ROM can read data on the chip freely, even though the user can read data. It is divided into a programmable PROM (Programmable ROM) that can be inserted and an OT-PROM (One Time Programmable ROM) that allows only one programming.

The OT-PROM has a factory-programmable mask ROM and a user-programmable fuse ROM for the chip manufacturing process. The PROM is an erasable PROM (EPROM) and an electrically erasable PROM (EEPROM).

EPROM refers to erasing the entire cell of a chip at once by irradiating UV light through a quartz glass window attached to the package. EEPROM refers to erasing using tunneling phenomena generated when a large electric field is applied.

In particular, instead of erasing by byte (8-bit) unit, EEPROM that erases cells at once by block unit is called flash memory.

The flash memory uses floating gates to increase the threshold voltage of the cell transistors by injecting electrons into the floating gates, and the erase operation extracts the electrons in the floating gates so that the floating gates have no electrons. It is the operation to lower the threshold voltage by making it into a state.

When the threshold voltage of the flash memory that has been programmed or erased is 6V during programming and 2V when erased, when 5V is applied to the word line connected to the upper gate, the programmed cell is turned off and the erased cell turns on and flows. The cell programmed by determining the difference in current is determined as "1" and the cell erased as "0".

The erasing operation will be described in detail during the programming or erasing of data in the flash memory.

In the multi-sector erasing operation, a negative charge pumping is performed after waiting for about 100 ms after receiving a sector address to generate a high voltage negative voltage. The negative voltage generated as described above is applied to the floating gate to remove electrons from the floating gate, and then erases the charged pump voltage to the original voltage.

After verifying that the erase operation has been performed normally, if the erase operation is not performed normally, the erase operation is performed again. If the erase operation is completed, the erase operation is judged to be over-erased. Complete and return to normal reading.

1 is a flowchart sequentially illustrating a conventional method of erasing a flash memory.

As shown here, first, an address is initialized (S100). Then, if the cell is programmed while changing the cell address of the sector to be erased, the preprogrammed program is performed in the case of the erased cell (S102).

If the preprogram is not executed by checking whether all cells in the sector have been programmed by performing the preprogram, the preprogram is executed again (S102). When the preprogram is normally completed, it is compared whether the sector address is the last (S106). If the sector address is the last one, the sector address is increased and other sectors are also preprogrammed (S102).

However, when the preprogram is executed to the last sector, the address is initialized again for the erase operation (S110).

The erase is performed by applying an erase bias to all cells of the first sector (S112). Then, it is checked whether all the cells are erased, and if one cell is not erased again, the erase operation is performed again (S112).

However, when the erasing is completed, it is compared whether or not the sector address currently erased to erase another sector is the last sector address (S116). In this case, when the sector address is not the last, the sector address is increased in order to continue erasing (S112).

After erasing is performed to the last sector, the address is initialized again for a later program (S120).

Then, it is compared whether the erased cell is over erased (S122). If the result of comparison is over-erased, a post-programming bias is applied in column units within the sector to raise the threshold voltage of the over-erased cell to the threshold voltage of a normal erase cell (S124).

When the post-program is applied to the gate of the cell in the same way, the threshold voltage is increased by the post-programming bias when it is over-erased, and there is no change when it is normally erased.

After all columns are programmed in this sector, it is determined whether the last sector is performed by comparing the sector address, and if the last sector is completed, the erase operation is terminated (S126). However, in this case, if it is not the last sector, the sector address is increased to perform a later program in another sector (S128).

In brief description of the above-described erasing method, all cells are pre-programmed and then the cells are erased. Only after all cells have been completely erased, a post-program for removing the erased cells is performed and the erase operation is completed.

2 is a graph showing the threshold voltage distribution of a cell erased by the above erase method.

Here, (a) is a distribution of the erased threshold voltage to have a high erase threshold voltage, (b) is a distribution of the erased threshold voltage to have a low erase threshold voltage.

As shown here, the 'A' graph shows the distribution of the preprogrammed state, the 'B' shows the distribution of the non-postprogrammed state, and the 'C' shows the distribution of the postprogrammed state.

If you look at the state before the post-program as above, you can see that there are a lot of over-erased cells. In particular, it can be seen that more cells are over-erased than those having a low erase threshold voltage than those having a high erase threshold voltage.

In the case of erasing by this method, all the cells are erased until the erasure is completed. Thus, in the case of a cell that is quickly erased due to the characteristic difference of the cell, the possibility of being erased by repeated erase operation is increased due to the late erased cell. . Since the erased cells may be recognized as erased due to the leakage current of the over erased cells, the erase may be recognized as being completed even though the erase is not completed. .

After the program is overerased, the cells that have been erased disappear after the program disappears, so that the cells that have been erased may reappear and erase may not be completed normally.

Therefore, when the cell is erased due to this problem, when the erase threshold voltage is set to be close to '0', it can be seen that the over-erased cell increases as shown in (b). Therefore, when there are many over-erased cells, a large amount of time is required for the post-program, and there is a problem that the post-program may not operate normally because the leakage current of the bit line increases due to the over-erased cells.

On the other hand, if the over-programmed cell is in the bit line because the post-program does not operate normally, if a voltage is applied to the gate to read the cell programmed in the bit line, the programmed cell is normally The problem is that it becomes unreadable.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to perform a post-program at regular intervals while repeatedly performing an erase after performing a preprogram on all cells. According to an aspect of the present invention, there is provided a method of erasing a flash memory in which cells that are quickly erased and are erased by repeated erase operations have a normal erase threshold voltage.

1 is a flowchart sequentially illustrating a conventional method of erasing a flash memory.

FIG. 2 is a graph showing a distribution of threshold voltages according to a conventional erase method of a flash memory. (A) is a graph showing a high erase threshold voltage, and (B) is a graph showing a low erase threshold voltage.

3 is a flowchart sequentially illustrating a method of erasing a flash memory according to the present invention.

4 is a graph illustrating a distribution of threshold voltages according to an erase method of a flash memory according to the present invention, (a) is a graph showing a high erase threshold voltage, and (b) is a graph showing a low erase threshold voltage.

The present invention for realizing the above object is a method of erasing a flash memory to perform a post program after all cells are completely erased, characterized in that the post program is performed at regular intervals while the erase is performed. .

The erase method described above is performed at regular intervals while the erase operation is repeated to prevent the memory cells from being erased excessively by being erased by the cells which will not be erased despite being erased earlier than other cells due to the characteristics of the cells. After the program is over-programmed, the over-erased cell is programmed to continue erasing for the cells that are not to be erased.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

3 is a flowchart sequentially illustrating a method of erasing a flash memory according to an exemplary embodiment of the present invention.

As shown here, first, an address is initialized (S300). Then, if the cell is programmed while changing the cell address of the sector to be erased, the preprogrammed program is performed in the case of the cell that has been left out (S302).

If the preprogram is not executed by checking whether all cells in the sector have been programmed by performing the preprogram, the preprogram is again performed (S302). When the preprogram is normally completed, it is compared whether the sector address is the last (S306). If the sector address is the last one, the sector address is increased and other sectors are also preprogrammed (S302).

However, when the preprogram is executed to the last sector, the address is initialized again for the erase operation (S310).

Erasing is performed by applying an erase bias to all cells of the first sector (S312). After the erase operation is performed a predetermined number of times, a post-programming bias is applied in the column unit in the sector to perform the post-program to raise the threshold voltage of the erased cell to the threshold voltage of the normal erase cell (S314). After the program is executed, the cell is erased normally. If not, the erase operation is performed again (S312).

However, when all the cells in the sector have been completely erased, the sector address is compared to determine whether it is the last sector address, and if it is the last sector address, the erase operation is terminated (S318). However, if it is not the last sector address at this time, the erase is performed by increasing the sector address (S312) to erase the next sector (S320).

The erase operation is performed while the program is erased while performing the erase operation.

4 is a graph illustrating a distribution of threshold voltages according to an erase method of a flash memory according to an exemplary embodiment of the present invention, (a) is a graph showing a high erase threshold voltage, and (b) is a graph showing a low erase threshold voltage. .

Here, (a) is a distribution of the erased threshold voltage to have a high erase threshold voltage, (b) is a distribution of the erased threshold voltage to have a low erase threshold voltage.

As shown here, graph 'A' is the distribution of preprogrammed state, 'D' is the distribution of non-programmed after the last loop of erasing operation, and 'C' is the distribution of the last loop of erasing operation. This is a distribution chart of the state where the program is executed.

Since the post program is executed at regular intervals while performing the erase operation as described above, it can be seen that the state before or after the post program is not significantly different in the last loop of the erase operation. In addition, it can be seen that the case of having a low erase threshold voltage or a case of having a high erase threshold voltage has almost similar distribution. Therefore, the erase threshold voltage can be set low to be close to '0'.

As described above, the present invention performs the post-program at regular intervals so that the cells that are erased early due to cell characteristics are excessively erased by performing the post-program at regular intervals while repeatedly erasing until all the cells are erased. While erasing is performed, there is an advantage of preventing leakage current due to excessive over-erasing.

In addition, there is an advantage that the post-program can be executed with a small load even in the operation for the post-program because it is not excessively erased, thereby reducing a lot of time.

On the other hand, by performing the post-program at regular intervals while the erase is in progress, there is an advantage that the erase threshold voltage can be set low by preventing over-erasing.

Claims (1)

A method of erasing a flash memory in which a post program is performed after all cells are completely erased, The post-program being executed at regular intervals during erasing Erasing method of the flash memory, characterized in that.