CN117912525A

CN117912525A - Nonvolatile memory and block erasing method thereof

Info

Publication number: CN117912525A
Application number: CN202311872645.XA
Authority: CN
Inventors: 郭伟峰; 朱庆军
Original assignee: Shanghai Youcun Technology Co ltd
Current assignee: Shanghai Youcun Technology Co ltd
Priority date: 2023-12-29
Filing date: 2023-12-29
Publication date: 2024-04-19

Abstract

The invention discloses a nonvolatile memory and a block erase method thereof. The nonvolatile memory includes: a memory block, a word line driver, and a logic controller; each memory block comprises a plurality of sectors, and each sector corresponds to a plurality of word line drivers; the logic controller is connected with the word line driver; the logic controller is used for triggering a word line driver corresponding to a target sector to execute an erase operation and an erase verification operation on the target sector, and storing a verification result of the erase verification operation through the word line driver; the target sector is a sector which is selected to be erased and the verification result is a sector which is failed to be verified; other sectors included in the memory block are in a non-erased state. According to the invention, on one hand, the phenomenon that the service lives of other sectors are reduced due to the fact that redundant erasing operations are carried out on other sectors can be avoided, and the phenomenon of nonuniform voltage distribution in a storage block due to the fact that other sectors are excessively erased is avoided; on the other hand, the overall erase time of the memory block can be shortened.

Description

Nonvolatile memory and block erasing method thereof

Technical Field

The present invention relates to the field of memory technologies, and in particular, to a nonvolatile memory and a block erase method thereof.

Background

Non-volatile memory is often referred to as erase operation, which is currently typically accomplished by Fowler-Nordheim tunneling (Fowler-Nordheim tunneling) effect: the stored charge or electrons are removed from the memory cell by applying a negative high voltage, e.g., -10V (volts), to the Gate of the memory cell and a positive high voltage, e.g., +8v, to bulk or p-well (p-hydrazine) to reset it to unprogrammed s (un-programmed) or erased states. There are two ways to operate on block erases (including half block and block erase) of memory at present: parallel erase, which means that all sectors included in a block perform an erase operation simultaneously, and serial erase, which means that all sectors included in a block perform an erase operation one by one. Some memory cells may retain a certain level of charge due to various factors such as process variations, wear and tear, and the number of programmed/erase operations, and the first parallel erase approach may result in non-uniform Vt voltage distribution within the memory block of the memory, which may adversely affect performance parameters such as endurance and read speed of the memory; while the second serial erase approach may alleviate the problem of non-uniform Vt voltage distribution within a memory block, the erase time is longer and may exceed the allowed time period specified for block erase as the number of program/ERASE CYCLING (program/erase cycles) increases; in addition, the charge pump charging and discharging that supplies the sector with voltage and the switching between the negative high voltage and the positive high voltage need to be performed once for each sector from the erased state to the bit-by-bit erased verified state, which also increases the overhead of the total erase time.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provides a novel optical fiber.

The invention solves the technical problems by the following technical scheme:

the present invention is directed to a nonvolatile memory and a block erase method thereof, which overcome the above-mentioned drawbacks of the prior art.

The invention solves the technical problems by the following technical scheme:

in a first aspect, there is provided a nonvolatile memory comprising: a memory block, a word line driver, and a logic controller; each memory block comprises a plurality of sectors, and each sector corresponds to a plurality of word line drivers;

The logic controller is connected with the word line driver; the logic controller is used for triggering a word line driver corresponding to a target sector to execute an erase operation and an erase verification operation on the target sector in an erase stage of executing a block erase command, and storing a verification result of the erase verification operation through the word line driver; the target sector is a sector which is selected to be erased and the verification result is a sector which is failed to be verified; other sectors contained in the storage block are in a non-erased state; the other sectors are sectors other than the target sector among all the sectors included in the memory block.

Optionally, the logic controller triggers word line drivers corresponding to each target sector to perform an erase operation on the target sector;

And/or the logic controller is further configured to clear the verification result stored by the word line driver when the verification results of all the sectors of the storage block are verification passing.

Optionally, the word line driver includes a flag register circuit and a voltage applying circuit;

The input end of the mark register circuit is connected with the first output end of the logic controller, and the output end of the mark register circuit is connected with the first input end of the voltage application circuit;

The second input end of the voltage application circuit is connected with the second output end of the logic controller, and the output end of the voltage application circuit is connected with the sector;

the logic controller outputs the verification result to the mark register circuit through the first output end so as to trigger the mark register circuit to output a verification level signal matched with the verification result to the voltage application circuit;

The logic controller also outputs the address signal of the sector to the voltage applying circuit through the second output end;

The voltage applying circuit outputs a voltage matched with the erase operation and/or a voltage matched with the erase verify operation according to the verify level signal and the address signal.

Optionally, the flag register circuit includes a flag register and an not gate;

The input end of the flag register is used as the input end of the flag register circuit, the output end of the flag register is connected with the input end of the NOT gate, and the output end of the NOT gate is used as the output end of the flag register circuit.

Optionally, the flag register comprises a static random access memory or a latch or a power down non-lost register.

In a second aspect, a block erase method of a nonvolatile memory is provided, the nonvolatile memory includes a plurality of memory blocks, each memory block includes a plurality of sectors, each sector corresponds to a plurality of word line drivers, and each word line driver is connected to a corresponding sector; the block erase method includes:

Triggering a word line driver connected with a target sector to execute an erase operation and an erase verification operation on the target sector in an erase stage of executing a block erase command;

storing, by the word line driver, a verification result of the erase verification operation;

The target sector is a sector which is selected to be erased and the verification result is a sector which is failed to be verified; other sectors contained in the storage block are in a non-erased state; the other sectors are sectors other than the target sector among all the sectors included in the memory block.

Optionally, triggering a word line driver connected to a target sector to perform an erase operation on the target sector includes:

For each erase operation, the word line drivers connected to each target sector are simultaneously triggered to perform the erase operation on the target sector.

Optionally, the triggering word line driver connected to the target sector performs an erase operation and an erase verify operation on the target sector, including:

outputting a verification result and an address signal of the sector to the word line driver to trigger the word line driver to output a voltage matched with the erase operation or a voltage matched with the erase verification operation according to the output verification result and the address signal.

Optionally, triggering the word line driver connected to the target sector to perform an erase verify operation on the target sector includes:

triggering a word line driver connected to a target sector to apply a voltage to the target sector that matches the erase verify operation;

For each target sector, reading and verifying, bit by bit, whether the voltage on the bit line comprised by the target sector falls within a voltage range matching the expected erased state;

Determining that verification results of target sectors containing the target bit lines are not passed under the condition that the voltages of the target bit lines do not fall into a voltage range matched with the expected erasing state, and continuing to execute erasing operation and erasing verification operation on all the target sectors;

And/or, under the condition that the voltage of the currently verified bit line falls into a voltage range matched with the expected erasing state, judging whether the currently verified bit line is the last bit line of the target sector where the currently verified bit line is located; when the judgment result is yes, storing the verification result of the target sector where the currently verified bit line is located as verification passing; and if not, returning to read and verify the voltage on the bit line contained in the target sector bit by bit.

Optionally, after the step of storing the verification result of the erase verification operation by the word line driver, the method further includes:

And clearing the verification result stored by the word line driver under the condition that the verification results of all the sectors of the storage block pass verification.

The invention has the positive progress effects that: after the invention executes the erasing verification operation on the sector, the verification result of the sector is recorded, then the selected erasing operation and the erasing verification operation are executed only on the sector which is not verified and is included in the block to be erased, namely the target sector, the verification result is that the sector which is verified and is included in the block to be erased is not executed with the erasing operation and the erasing verification operation, thereby avoiding the service life of other sectors caused by the redundant erasing operation on other sectors, and avoiding the non-uniform voltage distribution phenomenon in the storage block caused by the over erasing of other sectors; on the other hand, the logic controller triggers the plurality of word line drivers to perform the erase operation on the plurality of target sectors simultaneously, so as to shorten the overall erase time of the memory block.

Drawings

FIG. 1 is a circuit diagram of a memory array comprising a memory according to an exemplary embodiment of the present invention;

FIG. 2 is a schematic block diagram of a nonvolatile memory according to an exemplary embodiment of the present invention;

FIG. 3 is a circuit diagram of a portion of a non-volatile memory according to an exemplary embodiment of the present invention;

FIG. 4 is a flow chart of a method for erasing a block of a nonvolatile memory according to an exemplary embodiment of the present invention;

fig. 5 is a flowchart of a block erase method of a nonvolatile memory according to an exemplary embodiment of the present invention.

Detailed Description

The invention is further illustrated by means of the following examples, which are not intended to limit the scope of the invention.

An embodiment of the present invention provides a nonvolatile memory, which includes a memory array formed by memory cells, referring to fig. 1, the memory array includes a plurality of Word lines Word line and a plurality of Bit lines Bit line, word line numbers wl_n to wl_n-13, bit line numbers bl_m to bl_m-2. The memory cells may be, for example, transistors, each having a gate connected to a Word line, a drain connected to a Bit line, and a Source connected to a Source line Source. Transistors connected through the same Source line Source or having one bulk (or p-well) in common are referred to as memory blocks. One Sector (Sector) is typically defined in the art in a capacity of 4 kilobytes (Byte), i.e., 4 word lines for each Sector. Each memory block contains a plurality of sectors. The memory Block block_x is exemplarily shown in fig. 1 to contain other sectors in addition to the Sector sector_y and the Sector sector_y-1.

In this embodiment, the memory is erased by using the fowler-nordheim tunnel effect, and a typical erase algorithm used for a block erase command of the memory mainly includes three phases: a pre-program ALL0 phase, an erase phase, and a recovery from over-erase phase (sometimes referred to as a soft program phase). To complete the erase algorithm, each stage also needs to read the voltage Vt of the memory cell bit by bit to ensure that the voltage falls within a voltage range that matches the expected state of each stage.

Embodiments of the present invention generally relate to improvements in the erase phase of a memory, where the sectors in each memory block are the smallest unit to perform erase operations, and where the erase operations are performed on all sectors contained in the memory block selected for erasure. In some cases, it may be necessary to perform multiple erase operations on a memory block until the voltage of each memory cell in all sectors contained in the memory block falls within a voltage range that matches the intended erased state. In one implementation, the voltage of a memory cell is determined by reading the voltage on a bit line connected to the memory cell.

FIG. 2 is a schematic block diagram of a nonvolatile memory according to an exemplary embodiment of the present invention, the memory includes: a plurality of memory blocks 21, a plurality of word line drivers 22 (only one of which is exemplarily shown in the drawing), and a logic controller 23.

The nonvolatile memory includes a plurality of memory blocks 21. Each memory block 21 contains a plurality of sectors. Each sector corresponds to a plurality of word line drivers, each word line driver being coupled to a corresponding sector. Specifically, each word line driver is connected to a corresponding sector through a word line. The nonvolatile memory according to the embodiment of the present invention includes the memory block 21 including a plurality of sectors, each corresponding to 4 word lines, i.e., 4 word line drivers for each sector.

The logic controller 23 is connected to the word line driver 22. The logic controller 23 is configured to trigger the word line driver 22 connected to the target sector to perform an erase operation and an erase verify operation on the target sector and store a verification result of the erase verify operation by the word line driver 22 in an erase phase of performing a block erase command.

The target sector is a sector which is selected to be erased and the verification result is that the verification fails; the other sectors included in the memory block 21 are in a non-erased state; the other sectors are sectors other than the target sector among all the sectors included in the memory block 21.

The so-called selected erased sector, i.e. the sector comprised by the memory block 21 that the user selected to be erased.

The logic controller 23 does not trigger the word line driver 22 connected to the other sectors to perform the erase operation and/or the erase verify operation on the other sectors, so that the other sectors in the non-erased state, i.e., the sectors in which the verification result is verified in the memory block selected for the erase.

The verification is passed, that is, after an erase verification voltage is applied to the sector, the voltage of each memory cell in the sector falls within a voltage range matching the expected erased state. The verification is failed, that is, after the erase verification voltage is applied to the sector, the voltage of at least one memory cell in the sector does not fall within a voltage range matching the expected erase state.

In the embodiment of the invention, after the erasure verification operation is performed on the sector, the verification result of the sector is recorded, the erasure operation and the erasure verification operation are continuously performed only on the target sector which is not verified in the memory block which is selected to be erased, and the erasure operation and the erasure verification operation are not performed on other sectors which are selected to be erased and are verified to be passed in the verification result in the memory block which is selected to be erased, so that on one hand, the service life of other sectors is reduced due to the fact that the redundant erasure operation is performed on the other sectors, and the phenomenon of nonuniform voltage distribution in the memory block 21 due to the fact that the other sectors are excessively erased is avoided; on the other hand, the logic controller 23 may trigger the plurality of word line drivers 22 to perform the erase operation on the plurality of target sectors at the same time to shorten the overall erase time of the memory block 21.

In one embodiment, for each erase operation, if the number of target sectors is at least two, the logic controller triggers the word line driver connected to each target sector to perform the erase operation on the target sector at the same time, that is, perform parallel erase on each target sector, so as to reduce the erase duration of the memory block and improve the erase efficiency.

It can be appreciated that for each erase operation, the number of target sectors is determined based on the verification result of the previous erase verification. For example, one memory block has 16 sectors, and in the verification results of the previous erase verification, 6 sectors are verified, and then the 6 sectors are other sectors, the remaining 10 sectors in the memory block are target sectors, and the next erase operation is performed on the 10 target sectors in parallel.

In one embodiment, referring to fig. 3, each word line driver 22 includes a flag register circuit 221 and a voltage application circuit 222; an input terminal of the flag register circuit 221 is connected to a first output terminal of the logic controller 23, and an output terminal of the flag register circuit 221 is connected to a first input terminal of the voltage application circuit 222; a second input terminal of the voltage application circuit 222 is connected to a second output terminal of the logic controller 23, and an output terminal of the voltage application circuit 222 is connected to the sector. Specifically, the output terminal of the voltage application circuit 222 is connected to the word line of the sector.

The logic controller 23 outputs a verification result sev_pass to the flag register circuit 221 through the first output terminal to trigger the flag register circuit 221 to output a verification level signal matched with the verification result to the voltage application circuit 222. For example, the register output verify level signal "1" indicates that the verify result is verify failed, and the register output verify level signal "0" indicates that the verify result is verify passed.

The logic controller 23 also outputs the address signal of the target sector to the voltage applying circuit 222 through the second output terminal. The address signals include a Block address signal block_x_select and a sector address signal se_address of the memory Block.

The voltage applying circuit 222 outputs a voltage matched with the erase operation and/or a voltage matched with the verify operation to the target sector according to the verify level signal and the address signal.

In the embodiment of the present invention, under the control of the logic controller 23, the voltage applying circuit 222 applies a negative high voltage to the gate of the memory cell in the target sector, applies a positive high voltage to the bulk (or p-well) of the memory cell, and the high voltage generates a strong electric field on the oxide layer or ONO layer (one film layer of the memory cell) of the memory cell, so that electrons or negative charges of the memory cell obtain enough energy to pass through the oxide barrier, thereby realizing the erasing operation of the sector. After the erase operation, the voltage applying circuit 222 applies an erase verify voltage to the sector under the control of the logic controller 23, performing the erase verify operation. The control logic circuit reads the voltage of each memory cell in the target sector bit by bit; when the voltages of all the memory cells fall within the voltage range matching the expected erased state, indicating that the sector passes the erase verification, the logic controller 23 stores the verification result through the word line driver 22, for example, stores a flag "0" in the flag register circuit 221 connected to the sector passing the verification; as long as there are 1 memory cells whose voltages do not fall within the voltage range matching the expected erased state, indicating that the sector fails the erase verification, the logic controller 23 stores the verification result through the word line driver 22, for example, stores a flag "1" in the flag register circuit 221 connected to the sector that fails the verification as the target sector of the next erase operation. Judging whether the target sector which is not passed by the verification exists in the storage block 21, and if so, executing the erasing operation and the erasing verification operation again on the target sector which is not passed by the verification until all the sectors contained in the storage block 21 pass the erasing verification or stopping the erasing operation when the iteration stopping condition is satisfied. The iteration stop condition may include, but is not limited to, at least one of: the number of times of erasing the target sector reaches a threshold number of times, and the total erasing time reaches a block erase specified allowable time, i.e., a block erase specified allowable time. The total erase duration is the total duration of the three phases involved in the erase algorithm, and the block erase specification duration is typically set to 1.5 seconds.

In one embodiment, the voltage application circuit 222 includes a NAND gate and LEVEL SHIFTER (level shifter). A first input of the nand gate is connected to the output of the flag register circuit 221 as a first input of the voltage applying circuit 222, and is used to acquire a verification level signal representing a verification result. A second input terminal of the nand gate is connected to the second output terminal of the logic controller 23 as a second input terminal of the voltage applying circuit 222, and is used for acquiring an address signal. The output of the NAND gate is connected to the first input of the level shifter. The second input of the level shifter is connected to a charge pump which supplies the level shifter circuit with a voltage veng_erase for an ERASE operation and/or a voltage for ERASE verification. The third input of the level shifter is connected to a bias voltage Vunsel _bias. The output of the level shifter is connected to the word line of the sector. Vunsel _bias may be grounded or positive voltage or Floating.

It should be noted that the voltage veng_erase for the ERASE operation and the voltage for the ERASE verification may be supplied to the level shifter circuit by one charge pump; the voltage veng_erase for the ERASE operation and the voltage for the ERASE verification may also be supplied to the level shift circuit by 2 charge pumps, respectively.

In one embodiment, the level shifter is configured to output the bias voltage Vunsel _bias to the sector connected thereto when the first input terminal inputs a high level, the sector connected thereto is in a non-erased state, and the erase operation is not performed. The level shifter is configured to output an ERASE operation voltage veng_erase when the first input terminal inputs a low level, and the sector connected thereto is in an erased state, and then an ERASE operation is required to be performed. Taking fig. 3 as an example, the first input terminal of the level shifter connected to the Sector16 and the Sector1 inputs a high level, and the Sector16 and the Sector1 are in a non-erased state. In fig. 3, a first input terminal of a level shifter connected to the Sector10 inputs a low level, and the Sector10 is in an erased state.

Whether the voltage of the erase operation or the voltage of the erase verify operation is applied, the sector selection is involved, and the logic controller 23 in this embodiment realizes the selection of the sector by outputting the address signal to the voltage applying circuit 222. The address signals include a Block address signal block_x_select and a sector address signal se_address of the memory Block 21. In one embodiment, when block_x_select and SE_address of 1 sector are both 1, this indicates that the sector is selected; when at least 1 of block_x_select and se_address is 0, this indicates that the sector is not selected.

Whether the voltage applying circuit 222 applies the erase voltage and the erase verify voltage to the sector is determined by combining the verify level signal and the address signal. The process of the ERASE operation will be further described with reference to fig. 3, which is an example of the output bias voltage Vunsel _bias when the level shifter is configured to input the high level at the first input terminal and the ERASE operation voltage veng_erase when the level shifter is configured to input the low level at the first input terminal.

If the memory Block8 shown in fig. 3 is a memory Block selected for erasure, the memory Block contains 16 sectors, after 1 or more erasure verification operations, the verification results of the Sector1, the Sector3 and the Sector16 are verification passing, and the three sectors are other sectors, and then the three sectors do not need to be subjected to erasure operation and erasure verification operation. The logic controller 23 outputs address signals se_address 1=1 and block_8_select=1 to the nand gate of the word line driver 22 connected to the Sector1, the flag register circuit 221 of the word line driver 22 outputs a verify level signal 1 (high level) to the nand gate, the nand gate outputs a high level to a level shifter, the level shifter outputs a bias voltage Vunsel _bias to the Sector1, and the Sector1 is in a non-erased state. The logic controller 23 outputs address signals se_address 3=1 and block_8_select=1 to the nand gate of the word line driver 22 connected to the Sector3, the flag register circuit 221 of the word line driver 22 outputs a verify level signal 1 (high level) to the nand gate, the nand gate outputs a high level to a level shifter, the level shifter outputs a bias voltage Vunsel _bias to the Sector3, and the Sector3 is in a non-erased state. The erase control logic for Sector16 is similar and will not be described in detail herein.

In fig. 3, the Sector4 to Sector15 and Sector2 are target sectors, the logic controller 23 outputs address signals se_address 2=1 and block_8_select=1 to nand gates of the word line driver 22 connected to the Sector2, the flag register circuit 221 of the word line driver 22 outputs a verify level signal 0 (high level) to the nand gates, the nand gates output low level to level shifters, and the level shifters output erase voltages VENG ERASE to the Sector2, and the Sector2 is erased. The erase control logic for Sector4 through Sector15 is similar and will not be described in detail herein.

In one embodiment, for the verification result SEV PASS output by the logic controller, a high level is used to characterize the verification as failed and a low level is used to characterize the verification as passed. The flag register circuit includes a flag register and an NOT gate; the input end of the mark register is used as the input end of the mark register circuit, the output end of the mark register is connected with the input end of the NAND gate, and the output end of the NAND gate is used as the output end of the mark register circuit. When the logic controller outputs a high level (indicating that verification is not passed) to the flag register circuit, the flag register of the flag register circuit outputs the high level to the nand gate to output a low level to the level shifter by the nand gate in combination with the address signal, and the level shifter outputs the ERASE operation voltage veng_erase to the target sector connected thereto.

In one embodiment, for the verification result SEV PASS output by the logic controller, a low level is used to characterize the verification as failed and a high level is used to characterize the verification as passed. The flag register circuit includes a flag register; the input end of the mark register is used as the input end of the mark register circuit, and the output end of the mark register is used as the output end of the mark register circuit. When the logic controller outputs a low level (representing that verification is not passed) to the flag register, the flag register outputs the low level to the nand gate to output a low level to the level shifter by the nand gate in combination with the address signal, and the level shifter outputs the ERASE operation voltage veng_erase to the target sector connected thereto.

In one embodiment, the flag register may be a power down lost register, or may be a power down no lost register, or may be a static random access memory SRAM or a latch.

In one embodiment, the memory further comprises a charge pump connected to the third input of the voltage application circuit, the charge pump being for powering the voltage application circuit. For each erase operation, the logic controller 23 simultaneously triggers all the word line drivers 22 connected to the target sector to perform the erase operation on the respective target sectors to shorten the overall erase time of the memory block 21. That is, the logic controller 23 simultaneously triggers all the voltage applying circuits connected to the target sector to output voltages to the target sector.

It will be appreciated that as the number of erasures increases, more additional erase voltages are required for the sector to perform an erase operation, and that electrons or negative charges of the memory cell can gain sufficient energy to pass through the oxide barrier. In this embodiment, for one erase operation of the memory block 21, the voltage of the charge pump is intensively applied to the target sector, and is not required to be applied to other sectors, so that electrons or negative charges of the memory cells in the target sector can obtain enough energy to pass through the oxide barrier, and the efficiency of the erase operation is improved.

In one embodiment, for each erase operation, the logic controller 23 is further configured to determine a sector erase count that matches the power capability of the charge pump, and trigger a voltage application circuit equal to the sector erase count to output an erase voltage to the target sector.

Considering that the power supply capability of the charge pump is limited, for each erase operation, the voltage applying circuit in the embodiment, which triggers the number of voltage applying circuits matched with the power supply capability of the charge pump, outputs the erase voltage to the target sector, thereby improving the efficiency of each erase operation and further improving the overall efficiency of erasing the memory block 21.

Referring to table 1 below, the data in the table are time-consuming conditions of each stage obtained by erasing the memory according to the embodiment of the present invention and the memory according to the prior art, and the performance of both memories is the same, and each memory includes a sector subjected to 100 times of complete erasing and a sector subjected to 1 time of complete erasing. As can be seen from Table 1, the total erase duration of the memory provided by the embodiment of the present invention is only 230.18 milliseconds, which is greatly reduced compared with the total erase duration of the memory of the prior art, and the total erase duration of the memory provided by the embodiment of the present invention is less than the block erase specification duration (generally 1.5 seconds), while the total erase duration of the memory of the prior art is 1.92 seconds, which exceeds the block erase specification duration, and the block erase time specification requirement cannot be satisfied.

TABLE 1

In one embodiment, the logic controller 23 further determines whether the number of times of erasing the target sector reaches the number threshold, and when the number of times of erasing the target sector reaches the number threshold, the logic controller 23 does not trigger the word line driver to perform the erasing operation and the erasing verification operation on the target sector even if the verification result of the target sector is that the verification is failed.

When the number of times of erasing a certain sector reaches the number threshold, the result of erasing verification is not passed, which indicates that the sector is likely to have faults, and the erasing operation is not needed to be executed again. By judging the erasing times of the sector, the invalid erasing operation of the sector can be avoided, and the energy consumption is saved.

The present invention also provides embodiments of a block erase method for a non-volatile memory, corresponding to the foregoing memory embodiments.

Fig. 4 is a flowchart of a block erase method of a nonvolatile memory according to an exemplary embodiment of the present invention, where the block erase method is applied to the nonvolatile memory according to any one of the above embodiments, and the block erase method includes the following steps:

Step 401, in the erasing stage of executing the block erasing command, triggering a word line driver connected with the target sector to execute erasing operation and erasing verification operation on the corresponding target sector;

Step 402, storing a verification result of the erase verification operation through the word line driver;

In one embodiment, referring to FIG. 5, the step of triggering a word line driver connected to a target sector to perform an erase verify operation on the target sector includes:

Step 501, triggering a word line driver connected to a target sector to apply a voltage to the target sector that matches an erase verify operation.

Step 502, for each target sector, reading the voltage on the bit line included in the target sector bit by bit.

Step 503, in the process of reading bit by bit, it is determined whether the voltage on the bit line falls within a voltage range matching the expected erase state.

In step 503, when the determination result is no, step 504 is performed.

In step 503, when the determination result is yes, step 505 is executed.

Step 504, determining that the verification result of the target sector including the target bit line is that the verification is failed, and continuing to execute the erasing operation on the target sector. After completion, the process returns to step 501.

Step 505, determine whether the currently verified bit line is the last bit of the target sector.

In step 505, when the determination result is no, the process returns to step 502 to read the voltage on the next bit line and verify whether the voltage falls within the voltage range matching the expected erase state.

In step 505, when the determination result is yes, step 506 is performed.

Step 506, the verification result of the target sector is stored as verification passing.

In one embodiment, step 507 is performed after step 506.

Step 507, determining whether the last target sector of the memory block is the last target sector.

In step 507, when the determination result is yes, step 508 is performed.

In step 507, when the determination result is no, returning to step 502, reading and verifying, bit by bit, whether the voltage on the bit line included in the next target sector falls within the voltage range matching the expected erased state.

Step 508, go to the next recovery from over-erase phase and/or clear all word line driver stored verify results contained in the memory block.

Optionally, the memory further comprises a charge pump for powering the word line driver; the erasing method further includes:

Determining, for each erase operation, a sector erase number that matches a power capability of the charge pump;

triggering word line drivers equal to the number of sector erasures to output the voltage to the target sector.

For method embodiments, as they substantially correspond to non-volatile memory embodiments, the relevant parts are referred to in the description of the non-volatile memory embodiments, and in particular to the relevant parts of the logic controller.

While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the principles and spirit of the invention, but such changes and modifications fall within the scope of the invention.

Claims

1. A nonvolatile memory, comprising: a plurality of memory blocks, each memory block comprising a plurality of sectors;

each sector corresponds to a plurality of word line drivers, each word line driver being connected to a corresponding sector;

a logic controller connected to the word line driver; the logic controller is used for triggering a word line driver connected with a target sector to execute an erase operation and an erase verification operation on the target sector in an erase stage of executing a block erase command, and storing a verification result of the erase verification operation through the word line driver; the target sector is a sector which is selected to be erased and the verification result is a sector which is failed to be verified; other sectors contained in the storage block are in a non-erased state; the other sectors are sectors other than the target sector among all the sectors included in the memory block.

2. The non-volatile memory of claim 1, wherein for each erase operation, the logic controller simultaneously triggers a word line driver connected to each target sector to perform an erase operation on the target sector;

3. The nonvolatile memory according to claim 1 or 2, wherein the word line driver includes a flag register circuit and a voltage applying circuit;

4. The non-volatile memory of claim 3, wherein the flag register circuit comprises a flag register and a not gate;

5. The non-volatile memory of claim 4, wherein the flag register comprises a static random access memory or a latch or a power down non-lost register.

6. A block erase method of a nonvolatile memory, wherein the nonvolatile memory comprises a plurality of memory blocks, each memory block comprises a plurality of sectors, each sector corresponds to a plurality of word line drivers, and each word line driver is connected with a corresponding sector; the block erase method includes:

7. The method of block erase of a non-volatile memory of claim 6, wherein triggering a word line driver connected to a target sector to perform an erase operation on the target sector comprises:

8. The method of claim 6, wherein the triggering the word line driver connected to the target sector to perform an erase operation and an erase verify operation on the target sector comprises:

9. The block erase method of a nonvolatile memory according to any one of claims 6 to 8, wherein triggering a word line driver connected to a target sector to perform an erase verify operation on the target sector includes:

10. The block erase method of a nonvolatile memory according to claim 9, further comprising, after the step of storing a verification result of the erase verification operation by the word line driver: