KR20000007308A - Synchronizing type modulo n counter using d flip-flop - Google Patents

Abstract

PURPOSE: A synchronizing typed modulo N counter circuit is provided to have the whole simple hardware constitution, and to reduce the constitution size of the hardware, and to reduce the power consumption. CONSTITUTION: The synchronizing typed modulo N counter comprises: a device(10) to output by counting up an input signal; at least two D flip-flops(20,30) to output the signal inputted from the count-up device. The output of the D flip-flops is the feedback by the count-up device. The count-up device counts to 0 when the signal inputted form the D flip-flops is a binary number(N-1). The whole hardware constitution is made simple by organizing the D flip-flop for a JK flip flop on the synchronizing typed modulo N counter circuit.

Description

SYNCHRONOUS MODULO N COUNTING CIRCUIT USING D FLIP-FLOP WITH DEFLOPFLOP

The present invention relates to a synchronous module N counter circuit using a D flip-flop.

A modulo N counter or frequency divider is a binary counter that provides an output pulse for every N input pulses.

A conventional modulo N counter circuit is constructed using a JK flip-flop. However, since the JK flip-flop is composed of a plurality of gates, a module including the JK flip-flop has a disadvantage of increasing the size of the N counter circuit.

Accordingly, it is an object of the present invention to provide a modular N counter circuit with a simpler hardware configuration.

1 is a circuit diagram showing a synchronous modular three counter circuit according to a preferred embodiment of the present invention; And

FIG. 2 is a timing diagram of the synchronous modulo 3 counter circuit shown in FIG. 1.

* Description of the symbols for the main parts of the drawings *

10: count up circuit 12, 14: end gate

20, 30: the flip-flop

According to a feature of the present invention for achieving the object of the present invention as described above, the synchronous modulo N counter circuit comprises: means for counting up and outputting an input signal; At least two latch means for outputting a signal input from the count up means in synchronization with a clock signal, the output of the latch means being fed back to the count up means, the count up means being If the signal input from the latch means is a binary number (N-1), it counts as zero.

In a preferred embodiment, the synchronous modulo N counter circuit initiates operation by a predetermined reset signal.

In a preferred embodiment, the latch means consists of a D flip-flop.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The novel synchronous modulo N counter of the present invention comprises a means for counting up and outputting an input signal and at least two D flip-flops for outputting a signal input from the countup means in synchronization with a clock signal. do. The output of the D flip-flops is fed back to the count up means, and the count up means counts to zero if the signal input from the D flip-flops is binary (N-1). The synchronous module simplifies the overall hardware configuration by configuring D flip-flops instead of JK flip-flops in the N counter circuit. As a result, the construction area of hardware is reduced, and power consumption is reduced.

A synchronous modulo 3 counter starts counting from zero and counts within a range less than the remainder divided by three. That is, the counter repeats incrementing by 1 from 0 to 2.

[Table 1] shows the output of the synchronous modulo 3 counter.

TABLE 1

B A 0 0 0 One One 0 0 0

As shown in the table above, the output of the synchronous modulo 3 counter changes to binary 00, 01, 10, 00. That is, the output value changes in the order of decimal 0, 1, 2, 0.

In Table 1, when A and B are current states and A 'and B' are next states, the input and output relations are summarized in Table 2 as follows.

TABLE 2

Current Status Next status B A B ' A ' 0 0 0 One 0 One One 0 One 0 0 0 0 0 0 One

[Table 2] means that the next state A 'and B' are output to the D flip-flops 20 and 30 when A and B of the current state are input to the count-up circuit 10.

With reference to the above [Table 2], the relational expression of the next state A 'and B' based on the current state A and B is as follows.

When a logic circuit is formed according to the above relation and the next states A 'and B' are input to D flip-flops, respectively, the output of the counter is output at each D flip-flop at the rising edge of the clock signal. A more detailed description will be described with reference to FIGS. 1 and 2.

1 is a circuit diagram showing a synchronous modular three-counter circuit according to a preferred embodiment of the present invention.

Referring to FIG. 1, the synchronous modulo 3 counter circuit includes a count up circuit 10 and two D flip-flops 20 and 30.

The count up circuit 10 is a logic circuit according to the above relation, and is composed of two inverters 12 and 14 and two AND gates 16 and 18. In the count up circuit 10, A 'and B' are output according to the input of A and B. As shown in FIG. The output of each of the two AND gates 16, 18 configured in the count up circuit 10 is input to the D flip-flops 20, 30.

FIG. 2 is a timing diagram of the synchronous modulo 3 counter circuit shown in FIG. 1.

1 and 2, the D flip-flops 20 and 30 output a low L when the reset signal e is high. As the reset signal e becomes L, a count operation in which the D flip-flops 20 and 30 output the input signals a and b to the output terminal is started. Since the output of each of the AND gates 16 and 18 is H and L when the outputs of the D flip-flops 20 and 30 are all L, the signals output from the D flip-flops 20 and 30 ( b and d) become H and L. The D flip-flops 20 and 30 output the H and L signals b and d at the rising edge of the clock signal. The output signals b and d of the D flip-flops 20 and 30 are fed back to the count up circuit 10. The count up circuit 10 inputs the signals b and d fed back from the D flip-flops 20 and 30 to output L and H counted up. The counted up output signals a and c are input to the D flip-flops 20 and 30, respectively. The output signals b and d of the D flip-flops 20 and 30 are fed back to the count up circuit 10. The count up circuit 10 counts and outputs L and L since the signals b and d fed back from the D flip-flops 20 and 30 are L and H, respectively. The output signals a and c of L and L are input to D flip-flops 20 and 30, respectively.

As described above, the outputs of the D flip-flops 20 and 30 are output to L L, H L, L H, L and L at the rising edges of the clock signal, respectively. Signals A and B output from the D flip-flops 20 and 30 become synchronous modulo three counter output signals, one third of the clock signal frequency, respectively.

The same clock signal is inputted to all flip-flops of the synchronous modulo 3 counter circuit, so there is no ambiguous state due to cumulative propagation delay, and it operates at a high frequency clock.

When the configuration of the count-up circuit 10 is changed by using the above-described method, it is applicable to not only the synchronous modulo 3 counter but also the synchronous modulo N counter. As the value of N increases, the number of states increases, so the Kanaugh map can be used to reduce the redundancy of the input type logic and connect this result to the input of the D flip-flop.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

According to the present invention as described above, the overall hardware configuration can be simplified by configuring the D flip-flop instead of the JK flip-flop in the N counter circuit with the synchronous module. As a result, the construction area of hardware is reduced, and power consumption is reduced.

Claims (3)

In the synchronous modular N counter circuit, Means for counting up and outputting an input signal; At least two latch means for outputting a signal input from said count up means in synchronization with a clock signal, The output of the latch means is fed back to the count up means, And said count up means counts as zero when the signals input from said latch means are binary (N-1). The method of claim 1, And the synchronous modulo N counter circuit starts operation by a predetermined reset signal. The method of claim 1, And the latch means is a D flip-flop.