KR20000004592A - Analog-to-digital converting apparatus utilizing comparison window of variable size - Google Patents

Abstract

PURPOSE: An analog-to-digital converting apparatus is provided to compare data within a comparison window of variable size having high and low limits, so that the comparison time is reduced. CONSTITUTION: The apparatus comprises an analog-to-digital converting means(300) and a reference voltage generating means(305). The analog-to-digital converting means(300) compares an external analog signal with an internal reference voltage to convert the external analog signal into a digital signal. A digital signal from the analog-to-digital converting means(300) and a digital signal whose size is that of a comparison window are inputted to the reference voltage generating means(305). The reference voltage generating means(305) determines upper and lower limits of the reference voltage according to the input digital signals.

Description

Analog-to-Digital Converter Using Variable Size Comparison Window

The present invention relates to an analog-to-digital converter using a variable size comparison window.

First, the analog-to-digital conversion principle is briefly described. The analog-to-digital converter converts an analog signal into a digital signal by comparing it with an internally divided reference voltage.

Conventional analog-to-digital converters can be roughly divided into a SAR (Succesive Approximation Register) (hereinafter referred to as "SAR") method and a flash method.

1 is a block diagram of a conventional SAR-type analog-to-digital converter, which includes a sampling and holding unit 101, a comparator 102, a control unit 103, a register 104, and a digital-to-analog converter 105. do.

As shown in the figure, the SAR scheme compares the reference voltage several times until a desired digital output is obtained using one comparator 102 for the input. Therefore, while the hardware is simple, the n-bit analog-to-digital converter (ADC) 105 has a problem that the response time is slow by performing the comparison up to n times.

2 is a block diagram of a conventional flash-type analog-to-digital converter, which includes a sampling and holding unit 201, a comparator 202, a control unit 203, a register 204, and a digital-to-analog converter 205. do.

As shown in the figure, the flash method is used in a device requiring a quick response by using a plurality of comparators 202 to obtain a desired digital value at a time, but 2 ^{n for an} n-bit analog-to-digital converter. One comparator was required, which caused a burden on the hardware.

Accordingly, the present invention devised to solve the above-described problems, by using the continuity with respect to the time axis to generate a variable size window having an upper and lower limit and compare only within the border of the variable size of the variable size An object of the present invention is to provide an analog-to-digital converter using a comparison window.

1 is a block diagram of a conventional SAR-type analog-to-digital converter.

2 is a block diagram of a conventional flash-type analog-to-digital converter.

Figure 3 is an embodiment configuration of an analog-to-digital conversion device using a variable size comparison window according to the present invention.

4 is an explanatory diagram showing a comparison window for an analog input having continuity.

* Explanation of symbols for main parts of the drawings

300: analog / digital converter 301: first register

302: regulating device 303: second register

304: third resistor 305: reference voltage control unit

306: Digital to Analog Converter

An apparatus of the present invention for achieving the above object, in the analog / digital conversion device, analog / digital conversion means for comparing the analog signal from the external and the internal reference voltage, converting the analog signal to a digital signal and output ; And reference voltage generation means for receiving the digital signal from the analog-to-digital conversion means and the digital signal of the comparison window size from the outside to determine the upper limit value and the lower limit value of the reference voltage to be compared to generate the internal reference voltage.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of an embodiment of an analog-to-digital converter using a variable size comparison window according to the present invention.

As shown in the figure, the analog-to-digital converter includes a first register 301 for storing the size of the comparison window, an accelerometer 302 for calculating the upper and lower limits, and a second register 303 for storing the upper limit. A third register 304 for storing a lower limit value, a reference voltage controller 305 for generating a reference voltage, a digital to analog converter 306 for converting a digital signal into an analog signal, and sampling and maintaining an analog input signal A sampling and holding unit 307, a comparator 308 for comparing two analog signals, and a fourth register 309 for storing n-bit digital values converted into digital signals. In addition, the analog-to-digital converter 300 includes a digital-to-analog converter 306, a sampling and holding unit 307, a comparator 308, and a fourth register 309.

First, the first register 301 receives and stores an m-bit digital input signal for determining the size of the comparison window from the outside.

The adder / lower 302 receives an m-bit digital input signal from the first register 301, receives an n-bit digital input signal from the fourth register 309, and adds and subtracts the upper and lower limit values.

The second register 303 receives the upper limit value from the accelerometer 302 and stores and outputs the upper limit value.

The third register 304 receives the lower limit value from the retarder 302, stores it, and outputs it.

The reference voltage controller 305 receives a reset signal from an external source, outputs a comparison start signal to the digital-to-analog converter 306, and receives an upper limit value and a lower limit value from the second register 303 and the third register 304. The upper limit value and the lower limit value of the reference voltages to be compared are determined, and a reference voltage is generated and output as a digital signal.

The digital / analog converter 306 receives the comparison start signal and the digital signal from the reference voltage controller 305, converts the analog signal into an analog signal, and outputs the analog signal.

The sampling and holding unit 307 receives an analog signal from an external source, holds the sampled analog signal, and holds the sampled analog signal.

The comparator 308 receives and compares the sampled analog signal of the sampling and holding unit 307 with a reference voltage from the digital / analog converter 306 and outputs an n-bit digital value.

The fourth register 309 stores and outputs the n bit digital value from the comparator 308.

Meanwhile, in the conventional SAR method for analog-to-digital conversion with n-bit resolution, the size of the comparison window is the same as that of VDD, and the digital value to be converted is n bits.

However, according to the present invention as described above, when the size of the comparison window is determined as VDD / m at the resolution of n bits, the digitally converted digital value is reduced to n / (n-log ₂ m) bits, so that analog-to-digital conversion can be performed. In this case, it can be seen that the speed is n / (n-log ₂ m) times faster than the conventional SAR analog-to-digital converter. In this case, the lower log ₂ m bits are all in the same position as the input analog signal of the previous stage, so they have the stored value again through the comparator.

4 is an explanatory diagram showing a comparison window for an analog input having continuity.

As shown in the figure, an analog / digital conversion is performed using a comparison window for an analog input having continuity. One period represents the time taken for the input analog signal to be sampled once and the analog-to-digital conversion is performed, indicating that the input sampling time should be sufficiently oversampled relative to the frequency of the input signal.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains, and the above-described embodiments and accompanying It is not limited to the drawing.

Therefore, the present invention as described above can reduce the comparison time, increase the response speed, and significantly reduce the hardware in comparison with the flash method by generating a variable sized window having an upper and lower value and comparing only within its border. It can be effective.

Claims (4)

In the analog / digital converter, Analog / digital conversion means for comparing an analog signal from an external reference with an internal reference voltage and converting the analog signal into a digital signal and outputting the digital signal; And Reference voltage generation means for generating the internal reference voltage by determining an upper limit value and a lower limit value of a reference voltage to be compared by receiving a digital signal from the analog / digital conversion means and a digital signal having a comparison window size from the outside; Analog / digital conversion device using a variable size comparison window made of a. The method of claim 1, The reference voltage generating means, First storage means for receiving, storing, and outputting a digital input signal having a comparison window size from the outside; Calculation means for receiving the digital input signal from the first storage means and the digital signal from the analog / digital converting means and adding and subtracting the digital input signal to output an upper limit value and a lower limit value; Second storage means for storing and outputting an upper limit value and a lower limit value from said computing means; And Outputs a comparison start signal by receiving a reset signal from an external source, and receives an upper limit value and a lower limit value from the second storage means, determines an upper limit value and a lower limit value of a reference voltage to be compared, and generates the internal reference voltage to output a digital signal. Reference voltage control means Analog / digital conversion device using a variable size comparison window made of a. The method according to claim 1 or 2, The analog / digital conversion means, Sampling and holding means for sampling an analog signal from the outside and holding and outputting the sampled analog signal; Digital / analog conversion means for receiving a comparison start signal and a digital signal from the reference voltage control means and converting the analog signal into an analog signal and outputting the analog signal; Comparison means for comparing the internal reference voltage from the digital / analog conversion means with the sampled analog signal from the sampling and holding means and outputting a digital signal; And Fourth storage means for storing the digital signal from said comparing means and outputting it to said calculating means Analog / digital conversion device using a variable size comparison window made of a. The method of claim 3, wherein The comparison window size is, Analog-to-digital converter using a variable size comparison window, characterized by user-programmable.