WO2009070001A2

WO2009070001A2 - A successive approximationregistrer (sar)analog-to-digital converter (adc) with programmable voltage reference

Info

Publication number: WO2009070001A2
Application number: PCT/MY2009/000012
Authority: WO
Inventors: Leong Son Wee; Yuzman Yusoff; Rozaimah Baharim
Original assignee: Mimos Berhad
Priority date: 2007-11-30
Filing date: 2009-01-13
Publication date: 2009-06-04
Also published as: WO2009070001A3

Abstract

For a SAR ADC with having an integrated programmable voltage reference function, a process for the voltage programmable positive voltage reference integrated to SAR ADC, includes; a) integrating a bandgap (21) to provides a stable voltage b) scaling up to a higher voltage by first Opamp (22) from the bandgap (21) and the voltage divided by the first resistor string (24) and second resistor string (25) to provides taps for the different voltage levels c) buffering the voltage at second Opamp (23) d) transferring the voltage to the decoding network (28) e) decoding the voltage by the decoder having at least one signal (29) and connecting the voltage to at least one resistor string (27) and at least one resistor string (27) tap point to the input third Opamp (30) f) buffering the voltage at the third Opamp (30) and the output becoming voltage reference programmable g) used as voltage reference at the digital-to-analog DAC (12) and the output of the converted voltage becoming voltage digital-to-analog (Vdac) h) sending the Vdac to the comparator (13) and the output of the comparator sending to the SAR (11) i) modifying the Vdac contents bit by bit until the data are the digital equivalent of the analog input j) repeating steps (a) through (i) until a predetermined number of trials have been completed.

Description

A. successive Approximation register (SAR) analog-to-digital converter (ADC) with programmable voltage reference.

Technical Field

This invention relates to a successive approximation register (SAR) analog-to- digital converter (ADC) integrated with programmable voltage reference.

Background of the invention

Successive approximation ADC is the name commonly given to an digital-to-

■ i s _f -N ^f , M J ₁ I U l . t ier ( i )( ; analog conversion process in which digital approximations of the input analogue voltage are determined on the basis of a binary search. A digital value stored in an n-bit successive approximation register (SAR) is input to a digital-to-analog converter, and a decision is made as to whether the value in the SAR represents an analog voltage that is higher or lower that the input analogue value.

The invention of US6, 351, 231 Bl relates to an i improved successive approximation analogue-to-digital converter system including a D/A converter and a comparison capability, wherein a first trial value is stored in a successive approximation register and a comparison is made of relative amplitude D/A converter output with respect to analogue signal amplitude, and an iterative process is performed in which a subsequent trial value is stored in the successive' approximation register before¹ the comparison is repeated. The improvement comprises conducting only one comparison for each trial, with the subsequent trial value for a plurality of iterations being greater than one-half the first trial value, such that at a first trial value determined in error is corrected during iterations. Apparatus implementing the improved successive approximation A/D is also described. However, the invention of US6, 351, 231 Bl , don't have positive voltage reference integrate and programmable. Accordingly, there is a need to provide a programmable voltage reference to provide option for analog-to-digital converter (ADC) an adjustable positive reference voltage to give more accurate voltage step.

Summary

It is, therefore, an object of the present invention to provide a successive approximation register (SAR) analog-to-digital (ADC) with having an integrated programmable voltage reference comprising: a bandgap; first operational amplifier (Opamp); resistor strings wherein the resistor strings having first resistor string and second resistor string situated at the [negative; yoltage_; (Vr)₁ of- first .Opamp ι._s; _r. second operational amplifier! (Opamp); a. decoder .having; at

(Yg); third operational amplifier , (Opamp); a successive approximation register (SAR) analog-to-digital converter (ADC) block; whereby the second Opamp and the third Opamp works as a buffer and the decoder having at least one signal is formed by an array of transfer gate to form a decoding network wherein the decoding network is connected in a form of tree.

It is another object of the present invention to provide, a SAR ADC with haying! an integrated programmable voltage, reference function, , a process , for,, , the voltage programmable positive voltage reference integrated to SAR ADQ includes,- _<a) integrating the. bandgap to provides a stable voltage b) scaling up to a.higher voltage by first Opamp from the bandgap and the voltage _:divided by jthe first resistor _s string .and (Second resistor string to provides taps for the different voltage levels, c)_. buffering the. voltage: at second .Opamp d) ^transferring the voltage to the. decoding network.e) .decoding, the ypltage_:by the decoder having at least one, signal and connecting . the ,voltage.;tO; at.least^one;Tesistpr string and at least one resistor string tap point tp the input. third; Opamp. Λf) buffering the voltage at the third Opamp and the output becoming voltage reference programmable g) used as voltage reference at the digital-to-analog DAC and the output of the converted voltage becoming voltage digital-to-arialog (Vdac) h) sending the Vdac to the comparator and the output of the comparator sending to the SAR i) modifying the Vdac contents bit by bit until the data are the digital equivalent of the analog input j) repeating steps (a) through (i) until a predetermined number of trials have been completed.

Brief Description of the invention

The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:

Fig. 1 illustrates successive approximation register (SAR) analog-to-digital (ADC) integrated with programmable voltage reference circuit.

Fig. 2 illustrates Hpsice simulation with Vrp=3.3v

Fig. 3 illustrates Hpsice simulation with Vrp=2.96v

Detailed description of the invention

The embodiment described herein a successive approximation register (SAR) ADC with programmable voltage reference. The programmable voltage, reference provides option for analog-to-digital converter (ADC) and adjustable positive reference voltage to give a more accurate voltage steps.

Fig. 1 illustrates successive approximation register (SAR) analog-to-digital (ADC) integrated with programmable voltage reference circuit. A successive approximation register (SAR) analog-to-digital (ADC) with having an integrated programmable voltage reference comprising of a bandgap (21) where the bandgap (21) is used to integrated the design and provides a stable voltage. The bandgap (21) usually provides reference voltage for the analog-to-digital converter (ADC) (12) and has stable characteristic against a temperature or a process change. A first operational amplifier

(Opamp) (22) is configured as a non linera amplifier. The output voltage of the first

Opamp (22) allowed it to be varied by changing the first and second resistor string

(24,25) values. The first resistor string (24) and the second resistor string (25) is situated at the negative voltage (V-) of first Opamp (22). The first Opamp (22) voltage out (Vout) is given as

Vout= (1 + (second resistor string (25)/ first resistor string (25))) x Voltage in (Vin) [ Vout is output of first Opamp (22) voltage. Vin is input of first Opamp (22)]

Second operational amplifier (Opamp) (23) and the third operational amplifier (Opamp) (30) are act as a buffer. A buffer is an amplifier that isolates one circuit from another. It decreases the loading effect on an oscillator by reducing the interaction between the load and the oscillator. A decoder having at least one signal (29) is formed by an array of transfer gate (28) to form a decoding network (28) where the decoding network (28) is connected in a form of tree.

The process of SAR ADC integrated with the programmable voltage¹* reference function by integrating with the bandgap (21) to provides a stable voltage that scale-up to a higher voltage by the first Opamp (22). The scaled up voltage is divided by the first resistor string (24) and a the second resistor string (25) to provides taps for the different voltage levels. The voltage buffer at the second Opamp (23), where the second Opamp (23) act as a buffer between the source and the load to prevent loading effects. The voltage transferred to the decoding network (28). The voltage decoded by the decoder- having at least one signal (29) d) transferring the voltage to the decoding network (28J and connecting the voltage to at least one resistor string (27) and at least one' resistor string (27) tap point to the input third Opamp (30). As an example, assume that the output from the second Opamp (23) is 3v. The voltage drop to the at least one resistor (27) are 3v, 2.625V, 2.25v, 1.875v, 1.5v, 1.125v, 0.75v and 0.375v. If the reading at the 'decoder having at least one signal (29) is =111, it would activate transmission gate (28) no7 8. This would enable the link of voltage drop at least one resistor (27) of no. 8, 3v to' the third Opamp (30). The third Opamp (30) buffer the voltage and the output becoming voltage reference programmable (Vrp). The voltage reference programmable converted at the DAC (12) and the output of the converted voltage becoming as voltage digital-to- analog (Vdac). The Vdac being send to the comparator (13) and the output of the comparator sending to the SAR (11). The SAR (11) modified the Vdac contents bit by bit until the data are the digital equivalent of the analog input.

The illustration in Fig. 2 and Fig. 3 shows the Hpsice simulation with the Vrp=3.3v and the Vrp=2.96v. The result shows that the voltage of a SAR ADC when integrated with a voltage programmable reference are really stable and accurate.

While the present invention has been described with respect to certain preferred embodiments, it will be apparent to those skills in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.

Claims

What I claim is:

1. A successive approximation register (SAR) analog-to-digital (ADC) with having an integrated programmable voltage reference comprising: a bandgap (21); first operational amplifier (Opamp) (22); resistor strings wherein the resistor strings having first resistor string (24) and second resistor string (25) situated at the negative voltage (V-) of first Opamp (22); second operational amplifier (Opamp) (23); a decoder having at least one signal (29); ground voltage (Vg) (26); third operational amplifier (Opamp) (30); a successive approximation register (SAR) analog-to-digital converter (ADC) block (10); whereby the second Opamp (23) and the third Opamp (30) works as a buffer arid¹ the' ^l decoder having at least one signal (29) is formed by an array of transfer gate (28) to form a decoding network (28) wherein the decoding network (28) is connected in a form of tree.

2. A successive approximation register (SAR) analog-to-digital (ADC)'as claimed in claim 1 wherein first Opamp (22) is configured as a non-inverting amplifier.

3. A successive approximation register (SAR) analog-to-digital (ADC) as claimed in claim 1 wherein at each of the array of the transfer gate consist of at least one resistor string (27).

4. A successive approximation register (SAR) analog-to-digital (ADC) as claimed in claim 1 wherein the Vg (26) situated at the end of the second resistor string (25) arid at the end of at least one resistor string (27).

5. A successive approximation register (SAR) analog-to-digital (ADC) as claimed in claim 1 wherein the SAR ADC block (10) consist of; a successive approximation register (11); a digital-to-analog converter (12) and; a comparator (13).

6. For a SAR ADC with having an integrated programmable voltage reference function, a process for the voltage programmable positive voltage reference integrated to SAR ADC, includes; a) integrating the bandgap (21) to provides a stable voltage b) scaling up to a higher voltage by first Opamp (22) from the bandgap (21) and the voltage divided by the first resistor string (24) and second resistor string (25) to provides taps for the different voltage levels c) buffering the voltage at second Opamp (23) d) transferring the voltage to the decoding network (28) e) decoding the voltage by the decoder having at least one signal (29) and connecting the voltage to at least one resistor string (27) and at least one resistor string (27) tap point to the input third Opamp (30) f) buffering the voltage at the third Opamp (30) and the output becoming voltage reference programmable g) converting the voltage reference programmable at the DAC (12) and the output of the converted voltage becoming voltage digital-to-analog (Vdac) h) sending the Vdac to the comparator (13) and the output of the comparator sending to the SAR (11) i) modifying the Vdac contents bit by bit until the data are the digital equivalent of the analog input j) repeating steps (a) through (i) until a predetermined number of trials have been completed.

7. A successive approximation register (SAR) analog-to-digital (ADC) as claimed in claim 1 and claim 6 wherein the decoder having at least one signal (29) maybe in 3-8 bit or 4-16 bit.