CN103516363A

CN103516363A - Weight voltage type ADC and DAC based on dual weight resistance chain

Info

Publication number: CN103516363A
Application number: CN201210224713.7A
Authority: CN
Inventors: 陈启星
Original assignee: Individual
Current assignee: Individual
Priority date: 2012-06-15
Filing date: 2012-06-15
Publication date: 2014-01-15
Also published as: WO2013185265A1

Abstract

The invention provides a weight voltage type ADC and DAC based on a dual weight resistance chain. Currently, DACs are all based on the working principle of weight currents, wherein the mean value of working currents of the DACs increases geometrically along with the bits of digital signals and is hundreds of times of the minimum current of the DACs. According to the weight voltage type DAC based on the dual weight resistance chain, DA conversion is conducted in a weight voltage mode, so that the working current of the weight voltage type DAC is identically equal to the minimum current, the current mean value of the weight voltage type DAC is lowered by 2-3 orders of magnitude compared with a weight current DAC, and the number of devices is small. Compared with a current successive comparison type ADC of the same kind, the weight voltage type ADC based on the dual weight resistance chain has the advantages that the speed is increased by one order of magnitude; the number of conversion bits is large; the number of the devices is small; errors are small.

Description

Power voltage-type ADC and DAC based on antithesis power resistance chain

Technical field: the present invention be analog to digital converter and digital-to-analogue walk around device category (following, herein by analog to digital converter referred to as ADC, digital-to-analogue is walked around device referred to as DAC), belong to digital communication, digital device class, electronic product.

Background technology: ADC and DAC are applied to digital communication, radar, digital product etc., now have multiple ADC and DAC, but all exist a lot of not enough.

The manufacture of existing DAC has many methods, as: R-2R method, Method of constant flow source, power resistive method etc. ⁽¹⁾yet its basic principle is with regard to only one: digital signal is become to different power (2 ⁰, 2 ¹, 2 ², 2 ³...) I ₀electric current, and then superpose and pass through operational amplifier and convert analog voltage signal to.1., required electric current is very large this principle has two large shortcomings:, 18 DAC of take are example, if make minimum current, are I ₀, so maximum total current is I ₀* 2 ¹⁸=256*1024*I ₀, make equipment heating amount large, mobile communication facility stand-by time is shortened; 2., make to weigh electric current and reach that very high precision difficulty is very large, complex structure.

Main flow ADC operation principle has three major types: parallel model ADC (at a high speed), successive approximation ADC (middling speed), dual integration ADC (low speed), also have some variations of structure on this basis, as two-step, continuous-flow type, collapsible, interpolation type etc., all exist the contradiction between conversion speed and device amount, energy consumption.

The object of the invention is to solve the contradiction between device amount, energy consumption and the conversion speed of ADC and DAC.

Nominal definition: device amount---form ADC and DAC electronic device quantity.ADC and DAC are comprised of a lot of electronic devices, at present conventional " chip area size " come outlines device number, this is unreasonable because same circuit, with the technology of 100nm and the technology manufacture of 35nm, its chip area is different large, and device amount is identical; Sampling holder is called for short adopts guarantor's device, and sampling keeps hereinafter to be referred as adopting guarantor, adopts guarantor for one and is divided into sampling moment and maintenance phase the cycle;

Invention application content: the present invention is a kind of DAC and ADC based on antithesis power resistance chain, it is characterized in that: comprise the antithesis power resistance chain being connected into by antithesis resistance, be called for short antithesis chain; Proper noun and special symbol are defined as follows:

● figure place refers to number of bits, and N is antithesis chain type ADC or antithesis chain type DAC total bit, is sub level figure place sum;

● with α, β, γ ... statement sub level is other 1,2,3, Φ is their asterisk wildcard, and what (Φ+1) was Φ is secondary;

● switch resistance r ₀, additional resistance r ₁, dead resistance r---digital switch S _jduring conducting, there is a very little resistance to claim switch resistance r ₀; In order to eliminate the caused error of switch resistance, each power resistance has added an additional resistance r who equates with switch resistance ₁, switch resistance r ₀with additional resistance r ₁be collectively referred to as dead resistance r; Make three equate: r ₀=r ₁=r; V _rthe pressure drop that expression is produced by r; Major-minor resistance chain respectively has N r, and the total stray voltage symbol of main chain is V _nr, represent the pressure drop by N r generation, i.e. V _nr=V _n*r=N*V _r; Claim V _nrfor total stray voltage;

● all weights of weights j wildcard (0～N), digital signal D _jor digital switch S _jin weights j weigh exactly resistance 2 ^jr or only weigh resistance 2 ^jr ₀in weights j; That is, digital signal D _jcontrol corresponding digital switch S _jthereby control the power resistance 2 of corresponding weights ^jr;

with 2 ^jr ' in like manner;

● only weigh resistance---in resistance chain, reference resistance is R ₀, in order to make label R ₀observably be different from R, use instead

replace R ₀, in secondary resistance chain, reference resistance is

order

the clean power resistance that represents j position in main resistor chain, the 0th is the clean resistance of MINIMUM WEIGHT

be exactly reference resistance R ₀; In like manner,

the clean power resistance of j position in vice resistance chain; Clean power resistance can be a resistance, can be also 2 ^jthe series connection of individual reference resistance, to reduce error;

● power resistance---the transformed error causing in order to eliminate dead resistance r, order

and

that is, power resistance 2 ^jr or 2 ^jr ' has added dead resistance r, 2 on clean power resistance basis ^jr is called for short resistance with sovereign right, 2 ^jr ' is called for short secondary power resistance, is collectively referred to as power resistance; Each power resistance digital switch in parallel, has also comprised and has no longer separately added explanation by the digital switch that it is in parallel with regard to acquiescence while mentioning certain power resistance;

● access resistance, remove resistance and the resistance of trying---as digital switch S _jor

during for closure state, its resistance equals dead resistance r, by its power resistance 2 in parallel ^jr or 2 ^jr ' two terminal shortcircuits, make this power resistance in resistance chain, be equivalent to disappear, and are referred to as to remove, and this power resistance claims to remove resistance, because power resistance is much larger than r, so remove the resistance at resistance two ends, treats as in r; As digital switch S _jor

during for open-circuit condition, the power resistance 2 that it is in parallel ^jr or 2 ^jr ' resistance is just embodied in resistance chain, is referred to as access, and its power resistance claims the resistance that accesses resistance ，Qi two ends to equal power resistance 2 in parallel ^jr or 2 ^jr ' resistance; The special symbol of order access resistance with sovereign right is II ^jr, and make ∑ II ^jr is expressed as the access right resistance sum in main resistor chain; Equally, the special symbol of the secondary power of order access resistance is II ^jr ', and make ∑ II ^jr ' is expressed as the access right resistance sum in secondary resistance chain; For example, there is the digital signal D of 8 ₇d ₆d ₅d ₄d ₃d ₂d ₁d ₀=10011000, learn its D ₇, D ₄, D ₃position equals 1, is exactly by j=7,4, three resistance 2 with sovereign right of 3 ⁷r, 2 ⁴r, 2 ³r is set to access resistance, uses respectively II ⁷r, II ⁴r, II ³r describes, and obtains ∑ II ^jr=II ⁷r+ II ⁴r+ II ³r, other 5 resistance 2 with sovereign right ⁶r, 2 ⁵r, 2 ²r, 2 ¹r, 2 ⁰r is arranged to remove resistance; In ADC, certain resistance with sovereign right need to be attempted

Property access, according to comparative result, determine that again this resistance is need access or remove, this resistance is called the resistance of trying so; ● antithesis power resistance---main resistor chain 2 ⁰r～2 ^n-1r and secondary resistance chain 2 ⁰r '～2 ^n-1in R ', the major and minor electricity that weights j equates

Resistance is called antithesis power resistance, and resistance is equal, that is, and and 2 ^jr=2 ^jr ', 2 ^jr and 2 ^jr ' is antithesis power resistance;

● Dual switch---each power resistance digital switch by Digital Signals in parallel; 2 ^jr digital switch S in parallel _j, by digital signal D _jcontrol; 2 ^jr ' digital switch in parallel

by digital signal

control; S _jwith

for reciprocal Dual switch, Sj and

in always have a conducting and another cut-off, so antithesis resistance always one access one remove;

● digital signal D _jcontrol digital switch S at=1 o'clock _j=1, represent switch open circuit; Digital signal D _jcontrol S at=0 o'clock _j=0, represent switch short circuit;

with

in like manner; Adopt positive logic herein, i.e. high potential=1, electronegative potential=0;

● main apparent chain NR---power resistance 2 ⁰r, 2 ¹r ..., 2 ^n-1the series connection of R is called main apparent resistance chain NR, same, power resistance 2 ⁰r ', 2 ¹r ' ..., 2 ^n-1the series connection of R ' is called secondary apparent resistance chain NR ',

● main chain R _y---the total access resistance in main apparent chain, in main apparent chain NR, access resistance chain (the power resistance and the dead resistance that comprise access) and be called resistance chain with sovereign right, be called for short main chain R _y;

in formula, m removes resistance number in main resistor chain; Equally, the access resistance chain in secondary apparent resistance chain is called secondary power resistance chain, is called for short secondary chain R ' _y; in formula, m ' removes resistance number in secondary resistance chain;

● main chain is weighed resistance R only _y0only weigh resistance R with secondary chain ' _y0---main chain is got rid of the clean power resistance value R after dead resistance _y0be called for short main chain and only weigh resistance,

equally, secondary chain is weighed resistance only

● V _y---main chain total voltage,

● V _y0---main chain is weighed voltage only

● antithesis power resistance chain---main chain is called antithesis power resistance chain with connecting of secondary chain, hereinafter to be referred as antithesis chain; Power resistance 2 in main chain ^jr and power resistance 2 corresponding in secondary chain ^jr ' is antithesis resistance; Antithesis chain type ADC is called for short DOADC; Antithesis chain type DAC is called for short DODAC; Both merge and are called for short antithesis chain type transducer, are called for short DOC.

● antithesis chain all-in resistance R _z---due to the always access of one pair of antithesis resistance, another removes, so access resistance total value is 2 ⁰r+2 ¹r+ ... + 2 ^n-1r, removing resistance total value is N*r, so R _zfor definite value R _z=2 ⁰r+2 ¹r+ ... + 2 ^n-1r+N*r, antithesis chain electric current (being called for short chain electric current) I is definite value I=V _⊕/ R _z=V _⊕/ (2 ⁰r+2 ¹r+ ... + 2 ^n-1r+N*r);

● physical circuit is too numerous to enumerate, and the circuit implementation procedure in the present invention is just for example;

● subscript is the character of reindexing not, as CB adopts guarantor's device, CB _wremain and adopt guarantor's device, subscript w is footnote;

The total antithesis chain of apparent is in series by apparent main resistor chain NR and the secondary resistance chain NR ' of apparent, and apparent main resistor chain NR is by resistance 2 with sovereign right ⁰r～2 ^n-1r is in series, and the secondary resistance chain NR ' of apparent is by pair power resistance 2 ⁰r '～2 ^n-1r ' is in series, the major and minor resistance that in major and minor apparent resistance chain, weights j equates, 2 ^jr and 2 ^jr ' is the antithesis power resistance that a pair of resistance is equal, and only weighing resistance can be a resistance, can be also 2 ^jthe series connection of individual reference resistance; Each power resistance digital switch by Digital Signals in parallel; 2 ^jr digital switch S in parallel ^j, by digital signal D _jcontrol; 2 ^jr ' digital switch in parallel

by digital signal

control; Make S _jwith

for reciprocal Dual switch, Sj and

in always have a conducting and another cut-off, so antithesis resistance always one access one remove, make major and minor apparent resistance chain under Digital Signals, become the N bit digital formula adjustable resistor R of a pair of complementation _yand R ' _y, by R _yand R ' _ybe called main chain and secondary chain, claim to work as R _ywhile becoming large, R ' _ydiminishing of equivalent, vice versa, so R _y+ R ' _ywith electric current I be steady state value, its main chain voltage is V _y=R _y* I; Digital-to-analogue conversion process is: Digital Signals Dual switch, thereby control in antithesis chain, weigh resistance, and make to weigh resistance (2 ^n-1r ..., 2 ⁰r) can access arbitrarily and remove, form power voltage, get rid of after stray voltage, only weigh voltage (2 ^n-1Θ * I ..., 2 ⁰Θ * I) can add and subtract arbitrarily, so main chain voltage V _y(2 ⁿΘ * I～0) scope is adjustable, quantization step Δ=Θ * I; Because this device is exported adjustable power voltage by Digital Signals, so be antithesis chain power voltage-type DAC; On the basis of this DAC, if adopt step-by-step method just to become the successively comparison A/D C based on antithesis chain, if adopt anticipation formula method to add deserializer structure, just become the anticipation formula ADC based on antithesis chain;

Notice that digital switch resistance is semi-conducting material, variations in temperature can cause change in resistance, in order to offset this variation, weighs ohmically additional resistance and adopts material identical with switch resistance or that characteristic is consistent;

Introduce dead resistance and clean power resistance

meaning: known V _y=(∑ II ^jr+m*r) * I, in formula, m is that main resistor chain removes resistance number, this is a random number, can cause complex circuit designs, so will introduce clean power resistance

concept, order and

that is, because power resistance 2 ^jr is at clean power resistance

basis on to have added size be the dead resistance of r, so, the resistance 2 of holding power ^jr is when accessing or removing, and its parasitic resistance values r remains unchanged, and changing value just equals only to weigh resistance value; Dead resistance total value in main chain is constantly equal to N*r (being labeled as Nr), and the power voltage that obtains main resistor chain is because N*r*I is constant, the circuit that deducts N*r*I is easily realized, and obtains main chain and only weighs voltage

For example, there are 8 position digital signal D ₇d ₆d ₅d ₄d ₃d ₂d ₁d ₀=10011000, learn its D ₇, D ₄, D ₃position equals 1, controls its S ₇, S ₄, S ₃open circuit, other switch short circuit, by j=7,4, three resistance 2 with sovereign right of 3 ⁷r, 2 ⁴r, 2 ³r is set to access resistance, uses respectively II ⁷r, II ⁴r, II ³r describes, and obtains accessing the total resistance of resistance and is

other 5 resistance 2 with sovereign right ⁶r, 2 ⁵r, 2 ²r, 2 ¹r, 2 ⁰r is arranged to remove resistance, and its total resistance is 5*r, main chain all-in resistance

by subtracter, cut 8*r, obtain

so far, realize digital signal and to corresponding main chain, only weighed the conversion of voltage, realized digital-to-analogue conversion; Main chain is weighed voltage V only _y0quantization unit be Δ,

Δ is also minimum voltage counterweight unit, and a N position antithesis chain, has 2 ⁿindividual uniform quantization units of delta;

The explanation of embodiment and accompanying drawing, convenient in order to check, have a mind to embodiment is corresponding with the numbering of accompanying drawing, provide an accompanying drawing explanation and just follow to embodiment, both are combined to description, before the symbol no longer explanation conventionally explained.Agreement: tested voltage for u, U represent, exchange use small letter as u _i, u _g, u _wdeng, capitalization U for direct current _y, U _y0, U _wdeng; Known voltage, power voltage (claiming again voltage counterweight) represent with V, as V _y, V _y0deng, claim counterweight voltage.

Fig. 1 .1---N position antithesis chain type digital to analog converter schematic diagram

2 ⁰r～2 ^n-1r is resistance with sovereign right, S ₀～S _n-1for the digital switch with corresponding resistance parallel connection with sovereign right, jointly form main chain; 2 ⁰r '～2 ^n-1r ' is secondary power resistance, digital switch for corresponding with pair power resistance, forms secondary chain jointly; V _ycombined potential for main chain; ∑ is adder; V _nrequal main chain dead resistance sum; V _y0for main chain is weighed voltage only; Current source A _⊕and A _▲; The anodal V of system _p, sub-anodal V _⊕, power supply ground

sub-ground V _▲; (A _⊕, A _▲, V _p, V _⊕,

v _▲for general symbol(s));

Embodiment 1.1---and N position antithesis chain type digital to analog converter, is called for short DODAC;

The current source of connecting on resistance chain has just become general resistance chain, clearly agreement: all current source A in file _{⊕ Φ}and A _{▲ Φ}be option, the antithesis chain described in all embodiment is all general resistance chain, has contained and has had current source formula antithesis chain, no current source formula antithesis chain and current source to add three kinds of main chain formula resistance chains; Near the anodal V of system _pseries current source A _{⊕ Φ}after, A _{⊕ Φ}the voltage of the other end is V _{⊕ Φ}, claim V _{⊕ Φ}for sub-anodal, if do not adopt current source A _{⊕ Φ}, anodal V _pwith the anodal V in Asia _{⊕ Φ}merging and general; Equally, near system power supply ground

series current source A _{▲ Φ}after, A _{▲ Φ}other end voltage is V _{▲ Φ}, claim V _{▲ Φ}for sub-ground; If do not adopt current source A _{▲ Φ},

with sub-ground V _{▲ Φ}merging and general; Current source can only select one, to select A _{⊕ Φ}for example, because chain electric current I=V during no current source _{⊕ Φ}/ R _zso, current source A _{⊕ Φ}the definite optimum of parameter turns to: make current source A _{⊕ Φ}source electric current I _{⊕ Φ}be adjusted to I; Notice adjusting source electric current I _{⊕ Φ}time V _{⊕ Φ}can change again I _Φalso can change, so this is an interactive adjusting and design, finally realize I _{⊕ Φ}=I _Φ, can improve anti-interference and suppress switch burr voltage; If the in the situation that of high-precision current source, current source A _{⊕ Φ}source electric current I _{⊕ Φ}under arbitrary load, high accuracy is constant, can be regardless of I _Φand determine arbitrarily source electric current I _{⊕ Φ}value; At this moment, if secondary chain is replaced with wire, make only remaining main chain of antithesis chain, just become current source and add main chain formula DAC, obtain equally main chain and only weigh voltage equation:

realize DA conversion.A _{⊕ Φ}, V _{⊕ Φ}, V _pand A _{▲ Φ}, V _{▲ Φ},

principle in this unified explanation, below explain no longer separately.

This transducer is by main chain 2 ⁰r～2 ^n-1r and secondary chain 2 ⁰r '～2 ^n-1r ' connects and forms antithesis chain, and the order of series connection is: ground → main chain → secondary chain → V _⊕; Because electric current I is fixed, so need only digital signal, determine the access of all resistance with sovereign right and remove after state, just obtained main chain total voltage

by adder ∑, cut stray voltage V _nr, just obtain total clean power voltage V _y0,

complete digital-to-analogue conversion; Digital signal has been directly changed into magnitude of voltage; Stray voltage V in fact _nrbe a constant, just make output valve move on the whole V _nr, can not consider yet;

The operating current of this transducer is fixed value I=V _⊕/ (2 ⁰r+2 ¹r+ ... + 2 ^n-2r+2 ^n-1r+N*r), if make I equal the minimum current of current DAC, as a comparison, the required current maxima of current DAC is I 2 ⁿdoubly.

Fig. 1 .2---N position antithesis chain type digital to analog converter graphical diagram

R _ybe 2 ⁰r～2 ^n-1r and S ₀～S _n-1graphical diagram, R ' _ybe 2 ⁰r '～2 ^n-1r ' and

graphical diagram.

Fig. 1 .3---N bit digital formula adjustable resistor graphical diagram

R _ybe 2 ⁰r～2 ^n-1r and S ₀～S _n-1graphical diagram, graphical diagram is N bit digital formula adjustable resistor.

Embodiment 1.3---N bit digital formula adjustable resistor (Fig. 1 .3)

This enforcement is exactly that the main resistor chain in embodiment 1.1 is independently used, and under the control of digital signal, accesses corresponding power resistance, power resistance

can be arranged to arbitrarily access or remove according to digital signal, make the total resistance value between AA-BB can be between change, change interval is

Fig. 1 .4---mixed digital-analogue multiplier schematic diagram

CF is integrated operational amplifier, u ₁and u ₂for end of oppisite phase input signal, u ₃and u ₄for in-phase end input signal, R _c1, R _c2, R _c3, R _c4, be fixed resistance, R _czand R _cFfor above-mentioned N bit digital formula adjustable resistor, U _outfor output voltage.

Embodiment 1.4---mixed digital-analogue multiplier operation principle

If by the R in figure _czand R _cFchange fixed resistance into, this figure is exactly a traditional differential amplifier circuit, and the function that can realize plus-minus and amplify, becomes summation-amplifier; Make R _c1=R _c2=R _c3=R _c4, R _cz=R _cF, at this moment differential amplifier circuit summation is amplified pass and is: U _out=(R _cF/ R _c1) (u ₁-u ₂+ u ₃+ u ₄); If by digital signal Synchronization Control N bit digital formula adjustable resistor R _czand R _cFsize, just changed multiplication factor, become with input signal the relation multiplying each other.

Fig. 1 .5.1---triangle GS is voltage follower graphical diagram, and output voltage equals input voltage, is all U _x2, but improved load capacity, with triangle, in institute's drawings attached, represent this device, because implication is simple, without mark GS;

Fig. 1 .5.2---ratio reducer Ψ _xgraphical diagram; Ψ is reducer symbol (Ψ capitalization), and subscript X is asterisk wildcard, and reduction ratio is ψ _x(ψ small letter is not marked in figure), input signal U _x1, U ' _x1; Output signal U _x2=(U _x1+ U ' _x1)/ψ _x;

Fig. 1 .5.3---ratio reducer Ψ _xone of schematic diagram; Wherein integrated transporting discharging GS is Fig. 1 .5.1 voltage follower, because voltage follower GS is empty disconnected as the in-phase end of input, so R _x1and R _x2middle electric current equates, has: U according to dividing potential drop relation and superposition law _x2=(U _x1+ U ' _x1) * R _x2/ (R _x1+ R _x2), make ψ _x=(R _x1+ R _x2)/R _x2so, U _x2=(U _x1+ U ' _x1)/ψ _x;

The antithesis chain type digital to analog converter schematic diagram of Fig. 1 .6---S level * n position

Definition α, β, γ ... be the 1st, 2,3 ... level; The sub level that Φ wildcard is all, dotted line frame DODAC _Φi.e. Φ level DODAC; In figure, make figure place n at different levels _α, n _β..., n _sall equal n; At DODAC _Φin, 2 ⁰r _Φ～2 ^n-1r _Φfor resistance with sovereign right, S _{Φ 0}～S _{Φ (n-1)}for the digital switch with corresponding resistance parallel connection with sovereign right, jointly form main chain; 2 ⁰r _Φ'～2 ^n-1r _Φ' be secondary power resistance, digital switch for the parallel connection of corresponding secondary power resistance, forms secondary chain jointly; V _{y Φ}combined potential for main chain; V ' _{y Φ}for output voltage; V _{⊕ Φ}for sub level resistance chain voltage, be called for short chain voltage; Ratio reducer Ψ _{y Φ}; Voltage follower GS; Public part has: ∑ _zfor total summer; The total scaled value V of stray voltages at different levels _{∑ r}, be called for short total stray voltage; Dac value V _y0;

The antithesis chain type digital to analog converter principle of embodiment 1.6.1---S level * n position

Adopt unified modularized design, make DODAC at different levels _Φfigure place n _Φall equal n; At Φ level DODAC _Φin, DODAC _Φby main chain 2 ⁰r _Φ～2 ^n-1r _Φwith secondary chain 2 ⁰r _Φ'～2 ^n-1r _Φ' connect and formation antithesis chain, the order of Φ level subchain series connection is: ground → main chain → secondary chain → chain voltage V _{⊕ Φ}; Because chain electric current I _Φfixing, so as long as Φ stages of digital signal has been determined Φ level DODAC _Φthe access of all resistance with sovereign right and removing after state, has just obtained main chain total voltage

through voltage follower GS, improve V _{y Φ}load capacity; Ratio reducer Ψ _{y Φ}by main chain total voltage V _{y Φ}with secondary output voltage V ' _{y (Φ+1)}) phase adduction reduction 2 ⁿdoubly just become Φ level output voltage V ' _{y Φ}, that is: V ' _{y Φ}=(V _{y Φ}+ V ' _{y (Φ+1)})/2 ⁿ; If make V " _{y Φ}for V _{y Φ}to the voltage of total output, so V _{y Φ}to V " _{y Φ}to pass through (Φ-1) individual ratio reducer, so V " _{y Φ}=V _{y Φ}/ 2 ^{(Φ-1) * n}; At total summer ∑ _zin; Dac value V _y0+ V _{∑ r}=V _{y α}+ V ' _{y β}=V _{y α}+ V " _{y β}+ V " _{y γ}+ V " _{y δ}total stray voltage V _{∑ r}be a constant, make output valve move on the whole V _{∑ r}, also can ignore; During chip manufacturing, with unit resistance, can reduce error, so only weigh resistance

have two kinds of structures, a kind of is single resistance-type, only weighs resistance value and equals

a kind of is 2 ^jindividual reference resistance series connection, only weigh resistance

equal 2 ^jindividual be added;

As long as this transducer is by all DODAC _Φchange power current type DAC submodule into, just formed the power current type digital to analog converter of S level * n position;

If the ratio of omission reducer Ψ _{y Φ}, but by adjusting chain voltage V at different levels _{⊕ Φ}adjust output voltage, make V _{⊕ Φ}=V _⊕/ Ψ _{v Φ}, Ψ in formula _{v Φ}be that Φ level chain voltage is with respect to system power supply voltage V _⊕reduce multiple, make Ψ _{v Φ}=1/2 ^{(φ-1) * n}, obtain equally output voltage V ' _{y Φ}=V _{y Φ}/ 2 ^{(φ-1) * n}; Certainly, can reducer, also adjust chain voltage;

The unit resistance antithesis chain type digital to analog converter principle of embodiment 1.6.2---S level * n position

Whole identical with embodiment 1.6.1, difference is, power resistance 2 ^jr is by 2 ^jindividual unit resistance

be in series, each R switch in parallel, Digital Signals decoder, decoder control switch, thereby the access number of control unit resistance R, thus control main chain voltage; Its advantage is the matching problem of having removed additional resistance and switch resistance from;

Fig. 2 .1---successively compare type N position antithesis chain type analog to digital converter schematic diagram, be called for short DOADC

2 ⁰r～2 ^n-1r is resistance with sovereign right, S ₀～S _n-1for the digital switch with corresponding resistance parallel connection with sovereign right, jointly form main chain; 2 ⁰r '～2 ^n-1r ' is secondary power resistance, digital switch for corresponding with pair power resistance, forms secondary chain jointly; V _yfor main chain combined potential; u _itested AC signal for input; Dotted line frame QZDL is front end circuit, and QZDL comprises and [adopts and protect device CB, u _gin order to adopt guarantor's output signal, (CB is to u _iadopt the signal after guarantor, have positive-negative polarity); Positive and negative arbiter ZFP _x, U _gfor to u _goutput signal after differentiating (only having positive polarity); Polarity register D _x; Logarithmic compression law module LOG; U _y1for preposition output voltage; Y _xfor sampling executive signal]; CB _αfor the virtual guarantor's device of adopting; U _y0for tested net signal; ∑ _yfor adder; V ' _nrfor offsetting stray voltage; U _yfor tested voltage; Ba is comparator; H is comparison value; (d type flip flop) DH is comparison value register, and the D in DH is input and Q _hfor output; H ' is the temporary value of h; The triangle place of all triggers is trigger end below, and cp is triggering signal; The signal input part of trigger all represents with D; Dotted line frame XHYW is circulating register, and XHYW comprises that [N+1 D flip-flop, for fear of obscuring with input D, is renamed as DY trigger: DY by D flip-flop _n-1～DY ₀and DY _xa circulating register of common formation, Y _xwith

be respectively trigger DY _xtrue value and non-value output, same, Y _jwith be respectively trigger DY _jtrue value and non-value output, Y _jserve as DG _jtriggering signal,

dG is served as in negative saltus step _j-1put 1 signal]; Cp is clock pulse; Dotted line frame KGJC is switch register, and KGJC comprises [N G D-flip flop: DG _n-1～DG ₀, D _jfor trigger DG _jtrue value output, be S _jcontrol signal;

for D _jfor non-, be control signal; S _gfor 1 end, R are put in negative saltus step _gfor negative saltus step sets to 0 end]; Dotted line frame KGKZ is on-off controller, and KGKZ comprises above-mentioned [XHYW, KGJC and DH tri-parts];

Embodiment 2.1---and successively compare type N position antithesis chain type analog to digital converter, be called for short basic model DOADC

Basic model DOADC operation principle is divided into the operation principle introduction of a plurality of modules

Antithesis chain operation principle: with embodiment 1.1 something in common be: Digital Signals Dual switch, can obtain main chain total voltage

difference is: the digital signal in embodiment 1.1 is known, and trying to achieve of digital signal in the present embodiment is to rely on described logical circuit below; Comparator Ba is exactly an electronic balance, tested voltage U _ybe connected to the in-phase end of Ba, keeping phase U _ystable, U _y=U _y0+ V ' _nr, V ' _nrin order to offset dead resistance V _nrimpact, end of oppisite phase V _yvoltage counterweight, be in U _yamount relatively and in adjustment process, V _y=V _y0+ V _nr, U _ywith V _yby comparator Ba comparison, obtain comparison value h, work as U _y> V _ytime h=1, need to increase voltage counterweight, work as U _y< V _ytime h=0, need to reduce voltage counterweight; Note V _ybeing a dynamic value, is one group of counterweight, as weighing apple (voltage) in the balance, takes counterweight examination one by one, determines that it is to stay or to take away that examination adds counterweight, so V _ybe that quantization changes, claim to be determined going or staying to minimum quantum counterweight Δ always, cannot be again toward calling in the following text, final definite V _y0be regarded as the weight U of apple (voltage) _y0, full text V _y=U _ybe the concept in measuring accuracy, | V _y-U _y| < Δ; With electronic balance Ba, claim tested voltage U _yvalue, by on-off controller, examination voltage counterweight one by one, along with cp pulse, by resistance 2 with sovereign right ^jr is by 2 ^n-1r～2 ⁰the order of R one by one serve as the resistance of trying, when 2 ^jr serves as while trying resistance, if h=1 illustrates that this electricity counterweight adds that rear total voltage does not surpass U _y, by on-off controller, make digital register signal D _j=1, D _j=1 by 2 ^jr is defined as accessing resistance; If h=0, illustrates that this electricity counterweight adds that rear total voltage surpasses U _y, by on-off controller, make digital register signal D _j=0, D _j=0 by 2 ^jr is defined as removing resistance; When 2 ^n-1r～2 ⁰after R is all determined, U _ybe converted into digital signal D _n-1... D ₁d ₀thereby, realized AD conversion; As the peripheral circuit of antithesis chain, its structure is too numerous to enumerate, below takes a single example;

The operation principle of front end circuit QZDL: as sampling executive signal Y _xwhen=1 rising edge arrives, order is adopted and is protected device CB to input exchange signal u _i(having positive-negative polarity) adopts guarantor, obtains an input that keeps fixing and adopt guarantor's signal u within the sampling period _g; Positive and negative arbiter ZFP _xto u _gcarry out polarity discriminating and processing, work as u _gduring > 0, make polarity register D _x=0, ZFP _xdifferentiation output signal U _g=u _g, work as u _gduring < 0, make D _x=1, U _g=-u _gso,, U _gonly has positive polarity U _g=| u _g|; Simulation logarithmic compression law module LOG is option, (LOG module has mature technology when adopting analog companding technology, to need LOG module, do not repeat, mention herein log law when compression comprise as A compression rule and the μ compression of logarithmic approximation compression rule restrain), U at this moment _y1equal U _glogarithmic compression law, what after the conversion of AD uniformly-spaced, obtain is the digital signal of logarithmic compression law; U when not adopting LOG module _y1=U _g, AD is converted to linear; U _y1for front end circuit output voltage, the following summary of this process is: front end circuit QZDL is by u _iconvert preposition output signal U to _y1; Because in anticipation formula ADC below, need to make U _y1through one, adopt and protect device CB _wbecome U _y0, for the purpose of numbering unification, there is no CB _wjust at U _y1with U _y0between add every virtual adopting and protect device CB _α, CB in fact _αbe exactly wire, at this moment a U _y1=U _y0; Because of U _y0with total clean power voltage V _y0become relativity, so claim U _y0for clean measured signal;

∑ _yeffect with Ba: U _y0by adder ∑ _yincrease V ' _nr, just obtain measured signal U _y=U _y0+ V ' _nr; Comparator Ba is exactly an electronic balance, and its in-phase end is U _y, be tested voltage, end of oppisite phase is V _y, be voltage counterweight, U _ywith V _ycompare, i.e. U _y0+ V ' _nrwith V _y0+ V _nrcompare, i.e. U _y0with V _y0relatively, the impact of having offset dead resistance, obtains comparison value h and flows to DH, and DH is the register of comparison value h, when the negative saltus step of cp, the h value of DH is kept in as h ' is relatively more stable, and the assignment signal providing to KGJC is provided h '; H ' is connected to DG ₀～DG _n-1d end, wait for and put number, work as U _y> V _ytime have h '=1, examination making alive counterweight is stayed, work as U _y< V _ytime have h '=0, examination making alive counterweight is removed;

Analysis meeting subsequently knows, each cp pulse only can trigger DG ₀～DG _n-1one of them, h ' puts number to it;

The operation principle of circulating register XHYW saltus step: DY _n-1～DY ₀and DY _xcommon form a circulating register, make one 1 and circulate saltus step in XHYW; According to prior art, can obtain so circulation: along with beating again and again of cp, 1 saltus step is sequentially Y _n-1=1 → Y _n-2=1 → ... → Y ₃=1 → Y ₂=1 → Y ₁=1 → Y ₀=1 → Y _x=1 → Y _n-1=1 → Y _n-2=1 ... such cyclic shift, this is prior art, does not repeat;

Switch register KGJC operation principle: KGJC adopts the DG trigger can simplified structure, DG trigger is developed by d type flip flop, the explanation in embodiment 2.2 of its operation principle, here first introduce the function of DG trigger, D input is identical with traditional d type flip flop D end, for data input pin, when trigger impulse rising edge arrives, the data of D are delivered to output D _j; H ' is connected to DG ₀～DG _n-1d end, wait for and put number, when cp pulse makes the Y of XHYW _jwhile there is positive transition, only has DG _jbe triggered, so h ' only can be to DG _jput number; DG trigger and d type flip flop difference be putting number end, in d type flip flop, and S _dfor low level, put 1 end, work as S _d=0, output D _jput 1, R _dfor low level sets to 0 end, work as R _d=0, output D _jset to 0; And DG trigger and d type flip flop are different, S _gfor negative saltus step, put 1 end, work as S _gthere is negative saltus step moment in end, makes output D _jput 1, if not the moment in negative saltus step, even if S _g=0, can be to output valve D yet _jexert an influence, in like manner, R _gfor negative saltus step sets to 0 end, work as R _gthere is negative saltus step moment, output D in end _jset to 0;

This system completes a sampling-AD change-over period needs N+1 cp pulse (0～N), and the 0th pulse completes signal voltage sampling and preset Dual switch; The 1st to N pulse is N position AD transfer process, and concrete logical process is as follows:

Always have so moment, just make DY in XHYW _xd=1; ▲ when the 0th cp rising edge of a pulse arrives, make Y _xthere is positive transition and

there is negative saltus step, because

received DG _n-1s _gend, and received DG _n-2～DG ₀r _gend, institute is so that D _n-1=1 and D _n-2～D ₀=0, this group Digital Signals antithesis chain, only accessing the resistance of trying is .2 ^n-1r, now main chain total voltage

meanwhile, Y _xpositive transition is the instruction that makes CB sampling, known from foregoing front end circuit QZDL and ∑, obtains tested direct current signal U _y=U _y0+ V ' _nr; Ensuing process is designated hereinafter simply as the calculating process of h ', compares U by comparator Ba that is: _ywith V _ysize, obtain comparison value h and equal 0 or 1, if V _y< U _y, h=1, if V _y> U _y, h=0; Next the negative saltus step of cp, trigger DH is the d type flip flop that trailing edge triggers, so it is temporary that h is delivered to the output h ' of DH; H ' is connected to DG ₀～DG _n-1d end, prepare to put number; The 0th pulse is called " priming pulse ", makes ADC complete the preparation of current sampled signal being carried out to AD conversion: access the resistance 2 of trying ^n-1r also makes DY _n-1in D=1; Ensuing the 1st transfer process to N pulse is following cyclic process: (★ is circulation section start)

Make j from N-1, progressively change to 0 N cyclic process: ★ and 1. determine that examination adds counterweight going or staying: when N-j cp rising edge of a pulse arrives, because DY _jin D=1, so DY _jin Y _jpositive transition and

negative saltus step, Y _jdG is served as in positive transition _jtriggering signal, the h ' of its D end is sent to output D _j, D _j=h ' makes S _j=h ', determines the resistance 2 of trying thus ^jr is access resistance or removes resistance; If 2. h '=1, represents V _y< U _y, voltage counterweight is measured not enough, and examination adds counterweight 2 ^jr need to be retained in becomes access resistance on electronic balance, and Y _jpositive transition is just in time sent to DG by h '=1 _joutput D _j=1, D _j=1 makes S _j=1, thus determined 2 ^jr is access resistance; In like manner, if h '=0 represents V _y> U _y, need to determine 2 ^jr is for removing resistance, and Y _jpositive transition is just in time sent to DG by h '=0 _joutput D _j=0, D _j=0 can make S _j=0, thus determined 2 ^jr is for removing resistance; 3. except DG _jother outer DG ₀～DG _n-1trigger end no pulse, so fan-out is according to constant; 4. due to Y _j=1 delivers to DY _j-1d end, think that the saltus step of XHYW gets ready; 5. add next examination and add counterweight:

at DG _j-1s _gthe negative saltus step of end, makes at DG _j-1output D _j-1=1, by 2 ^j-1r, as the resistance of trying, obtains new V _y, again carry out the calculating process of h ', h ' is delivered to DG ₀～DG _n-1d end; Assignment j:=j-1, h ' waits for next bit DG _jput number; If the circulation of ★ place is got back in j>=0 item;

Supplement a bit, during j=0, i.e. somewhat special during N pulse, DY ₀'s for unsettled useless, Y ₀=1 delivers to DY _xd end, get back to ▲ locate, start the 0th pulse in new cycle, for the next one sampling-AD change-over period prepares;

After a N+1 like this pulse, completed a sampling-AD change-over period, 2 ^n-1r～2 ⁰r and D _n-1～D ₀all all determined U _y0be converted into digital signal D _n-1... D ₁d ₀thereby, realized AD conversion;

Fig. 2 .2---G D-flip flop fundamental diagram, dotted line frame DG _jfor G D-flip flop block diagram; D _jwith be respectively G D-flip flop DG _jtrue value and non-value output; DY _jfor D flip-flop; S _dfor DY _jlow level put 1 end; R _dfor DY _jlow level set to 0 end; S _gfor DG _jnegative saltus step put 1 end; R _gfor DG _jnegative saltus step set to 0 end; D is data input pin; Cp end (or triangle end) is trigger end; C ₁and C ₂for saltus step electric capacity; R ₁and R ₂for step resistance; SR is hot end;

Fig. 2 .3 is G D-flip flop graphical diagram, each label DG _j, D _j,

d, cp, S _g, R _gin Fig. 2 .2, explained;

Embodiment 2.2---G D-flip flop operation principle

G D-flip flop is developed by D flip-flop, DY _jfor D flip-flop; In d type flip flop, S _dfor low level, put 1 end, work as S _d=0, output D _junconditionally put 1; R _dfor low level sets to 0 end, work as R _d=0, output D _junconditionally set to 0; D is data input pin, and cp end (triangle end) is trigger end, at the S that satisfies condition _d=1 and R _dunder=1 prerequisite, when trigger impulse arrives, the data of D end are sent to D _jend; And G D-flip flop and d type flip flop are different, S _gfor negative saltus step, put 1 end, only work as S _gthere is negative saltus step moment in end, makes output D _jput 1, if not the moment in negative saltus step, even if S _g=0, can be to output valve D yet _jexert an influence, its circuit theory is: work as S _g=1 o'clock C ₂high potential 1 is all received at two ends, so C ₂middle steady state voltage is 0, at this moment S _d=1, to DY _joutput valve without impact; Work as S _gjump at 0 o'clock by 1, due to C ₂voltage can not suddenly change, so this moment S _d=0, but because SR end is high potential 1, form charge circuit SR → R ₂→ C ₂→ S _gto C ₂charging, according to the known charge constant τ=R of electric circuit knowledge ₂* C ₂, C after elapsed time τ ₂be full of 63%, C after 3 τ ₂be full of 95%, make S _d=1, design makes τ very little, so only at S _gby 1, jump to 0 moment S _d=0, make output D _junconditionally put 1; In like manner, R _gfor negative saltus step sets to 0 end, only work as R _gthere is negative saltus step moment in end, makes output D _jset to 0, if not the moment in negative saltus step, even if R _g=0, can be to output valve D yet _jexert an influence; At the S that satisfies condition _gand R _gall do not have to occur under the prerequisite of negative saltus step, when trigger impulse arrives, the data of D end are sent to D _jend;

Fig. 3 .1---category-A N position anticipation formula antithesis chain analog to digital converter schematic diagram

Parallel model analog to digital converter (hereinafter to be referred as deserializer, because be mature technology, only having sketch); Before explained have: 2 ⁰r～2 ^n-1r; S ₀～S _n-1; 2 ⁰r '～2 ^n-1r ';

v _y; QZDL; CB; ZFP _x; D _x; LOG; u _i; u _g; U _g; U _y1; U _y0; V ' _nr; Need having of explanation: anticipation arithmetic unit YSQ; Category-A (q-1)～0 accurate measurement deserializer BXQ _q, comprise [chain resistance R _q～R ₁; Reference potential V _q-1～V ₀; Comparator B _q-1～B ₁; Encoder BMQ _q; Accurate measurement correction digital quantity (d _q-1... d ₀); ]; (q+t-1)～q position bigness scale deserializer BXQ _t, comprise [chain resistance R ' _t～R ' ₁; Reference potential V ' _t-1～V ' ₀; Comparator B ' _t-1～B ' ₁; Encoder BMQ _t; Bigness scale correction digital quantity (d ' _t-1... d ' ₀)]; Correction is adopted and is protected device CB _w; Correction adder ∑ _w; Correction interchange value u _w; The positive and negative arbiter ZFP of correction _w; Correction polarity register d ' _q; Correction absolute value U _w; Correction absolute value amplifier FD _w; Correction absolute value value of magnification U _wT; Sampling pulse signal Y _x; Dead resistance adder ∑ _y;

Embodiment 3.1---category-A N position anticipation formula antithesis chain analog to digital converter (Fig. 3 .1)

Definition: ● with D (X), represent digital quantity corresponding to analog voltage X, for example, with D (V _y) expression voltage V _ycorresponding digital quantity D _n-1d _n-2... D ₁d ₀, i.e. D (V _y)=D _n-1d _n-2... D ₁d ₀; On off state S _n-1s _n-2... S ₁s ₀with digital quantity D _n-1d _n-2... D ₁d ₀correspondent equal one by one; In like manner, d (U _w)=d _q+t-1d _q+t-2... d ₁d ₀, ● take a as upper target is as just completing the current amount of conversion, such as tested voltage U _yjust complete AD conversion and just used U ^a _yrepresent, claim current voltage U ^a _y, similar have, V ^a _y, D ^a _j, S ^a _jclaim current amount; Take b as upper target is amount to be turned, be close to and follow U ^a _ybe sampled and be about to the measured U of conversion _yuse U ^b _yrepresent, claim voltage U to be turned ^b _y, with U ^b _ycorresponding have a numeral amount D to be turned ^b _j, V ^b _yfor weighing the electric counterweight of amount to be turned; In like manner, V ^s _yclaim anticipation amount electricity counterweight, D ^s _jclaim anticipation digital quantity; ● V ^f _yclaim U ^b _yresult quantities, i.e. U ^b _y-V ^f _y< Δ; ● voltage increment is called for short correction, and correction is U namely ^b _y-U ^a _ydifference, w is that lower aiming symbol is correction symbol, as CB _w, ∑ _w, u _w, ZFP _w, U _w; ● digital quantity (1 _q) expression D _q=1, (1 _q) corresponding simulation power voltage is 2 ^qΔ; In like manner, (0 _q) expression D _q=0; ● make 2 ^q=Q, 2 ^t=T;

Operation principle: this ADC is by the position bigness scale deserializer BXQ of N position antithesis chain, q～(q+t-1) _t(q-1)～0 accurate measurement deserializer BXQ _qthree grades of compositions; N position is divided into three sections: the high-order g position (D of section of foundation _g+t+q-1... D _t+q), bigness scale section meta t position (D _t+q-1... D _q) and accurate measurement section low level q position (D _q-1... D ₀); Known corrections amount u _w=U ^b _y-U ^a _y, suppose that sampling density is higher, guarantee to make correction u _wcorresponding digital variable quantity < 2 ^t+q, so, as long as to correction u _wcarry out AD conversion and can obtain complete AD conversion, for this reason, with bigness scale deserializer BXQ _tto correction u _wcarry out bigness scale, by the digital quantity after bigness scale and Contemporary Digital amount V ^a _ybe added, obtain U ^b _yanticipation digital quantity V ^s _y, at V ^s _ybasis on carry out accurate measurement; Suppose and obtain current amount U ^a _yaD conversion D (V ^a _y)=(D ^a _n-1d ^a _n-2... D ^a ₁d ^a ₀), this example is treated and is turned voltage U ^b _yan AD conversion minute following step:

The first step, asks correction bigness scale value d (U ^t _w), by (q+t-1)～q position bigness scale deserializer BXQ _tobtain d (U ^t _w), obtain U ^b _y-U ^a _ythe AD conversion of the position of q～(q+t-1), principle is that 1. QZDL is by u _iconvert clean measured signal U to _y1; U _y1the amount of being corrected is adopted and is protected device CB _wstop, lag behind U _y0a sampling period, as certain U _y0after converting, become U ^a _yand send sampling pulse Y _xafter, U _y1as U ^b _ybe sent to CB _woutput become U _y0so, at sampling pulse Y _xthe moment arriving, U _y1for U ^b _yand U _y0for U ^a _y; 2. by correction adder ∑ _wcomplete U ^b _ywith U ^a _ycorrection computing u _w=U ^b _y-U ^a _y=U _y1-U _y0, 3. by the positive and negative arbiter ZFP of correction _wto u _wcarry out polarity discriminating and processing, work as u _wduring > 0, make polarity register d ' _q=0, ZFP _wdifferentiation output signal U _w=u _w; Work as u _wduring < 0, make d ' _q=1, U _w=-u _wso,, U _wonly have positive polarity, complete the signed magnitude arithmetic(al) U of correction _w=| u _w|, U _w=(0～2 ^t+qΔ); 4. correction absolute value amplifier FD _wby correction absolute value U _wzoom into correction absolute value value of magnification U _wT, excursion is (0～V _⊕; V _⊕=2 ^g+t+qΔ); 5. by bigness scale deserializer BXQ _tto U _wcarry out AD conversion, obtain correction U _wthe bigness scale value d (U of high range ^t _w)=d ' _t-1d ' _t-2... d ' ₁d ' ₀=d _q+t-1d _q+t-2... d _q+1d _q, (make d ' _x=d _q+xas d ' _t-1=d _q+t-1, d ' ₀=d _q, accurate measurement position q superposes in subscript; ), bigness scale value quantization unit digital quantity is (1 _q), analog quantity is 2 ^qΔ, meticulousr measurement awaits two steps below and completes;

The accurate measurement value d (U of the meticulous scale of correction ^q _w)=d _q-1d _q-2... d ₁d ₀wait until that it is (1 that the 3rd step completes ，Qi minimum quantization unit digital quantity ₀), analog quantity is Δ, easily knows accurate measurement value d (U ^q _w)=(d _q-1d _q-2... d ₁d ₀) < (1 _q), accurate measurement value sum is less than the quantization unit of bigness scale value; Total correction d (U _w) equal correction bigness scale value d (U ^t _w) and correction accurate measurement value d (U ^q _w) sum, d (U _w)=d (U ^t _w)+d (U ^q _w)=(d _q+t-1d _q+t-2... d _q+1d _q)+(d _q-1d _q-2... d ₁d ₀)=(d _q+t-1d _q+t-2... d _q+1d _qd _q-1d _q-2... d ₁d ₀), with analog scale, be shown U _w=U ^t _w+ U ^q _w, such as 6.3=6+0.3;

Second step, calculates anticipation value d (U ^s _y), make polarity register d ' _qcorresponding d (U ^t _w) d _qposition, makes d (U ^td _w)=d (U ^t _w)+d ' _q=(d _q+t-1d _q+t-2... d _q+1d _q)+d ' _q; Work as d ' _q=0 o'clock, d (U ^td _w)=d (U ^t _w), work as d ' _q=1 o'clock, d (U ^td _w)=d (U ^t _w)+(1 _q);

Work as u _wfor timing, d ' _q=0, known anticipation digital quantity D (U ^s _y)=D (U ^a _y)+d (U ^td _w)=D (U ^a _y)+d (U ^t _w)+(0 _q)=D (U ^a _y) ++ d (U ^t _w), at this moment, amount U to be turned ^b _yshould equal current amount U ^a _yadd correction U _w, U ^b _y=U ^a _y+ U _w, with digital quantity, be expressed as D (U ^b _y)=D (U ^a _y)+d (U _w)=D (U ^a _y)+d (U ^t _w)+(0 _q)+d (U ^q _w)=D (U ^a _y)+d (U ^td _w)+d (U ^q _w)=D (U ^s _y)+d (U ^q _w), and according to the D (U having obtained above ^a _y) and D (U ^td _w), then can obtain D (U through arithmetic unit YSQ ^s _y), so as long as again by d (U ^q _w) just measure and can complete U ^b _yaD conversion, for this reason, antithesis chain is according to anticipation digital quantity D (U ^s _y) preset Dual switch, obtain main chain anticipation combined potential V ^s _y=U ^a _y+ U ^td _w;

Work as u _wwhen negative, d ' _q=1 _q, known anticipation digital quantity D (U ^s _y)=D (U ^a _y)-d (U ^td _w), amount U at this moment to be turned ^b _yshould equal current amount U ^a _ysubtract correction U _w, U ^b _y=U ^a _y-U _w, with digital quantity, be expressed as D (U ^b _y)=D (U ^a _y)-d (U _w)=D (U ^a _y)-d (U ^t _w)-d (U ^q _w)=D (U ^a _y)-d (U ^t _w)-(1 _q)+(1 _q)-d (U ^q _w)=D (U ^a _y)-d (U ^td _w)+(1 _q)-d (U ^q _w)=D (U ^s _y)+(1 _q)-d (U ^q _w), by analog quantity, expressing is U ^b _y-U ^s _y=2 ^qΔ-U ^q _wso, as long as by 2 ^qΔ-U ^q _wjust measure and can complete U ^b _yaD conversion, for this reason, antithesis chain is according to anticipation digital quantity D (U ^s _y) preset Dual switch, obtain main chain anticipation combined potential V ^s _y=U ^a _y-U ^td _w; Should be noted that, be to have a mind to allow anticipation amount sink 2 here ^qΔ, is beneficial to the convenience of refinement measured value;

The 3rd step, asks correction accurate measurement value D (U ^b _y-V ^s _y), by (q-1)～0 accurate measurement deserializer BXQ _qobtain U ^b _y-V ^s _yaD conversion value; Deserializer BXQ _qbetween major-minor resistance chain, from the angle of current potential, deserializer BXQ _qto stand on the shoulder of main chain, so, the preset combined potential V of main chain obtained ^s _yafter, U ^b _yhigher than V ^s _ypart can be less than the quantization unit 2 of bigness scale value ^qΔ，Gai mantissa is by BXQ _qbe responsible for conversion;

Work as u _wfor timing, U ^b _y-V ^s _y=U ^q _w, because U ^q _w< 2 ^qΔ, so use deserializer BXQ _qjust can complete U ^q _waD conversion, obtain D (U ^b _y-V ^s _y)=d (U ^q _w)=(d _q-1... d ₀);

Work as u _wwhen negative, U ^b _y-U ^s _y=2 ^qΔ-U ^q _w, because U ^q _w< 2 ^qΔ, 2 ^qΔ > 2 ^qΔ-U ^q _w> 0, so use BXQ _qjust can complete 2 ^qΔ-U ^q _waD conversion, obtain D (U ^b _y-V ^s _y)=(1 _q)-d (U ^q _w)=(d _q-1... d ₀);

The 4th step, asks D (U ^b _y), by above step, obtained respectively D (V ^s _y) and D (U ^b _y-V ^s _y)=(d _q-1... d ₀), then can obtain D (U through arithmetic unit YSQ ^b _y)=D (V ^s _y)+(d _q-1... d ₀), thereby complete U ^b _yaD conversion; Certainly, this D (U ^b _y) in the conversion of next cycle, be again as D (U ^a _y) occur;

Fig. 3 .2---category-B N position anticipation formula antithesis chain analog to digital converter schematic diagram

Before explained have: 2 ⁰r～2 ^n-1r; S ₀～S _n-1; 2 ⁰r '～2 ^n-1r ';

v _y; QZDL; CB; ZFP _x; D _x; LOG; u _i; u _g; U _g; U _y1; U _y0; V ' _nr; YSQ; R _q～R ₁; V _q-1～V ₁; B _q-1～B ₁; BMQ _q; (d _q-1... d ₀); BXQ _t; R ' _t-1～R ' ₁; R ' _t; V ' _t-1～V ' ₁; B ' _t-1～B ' ₁; BMQ _t; (d ' _t-1... d ' ₀); CB _w; ∑ _w; u _w; ZFP _w; D ' _q; U _w; Y _x; ∑ _y; Need having of explanation: anticipation summer ∑ ' _y; Anticipation exchanges error u _z; The positive and negative arbiter ZFP of anticipation error _z; Anticipation error polarity register D _z; Anticipation Error Absolute Value (abbreviation is sentenced poor) U _z; Category-B (q-1)～0 accurate measurement deserializer BXQ ' _q; FD _qfor sentencing poor amplifier; U _zqsentence poor value of magnification;

Embodiment 3.2---category-B N position anticipation formula antithesis chain analog to digital converter (Fig. 3 .2)

This embodiment is identical with operation principle, the first step, the second step of embodiment 3.1, only the difference of the 3rd step, the 4th step is described here;

The 3rd step, asks correction accurate measurement value D (U ^b _y-V ^s _y), anticipation summer ∑ ' _yto U ^b _yand V ^s _ycarry out summation operation, obtain anticipation error and keep u _z=U ^b _y-V ^s _y, the positive and negative arbiter ZFP of anticipation error _zanticipation error polarity is stored in to register D _z, and will have the u of polarity _zchange into and sentence poor U _z, because U ^b _ywith V ^s _ydistance can be less than the quantization unit 2 of bigness scale value ^qΔ, so sentence poor U _zscope be (0～2 ^qthen use amplifier FD Δ), _qto sentence poor U _zbe enlarged into and sentence poor value of magnification U _zq, value of magnification U _zqscope be (0～V _⊕; V _⊕=2 ^g+t+qΔ), by accurate measurement deserializer BXQ ' _qobtain U _zqaD conversion value (d _q-1... d ₀);

Also can be by accurate measurement deserializer BXQ ' _qdirectly obtain U _zaD conversion value (d _q-1... d ₀);

The 4th step, asks D (U ^b _y), by above step, obtained respectively D (V ^s _y) and (d _q-1... d ₀), then can obtain D (U through arithmetic unit YSQ ^b _y)=D (V ^s _y)+(d _q-1... d ₀), thereby complete U ^b _yaD conversion;

The sub-DOADC of Figure 43 level adds the pipeline system DOADC schematic diagram of final stage deserializer

Symbol and the function explained have: QZDL, CB; ZFP _x; D _x; LOG; u _i; u _g; U _g; U _y1; CB _α; U _y0; V ' _nr; Y _x; Need having of explanation: Fig. 4 is the E class ADC of 3 grade of * 4 seat DOADC+4 parallel-by-bit device; E _α, E _β, E _γbe respectively α level, β level, the sub-DOADC of γ level; Make φ wildcard α, β, γ, δ ..., U _{γ φ}be abbreviated as U _φ, U _φfor the tested voltage of φ level; V _{y φ}be abbreviated as V _φ, V _φbe respectively φ level counterweight voltage; B _φfor φ level comparator; h _φfor φ level comparison value; Dotted line frame KGKZ _φfor φ level on-off controller; S _f～S _c, S _b～S ₈, S ₇～S ₄be respectively α level, β level, γ level main chain digital switch;

be respectively α level, β level, the secondary chain digital switch of γ level; D _f～D _c, D _b～D ₈, D ₇～D ₄be respectively α level, β level, γ stages of digital signal; 2 ^fr～2 ^cr, 2 ^br～2 ⁸r, 2 ⁷r～2 ⁴r is respectively α level, β level, γ level main chain power resistance; 2 ^fr '～2 ^cr ', 2 ^br '～2 ⁸r ', 2 ⁷r '～2 ⁴r ' is respectively α level, β level, the secondary chain power of γ level resistance; Dotted line frame JJZH _bfor category-B inter-stage transducer, comprise its voltage mantissa summer ∑ _b, the amplifier A of mantissa _b, mantissa adopts and protects device CB _b, stray voltage summer ∑ _b1; Dotted line frame JJZH _cfor C class inter-stage transducer, comprise its voltage mantissa summer ∑ _c, the amplifier A of mantissa _c, mantissa adopts and protects device CB _c; Dotted line frame JJZH _dfor D class inter-stage transducer, comprise its voltage mantissa summer ∑ _d, the amplifier A of mantissa _d, mantissa adopts and protects device CB _d; U _{β 2}, U _{δ 2}be respectively the 2nd grade, the 4th grade front step voltage mantissa receiving; U _b1, U _{δ 1}be respectively U _{β 2}, U _{δ 2}value of magnification; U _{β 0}, U _{δ 0}be respectively U _{β 1}, U _{δ 1}adopt value preserving; V _{γ r}scaled value for γ level stray voltage; U _{γ 4}the front step voltage mantissa of the scaled value that comprises stray voltage receiving for 3rd level; ∑ _{β 1}for stray voltage summer; The sub-ADC of δ level is E _δfor deserializer, comprise [chain resistance R _f～R ₁; Reference potential V _f～V ₀; Comparator B _f～B ₁; Encoder BMQ _δ; Digital quantity (d ₃... d ₀); ]; δ level clean voltage U to be measured _{δ 0};

Embodiment 4.1---and the sub-DOADC of m level adds the pipeline system DOADC of final stage deserializer.Be called for short E class ADC

This example is the pipeline system DOADC that the sub-DOADC of m level adds final stage deserializer because will avoid the confusion of label, special by the 1st,, 2,3,4 ... α, β, γ, δ for level ... level represents; Sub-DOADC is labeled as E _α, E _β, E _γ, E _δ, the operation principle of every grade of sub-DOADC is identical with basic DOADC's, and the conversion figure place of every sub-DOADC all equals n, and final stage is a n _qthe deserializer of position, so the total bit N=m*n+n of E class ADC _q, from high to low, the 1st grade of (α level) major-minor power resistance weights are (2 to figure place ^n-1～2 ^n-n), same, the 2nd grade of weights are (2 ^n-n-1～2 ^n-2*n) ..., s level weights are (2 ^{n-(s-1) * n-1}～2 ^n-s*n), Due at different levels be all concurrent working, so the cycle of the each sample conversion of this ADC is n+1 cp pulse; Because drawn, the space of a whole page limits, and Fig. 4 has only drawn the E class ADC of 3 grades * 4+4;

Front end circuit QZDL is by u _iconvert clean measured signal U to _y1, because CB _αthe virtual guarantor's of adopting device, so U _y0=U _y1, by adder ∑ _yobtain α level measured signal U _α=U _y0+ V ' _nr; With basic model, DOADC is the same, and the sub-DOADC of α level is E _αto U _αcarry out AD conversion, obtain the 1st grade of power resistance (2 ^n-1r～2 ^n-nr) access-remove relation, thus the digital signal (D of the 1st grade obtained _n-1～D _n-n) and the 1st grade of counterweight voltage V _α;

In Fig. 4, the 2nd grade has adopted category-B inter-stage transducer JJZH _b, the JJZH of the 2nd grade _bthe U receiving _α, V _αthrough voltage mantissa summer ∑ _bobtain U _{β 2}=U _α-V _α, because the 1st grade of minimum counterweight voltage is 2 ^n-nr*I, so U _{β 2}< 2 ^n-nr*I, U _{β 2}through the amplifier A of mantissa _bamplify 2 ⁿdoubly, obtain U _{β 1}, make U _{β 1}excursion and U _αidentical, U _{β 1}through mantissa, adopt and protect device CB _bafter obtain voltage U fixing within the sampling period _{β 0}, Here it is tested clean voltage, U _{β 0}through stray voltage summer ∑ _b1obtain the tested voltage U of β level _β=U _{β 0}+ V ' _nr, V ' wherein _nr=V _nr, balance out the dead resistance in main chain; With basic model, DOADC is the same, E _βby U _βcarry out after AD conversion, obtain the 2nd grade of power resistance (2 ^n-n-1r～2 ^n-2*nr) access-remove relation, thus the digital signal (D of the 2nd grade obtained _n-n-1～D _n-2*n) and the 2nd grade of counterweight voltage V _β; The 2nd grade of sub-DOADC is E _β

In Fig. 4,3rd level has adopted C class inter-stage transducer JJZH _c, the JJZH of 3rd level _cthe U receiving _β, V _βthrough voltage mantissa summer ∑ _cobtain U _{γ 4}=U _β+ V _{γ r}-V _β, V wherein _{γ r}=V _nr/ 2 ⁿ, JJZH _cby balancing out the operation of dead resistance in main chain, give ∑ _cdo, thereby by JJZH _bsaved stray voltage summer ∑ _b1; JJZH _cand JJZH _bbe equivalent, can exchange; Because the 2nd grade of minimum counterweight voltage is 2 ^n-2*nr*I, so U _{γ 4}< 2 ^n-2*nr*I, U _{γ 4}through the amplifier A of mantissa _camplify 2 ⁿdoubly, obtain U _{γ 3}, make U _{γ 3}excursion and U _αidentical, U _{γ 3}through mantissa, adopt and protect device CB _cafter obtain the tested voltage U of γ level _γ; With basic model, DOADC is the same, E _γby U _γcarry out after AD conversion, obtain 3rd level power resistance (2 ^n-2*n-1r～2 ^n-3*nr) access-remove relation, thus the digital signal (D of 3rd level obtained _n-2*n-1～D _n-3*n) and 3rd level counterweight voltage V _γ;

In Fig. 4, final stage has adopted D class inter-stage transducer JJZH _d, the JJZH of the 4th grade _dthe U receiving _γ, V _γthrough voltage mantissa summer ∑ _dobtain U _{δ 2}=U _γ-V _γ, because the minimum counterweight voltage of 3rd level is 2 ^n-3*nr*I, so U _{δ 2}< 2 ^n-3*nr*I, U _{δ 2}through the amplifier A of mantissa _damplify 2 ⁿdoubly, obtain U _{δ 1}, make U _{δ 1}excursion and U _αidentical, U _{δ 1}through mantissa, adopt and protect device CB _dafter obtain the tested clean voltage U of δ level _{δ 0}, because final stage employing is deserializer, there is not dead resistance problem, so directly by U _{δ 0}carry out AD conversion, obtain the digital signal (D of final stage _n-3*n-1～D _n-4*n)=(D _n-1～D ₀).

Embodiment 4.2---the pipeline system DOADC of the sub-DOADC of m level.Be called for short F class ADC

This example is the pipeline system DOADC of the sub-DOADC of m level, changes the final stage of embodiment 4.1 into sub-DOADC.

The pipeline system GADC of Fig. 5---4 grade of 3 parallel-by-bit device+DODAC.Be called for short G class ADC or GADC

Symbol and the function explained have: QZDL, CB; ZFP _x; D _x; LOG; u _i; u _g; U _g; U _y1; CB _α; V _nr; Y _x; Need having of explanation: G _φbe the sub-GADC of φ level; G _φin deserializer BXQ _{g φ}comprise [chain resistance R _{φ 7}～R _φ ₀; Reference potential V _{φ 7}～V _{φ 0}; Comparator B _{φ 7}～B _{φ 1}; Encoder BM _φ; Digital quantity (D _{φ 2}d _{φ 1}d _{φ 0})]; DODAC _φbe exactly the N position antithesis chain type digital to analog converter described in embodiment 1.1, with Fig. 1 .2 graphical diagram, represent R _{y φ}for main chain, R ' _{y φ}for secondary chain, V _φfor main chain combined potential; Interstage circuit comprises [to be adopted and protects device CB _{g φ}; Summing amplifier ∑ _{g φ}]; U _{φ 3}be the input voltage (being exactly prime mantissa voltage) of φ level, U _{φ 0}for clean tested voltage;

Embodiment 5---the pipeline system GADC of m level n parallel-by-bit device+DODAC.Be called for short G class ADC or GADC

GADC is by m sub level G _φform sub level G _φn parallel-by-bit device, n position DODAC and interstage circuit three parts, consist of, final stage only has n parallel-by-bit device and Cai Bao device; α level measured signal U _{α 0}zong be exactly measured signal has jointly been tested AD by m GADC sub level and has been changed, each sub level conversion n position (D _{φ (n-1)}/ D _{φ (n-2)}/ ... / D _{φ 1}/ D _{φ 0}), because data acquisitions at different levels are protected rear concurrent working, so identical with full parallel model ADC speed; Make (φ+1) for example, for the rear one-level of φ: when φ=β, (φ+1)=γ; U _{(φ+1) 3}being φJi mantissa voltage, is also (φ+1) level input voltage; Transfer process is as follows:

1. front end circuit QZDL is by u _iconvert advance signal U to _y1, for the purpose of numbering unification, by U _y1change and be designated as U _{α 3};

2. m GADC sub level synchronously carries out this section of operation.For φ level, adopt and protect device CB _{g φ}to input voltage U _{φ 3}the clean measured signal U obtaining after sampling _{φ 0}in a maintenance phase, the U of current sampling _{φ 0}equal the U of a sampling _{φ 3}; G _φdeserializer BXQ _{g φ}by U _{φ 0}convert digital signal (D to _{φ (n-1)}/ D _{φ (n-2)}/ ... / D _{φ 1}/ D _{φ 0}) after, this Digital Signals DODAC _φobtain φ level main chain combined potential V _φ=V _{φ 0}+ V _nr, through summing amplifier ∑ _{g φ}after computing, obtain offsetting stray voltage Hou mantissa voltage U _{(φ+1) 3}=2 ⁿ(U _{φ 0}+ V ' _nr-V _φ)=2 ⁿ(U _{φ 0}-V _{φ 0}), φJi mantissa voltage U _{(φ+1) 3}offer (φ+1) level as input voltage; When next sampling pulse arrives, through adopting, protect device CB _{g (φ+1)}after, U _{(φ+1) 3}become the clean tested voltage U of (φ+1) level _{(φ+1) 0};

Wherein final stage GADC does not have DODAC _φand ∑ _{g φ}so its simplified control is G _φbXQ _{g φ}by U _{φ 0}convert digital signal (D to _{φ (n-1)}/ D _{φ (n-2)}/ ... / D _{φ 1}/ D _{φ 0});

3. certain tested voltage U _{α 0}it is exactly U that the digital signal of changing through m level links up _{α 0}complete AD conversion value.

Embodiment 6---digital and analog log law compression

At seniority top digit ADC, analog signal is converted to after the digital signal of seniority top digit, by digital log law compression module, the digital signal of seniority top digit is compressed into the digital signal of lower-order digit; Workflow is as follows:

Digital log law companding: the accurate logarithmic quantization digital signal → transmission → transmission of analog voltage → AD conversion → high-order (such as 18) uniform quantization digital signal → log law quantizing encoder → low level (such as 7) → ... → acceptance → low level logarithmic quantization digital signal → log law quantization decoding device → high-order uniform quantization digital signal → DA conversion → analog voltage;

Analog log law companding: analog voltage → log law compression → log law analog voltage → AD conversion → accurate logarithmic quantization digital signal → transmission → transmission → ... → acceptance → accurate logarithmic quantization digital signal → DA conversion → log law analog voltage → antilogarithm rule expansion → analog voltage.Simulation logarithmic compression law module LOG is the option in front end circuit.

Claims

1. power voltage-type ADC and the DAC based on antithesis power resistance chain, is characterized in that: comprise antithesis power resistance chain, the total antithesis resistance chain of its apparent is in series by apparent main resistor chain NR and the secondary resistance chain NR ' of apparent, and apparent main resistor chain NR is by resistance 2 with sovereign right ⁰r～2 ^n-1r is in series, and the secondary resistance chain NR ' of apparent is by pair power resistance 2 ⁰r '～2 ^n-1r ' is in series, the major and minor resistance that in major and minor apparent resistance chain, weights j equates, 2 ^jr and 2 ^jr ' is the antithesis power resistance that a pair of resistance is equal; Each power resistance digital switch by Digital Signals in parallel; 2 ^jr digital switch S in parallel _j, by digital signal D _jcontrol; 2 ^jr ' digital switch in parallel

by digital signal

control; Make S _jwith for reciprocal Dual switch, i.e. S _jwith

in always have a conducting and another cut-off, so antithesis resistance always one access one remove, make major and minor apparent resistance chain under Digital Signals, become the N bit digital formula adjustable resistor main chain R of a pair of complementation _ywith secondary chain R ' _y, work as R _ywhile becoming large, R ' _ydiminishing of equivalent, vice versa, so R _y+ R ' _ywith electric current I be steady state value, its main chain voltage is V _y=R _y* I; Digital-to-analogue conversion process is: Digital Signals Dual switch, thereby control in antithesis power resistance chain, weigh resistance, and make to weigh resistance (2 ^n-1r ..., 2 ⁰r) can access arbitrarily and remove, form power voltage, get rid of after stray voltage, only weigh voltage (2 ^n-1Θ * I ..., 2 ⁰Θ * I) can add and subtract arbitrarily, so main chain voltage V _y(2 ⁿΘ * I～0) scope is adjustable, quantization step Δ=Θ * I; Because this device is exported adjustable power voltage by Digital Signals, so be antithesis power resistance chain power voltage-type DAC; On the basis of this DAC, if adopt step-by-step method just to become the successively comparison A/D C based on antithesis power resistance chain, if adopt anticipation formula method to add deserializer structure, just become the anticipation formula ADC based on antithesis power resistance chain;

2. power voltage-type ADC and the DAC based on antithesis power resistance chain according to claim 1, its further feature is: the current source of connecting on resistance chain has just become general resistance chain, clearly agreement: all current source A in file _{⊕ Φ}and A _{▲ Φ}be option, the antithesis chain in all embodiment is all general resistance chain, has contained and has had current source formula antithesis chain, no current source formula antithesis chain and current source to add three kinds of main chain formula resistance chains; Near the anodal V of system _pseries current source A _{⊕ Φ}after, A _{⊕ Φ}the voltage of the other end is V _{⊕ Φ}, claim V _{⊕ Φ}for sub-anodal, if do not adopt current source A _{⊕ Φ}, anodal V _pwith the anodal V in Asia _{⊕ Φ}merging and general; Equally, near system power supply ground

realize DA conversion.

3. power voltage-type ADC and the DAC based on antithesis power resistance chain according to claim 1, its further feature is: a kind of N position antithesis power resistance chain type digital to analog converter DODAC; By DODAC basic principle, constructed: S level * n position antithesis power resistance chain type digital to analog converter, adopt unified modularized design, make DODAC at different levels _Φfigure place n _Φall equal n; At Φ level DODAC _Φin, DODAC _Φby main chain 2 ⁰r _Φ～2 ^n-1r _Φwith secondary chain 2 ⁰r _Φ'～2 ^n-1r _Φ' connect and formation antithesis chain, the order of Φ level subchain series connection is: ground → main chain → secondary chain → chain voltage V _{⊕ Φ}; Because chain electric current I _Φfixing, so as long as Φ stages of digital signal has been determined Φ level DODAC _Φthe access of all resistance with sovereign right and removing after state, has just obtained main chain total voltage

through voltage follower GS, improve V _{y Φ}load capacity; Ratio reducer Ψ _{y Φ}by main chain total voltage V _{y Φ}with secondary output voltage V ' _{y (Φ+1)}) phase adduction reduction 2 ⁿdoubly just become Φ level output voltage V ' _{y Φ}, that is: V ' _{y Φ}=(V _{y Φ}+ V ' _{y (Φ+1)})/2 ⁿ; If make V " _{y Φ}for V _{y Φ}to the voltage of total output, so V _{y Φ}to V " _{y Φ}to pass through (Φ-1) individual ratio reducer, so V " _{y Φ}=V _{y Φ}/ 2 ^{(φ-1) * n}; At total summer ∑ _zin; Dac value V _y0+ V _{∑ r}=V _{y α}+ V ' _{y β}=V _{y α}+ V " _{y β}+ V " _{y γ}+ V " _{y δ}total stray voltage V _{∑ r}be a constant, make output valve move on the whole V _{∑ r}, also can ignore; Clean power resistance has two kinds of structures, and a kind of is single resistance-type, and a kind of is 2 ^jindividual reference resistance series connection.

4. power voltage-type ADC and the DAC based on antithesis power resistance chain according to claim 1, its further feature is: a kind of successively type N position antithesis power resistance chain type analog to digital converter operation principle relatively; Digital Signals Dual switch, can obtain main chain total voltage

trying to achieve of digital signal is to rely on described logical circuit below; Comparator Ba is exactly an electronic balance, tested voltage U _ybe connected to the in-phase end of Ba, keeping phase U _ystable, U _y=U _y0+ V ' _nr, V ' _nrin order to offset dead resistance V _nrimpact, end of oppisite phase V _yvoltage counterweight, be in U _yamount relatively and in adjustment process, V _y=V _y0+ V _nr, U _ywith V _yby comparator Ba comparison, obtain comparison value h, work as U _y> V _ytime h=1, need to increase voltage counterweight, work as U _y< V _ytime h=0, need to reduce voltage counterweight; Note V _ybeing a dynamic value, is one group of counterweight, as weighing voltage in the balance, takes counterweight examination one by one, determines that it is to stay or to take away that examination adds counterweight, so V _ybe that quantization changes, claim to be determined going or staying to minimum quantum counterweight Δ always, cannot be again toward calling in the following text, final definite V _y0be regarded as the weight U of voltage _y0, full text V _y=U _ybe the concept in measuring accuracy, | V _y-U _y| < Δ; With electronic balance Ba, claim tested voltage U _yvalue, by on-off controller, examination voltage counterweight one by one, along with cp pulse, by resistance 2 with sovereign right ^jr is by 2 ^n-1r～2 ⁰the order of R one by one serve as the resistance of trying, when 2 ^jr serves as while trying resistance, if h=1 illustrates that this electricity counterweight adds that rear total voltage does not surpass U _y, by on-off controller, make digital register signal D _j=1, D _j=1 by 2 ^jr is defined as accessing resistance; If h=0, illustrates that this electricity counterweight adds that rear total voltage surpasses U _y, by on-off controller, make digital register signal D _j=0, D _j=0 by 2 ^jr is defined as removing resistance; When 2 ^n-1r～2 ⁰after R is all determined, U _ybe converted into digital signal D _n-1... D ₁d ₀thereby, realized AD conversion;

Successively relatively the circuit theory of type N position antithesis power resistance chain type analog to digital converter is:

Each cp pulse only can trigger DG ₀～DG _n-1one of them, h ' puts number to it;

there is negative saltus step, because

received DG _n-1s _gend, and received DG _n-2～DG ₀r _gend, institute is so that D _n-1=1 and D _n-2～D ₀=0, this group Digital Signals antithesis chain, only accessing the resistance of trying is 2 ^n-1r, now main chain total voltage meanwhile, Y _xpositive transition is the instruction that makes CB sampling, known from foregoing front end circuit QZDL and ∑, obtains tested direct current signal U _y=U _y0+ V ' _nr; Next be the calculating process of h ', that is: by comparator Ba, compare U _ywith V _ysize, obtain comparison value h and equal 0 or 1, if V _y< U _y, h=1, if V _y> U _y, h=0; Next the negative saltus step of cp, trigger DH is the d type flip flop that trailing edge triggers, so it is temporary that h is delivered to the output h ' of DH; H ' is connected to DG ₀～DG _n-1d end, prepare to put number; The 0th pulse is called " priming pulse ", makes ADC complete the preparation of current sampled signal being carried out to AD conversion: access the resistance 2 of trying ^n-1r also makes DY _n-1in D=1; Ensuing the 1st transfer process to N pulse is following cyclic process:

During j=0, i.e. somewhat special during N pulse, DY ₀'s

for unsettled useless, Y ₀=1 delivers to DY _xd end, get back to ▲ locate, start the 0th pulse in new cycle, for the next one sampling-AD change-over period prepares;

5. power voltage-type ADC and the DAC based on antithesis power resistance chain according to claim 1, its further feature is: G D-flip flop operation principle; G D-flip flop is developed by D flip-flop, DY _jfor D flip-flop; In d type flip flop, S _dfor low level, put 1 end, work as S _d=0, output D _junconditionally put 1; R _dfor low level sets to 0 end, work as R _d=0, output D _junconditionally set to 0; D is data input pin, and cp end is for trigger end, at the S that satisfies condition _d=1 and R _dunder=1 prerequisite, when trigger impulse arrives, the data of D end are sent to D _jend; And G D-flip flop and d type flip flop are different, S _gfor negative saltus step, put 1 end, only work as S _gthere is negative saltus step moment in end, makes output D _jput 1, if not the moment in negative saltus step, even if S _g=0, can be to output valve D yet _jexert an influence, its circuit theory is: work as S _g=1 o'clock C ₂high potential 1 is all received at two ends, so C ₂middle steady state voltage is 0, at this moment S _d=1, to DY _joutput valve without impact; Work as S _gjump at 0 o'clock by 1, due to C ₂voltage can not suddenly change, so this moment S _d=0, but because SR end is high potential 1, form charge circuit SR → R ₂→ C ₂→ S _gto C ₂charging, charge constant τ=R ₂* C ₂, C after 3 τ ₂be full of 95%, make S _d=1, design makes τ very little, so only at S _gby 1, jump to 0 moment S _d=0, make output D _junconditionally put 1; In like manner, R _gfor negative saltus step sets to 0 end, only work as R _gthere is negative saltus step moment in end, makes output D _jset to 0, if not the moment in negative saltus step, even if R _g=0, can be to output valve D yet _jexert an influence; At the S that satisfies condition _gand R _gall do not have to occur under the prerequisite of negative saltus step, when trigger impulse arrives, the data of D end are sent to D _jend;

6. power voltage-type ADC and the DAC based on antithesis power resistance chain according to claim 1, its further feature is: category-A N position anticipation formula antithesis chain analog to digital converter operation principle: this ADC is by the position bigness scale deserializer BXQ of N position antithesis chain, q～(q+t-1) _t(q-1)～0 accurate measurement deserializer BXQ _qthree grades of compositions; N position is divided into three sections: the high-order g position (D of section of foundation _g+t+q-1... D _t+q), bigness scale section meta t position (D _t+q-1... D _q) and accurate measurement section low level q position (D _q-1... D ₀); Known corrections amount u _w=U ^b _y-U ^a _y, suppose that sampling density is higher, guarantee to make correction u _wcorresponding digital variable quantity < 2 ^t+q, so, as long as to correction u _wcarry out AD conversion and can obtain complete AD conversion, for this reason, with bigness scale deserializer BXQ _tto correction u _wcarry out bigness scale, by the digital quantity after bigness scale and Contemporary Digital amount V ^a _ybe added, obtain U ^b _yanticipation digital quantity V ^s _y, at V ^s _ybasis on carry out accurate measurement; Suppose and obtain current amount U ^a _yaD conversion D (V ^a _y)=(D ^a _n-1d ^a _n-2... D ^a ₁d ^a ₀), this example is treated and is turned voltage U ^b _yan AD conversion minute following step:

7. power voltage-type ADC based on antithesis power resistance chain according to claim 1 and DAC and according to category-A N position anticipation formula antithesis chain analog to digital converter according to claim 6, its further feature is: on the basis of category-A N position anticipation formula antithesis chain analog to digital converter, construct category-B N position anticipation formula antithesis chain analog to digital converter, the first step, second step are identical with category-A N position anticipation formula antithesis chain analog to digital converter;

8. power voltage-type ADC and the DAC based on antithesis power resistance chain according to claim 1, its further feature is: the pipeline system GADC of a kind of m level n parallel-by-bit device+DODAC; GADC is comprised of m sub level, defines last sub level and claims final stage GADC, and other sub level claims sub-GADC, and GADC sub level comprises final stage GADC and sub-GADC; Every sub-GADC is comprised of n parallel-by-bit device, n position DODAC and interstage circuit three parts, and final stage only has n parallel-by-bit device and Cai Bao device; α level measured signal U _{α 0}zong be exactly measured signal has jointly been tested AD by m GADC sub level and has been changed, each sub level conversion n position (D _{φ (n-1)}/ D _{φ (n-2)}/ ... / D _{φ 1}/ D _{φ 0}), due at different levels be all concurrent working, so the cycle of the each sample conversion of GADC is identical with the change-over period of a sub-GADC, identical with full parallel model ADC speed; Transfer process is as follows:

1. front end circuit QZDL is by u _iconvert advance signal U to _y1,

2. m GADC sub level synchronously carries out this section of operation.For φ level, adopt and protect device CB _{g φ}to input voltage U _{φ 3}the clean measured signal U obtaining after sampling _{φ 0}in a maintenance phase, the U of current sampling _{φ 0}equal the U of a sampling _{φ 3}; G _φdeserializer BXQ _{g φ}by U _{φ 0}convert digital signal (D to _{φ (n-1)}/ D _{φ (n-2)}/ ... / D _{φ 1}/ D _{φ 0}) after, this Digital Signals DODAC _φobtain φ level main chain combined potential V _φ=V _{φ 0}+ V _nr, through summing amplifier ∑ _{g φ}after computing, obtain offsetting stray voltage Hou mantissa voltage U _{ψ 3}=2 ⁿ(U _{φ 0}+ V ' _nr-V _φ)=2 ⁿ(U _{φ 0}-V _{φ 0}), φJi mantissa voltage U _{ψ 3}offer ψ level as input voltage; When next sampling pulse arrives, through adopting, protect device CB _{g ψ}after, U _{ψ 3}become the clean tested voltage U of ψ level _{ψ 0};

3. digital signals at different levels chronologically relation to link up be exactly complete AD conversion value.

9. power voltage-type ADC and the DAC based on antithesis power resistance chain according to claim 1, its further feature is: a kind ofly based on N bit digital formula adjustable resistor, construct a kind of mixed digital-analogue multiplier; A traditional differential amplifier circuit, makes R _c1=R _c2=R _c3=R _c4, R _cz=R _cF, at this moment differential amplifier circuit summation is amplified pass and is: U _out(R _cF/ R _c1) (u ₁-u ₂+ u ₃+ u ₄); If by digital signal Synchronization Control N bit digital formula adjustable resistor R _czand R _cFsize, just changed multiplication factor, become with input signal the relation multiplying each other.

10. power voltage-type ADC and the DAC based on antithesis power resistance chain according to claim 1, its further feature is: digital and analog log law pressure texture;

Digital log law companding: the digital signal → transmission → transmission of analog voltage → AD conversion → high-order uniform quantization digital signal → log law quantizing encoder → low level logarithmic quantization → ... → acceptance → low level logarithmic quantization digital signal → log law quantization decoding device → high-order uniform quantization digital signal → DA conversion → analog voltage;

Analog log law companding: analog voltage → log law compression → log law analog voltage → AD conversion → accurate logarithmic quantization digital signal → transmission → transmission → ... → acceptance → accurate logarithmic quantization digital signal → DA conversion → log law analog voltage → antilogarithm rule expansion → analog voltage; Simulation logarithmic compression law module LOG is the option in front end circuit.