KR20000004533A - Method for manufacturing a storage electrode of semiconductor devices - Google Patents

Method for manufacturing a storage electrode of semiconductor devices Download PDF

Info

Publication number
KR20000004533A
KR20000004533A KR1019980025977A KR19980025977A KR20000004533A KR 20000004533 A KR20000004533 A KR 20000004533A KR 1019980025977 A KR1019980025977 A KR 1019980025977A KR 19980025977 A KR19980025977 A KR 19980025977A KR 20000004533 A KR20000004533 A KR 20000004533A
Authority
KR
South Korea
Prior art keywords
manufacturing
film
storage electrode
semiconductor device
charge storage
Prior art date
Application number
KR1019980025977A
Other languages
Korean (ko)
Inventor
김경민
박기선
Original Assignee
김영환
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대전자산업 주식회사 filed Critical 김영환
Priority to KR1019980025977A priority Critical patent/KR20000004533A/en
Publication of KR20000004533A publication Critical patent/KR20000004533A/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A fabrication method of a storage electrode is provided to reduce a leakage current and improve a reliability of devices by using a TaN layer having oxidative tolerance and thermal stability as an upper electrode. CONSTITUTION: The method comprises the steps of forming an interlayer dielectric(11) on a semiconductor substrate having a lower electrode(13); performing an RTN(rapid thermal nitrization) of the lower electrode(13) to form a RTN film(15) on the surface of the lower electrode; forming a dielectric layer(17) made of Ta2O5 on the RTN film(15); performing N2O plasma treatment of the dielectric layer(17); annealing the dielectric layer(17); and forming a TaN film(19) used as an upper electrode on the dielectric layer(17).

Description

반도체소자의 전하저장전극 제조방법Method for manufacturing charge storage electrode of semiconductor device

본 발명은 반도체 소자의 전하저장전극 제조방법에 관한 것으로, 특히 고유전율의 특성을 갖는 Ta2O5막을 유전체막으로 사용하는 반도체소자에 있어서, 내산화성과 열적 안정성이 우수한 TaN막을 상부전극으로 사용함으로써 누설전류를 감소시키고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a charge storage electrode of a semiconductor device. In particular, in a semiconductor device using a Ta 2 O 5 film having high dielectric constant as a dielectric film, a TaN film having excellent oxidation resistance and thermal stability is used as an upper electrode. The present invention relates to a technology for reducing leakage current and thereby improving characteristics and reliability of semiconductor devices.

일반적으로, 고유전 특성의 Ta2O5막을 유전체막으로 이용하여 전하저장전극를 제조하는 경우 누설전류 등의 전기적 특성이 저하되고 후속 공정의 고온 열처리 공정에서 열화되어 유전율이 감소되는 것을 방지하기 위해 다결정실리콘막/TiN/Ta2O5의 이중전극 구조의 전하저장전극을 사용하고 있으나, 600℃ 이상의 고온공정에서 상기 TiN막과 Ta2O5막 중의 산소가 반응하여 산화된 TiON을 형성한다. 또한, Ta2O5막의 Ta가 TiN막중으로 확산되고, 상기 TiN막의 Ti가 Ta2O5막 내로 확산되고, 상기 Ta2O5막내의 산소가 결핍되어 상기 Ta2O5막의 막질이 열화됨으로써 누설전류가 증가하게 되는 문제점이 있다.In general, in the case of manufacturing a charge storage electrode using a Ta 2 O 5 film having a high dielectric property as a dielectric film, a polycrystal is used to prevent electrical properties such as leakage current from deteriorating and deterioration in high temperature heat treatment in a subsequent process. Although a charge storage electrode having a double electrode structure of silicon film / TiN / Ta 2 O 5 is used, oxygen in the TiN film and Ta 2 O 5 film reacts to form oxidized TiON in a high temperature process of 600 ° C. or higher. Further, by being spread to the Ta 2 O 5 film, Ta is TiN film, the TiN film, Ti is diffused into the Ta 2 O 5 film, and said Ta 2 O 5 film, the film quality deterioration of the oxygen of the Ta 2 O 5 N deficient There is a problem that the leakage current increases.

본 발명은 상기한 문제점을 해결하기 위하여, Ta2O5을 유전체막으로 사용하는 반도체소자에서 TaN막을 상부전극으로 사용함으로써 소자의 전기적 특성을 향상시키는 반도체소자의 전하저장전극 제조방법을 제공하는 데 그 목적이 있다.The present invention provides a method of manufacturing a charge storage electrode of a semiconductor device to improve the electrical characteristics of the device by using a TaN film as an upper electrode in a semiconductor device using Ta 2 O 5 as a dielectric film to solve the above problems. The purpose is.

도 1 내지 도 3 은 본 발명에 따른 반도체소자의 전하저장전극 제조방법을 도시한 단면도.1 to 3 are cross-sectional views showing a method for manufacturing a charge storage electrode of a semiconductor device according to the present invention.

◈ 도면의 주요부분에 대한 부호의 설명◈◈ Explanation of symbols for the main parts of the drawing

11 : 층간절연막 13 : 하부전극11 interlayer insulating film 13 lower electrode

15 : RTN막 17 : 유전막15: RTN film 17: dielectric film

19 : 상부전극19: upper electrode

상기 목적을 달성하기 위해 본 발명에 따른 반도체소자의 전하저장전극 제조방법은,Method for manufacturing a charge storage electrode of a semiconductor device according to the present invention to achieve the above object,

소정의 하부구조물이 형성된 반도체기판 상부에 하부전극이 구비된 층간절연막을 형성하는 공정과,Forming an interlayer insulating film having a lower electrode on the semiconductor substrate on which the predetermined lower structure is formed;

상기 하부전극 상부를 RTN처리하는 공정과,RTN processing the upper portion of the lower electrode,

전체표면 상부에 Ta2O5막으로 유전막을 형성하는 공정과,Forming a dielectric film on the entire surface with a Ta 2 O 5 film;

상기 유전막 상부에 상부전극용 TaN막을 형성하는 공정을 포함하는 것을 특징으로 한다.And forming a TaN film for an upper electrode on the dielectric film.

이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 전하저장전극 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a charge storage electrode of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 1 내지 도 3 은 본 발명에 따른 반도체소자의 전하저장전극 제조방법에 의해 형성된 전하저장전극을 도시한 단면도이다.1 to 3 are cross-sectional views showing a charge storage electrode formed by a method of manufacturing a charge storage electrode of a semiconductor device according to the present invention.

먼저, 반도체기판에 소자분리 절연막, 게이트 산화막을 형성하고, 게이트 전극 및 소오스/드레인영역을 구비하는 모스 트랜지스터를 형성한 다음, 비트라인 등의 하부구조물을 형성한 다음, 층간절연막(11)을 형성한다.First, a device isolation insulating film and a gate oxide film are formed on a semiconductor substrate, a MOS transistor having a gate electrode and a source / drain region is formed, a substructure such as a bit line is formed, and then an interlayer insulating film 11 is formed. do.

다음, 상기 모스 트랜지스터의 소오스/드레인영역에서 저장전극 콘택으로 예정되는 부분과 접속되는 하부전극(13)을 다결정실리콘층으로 형성하고, 그 표면을 불산(HF)나 비.오.이.(buffered oxide etchant, 이하 BOE 라 함)용액으로 식각하여 자연산화막을 제거한다.Next, a lower electrode 13, which is connected to a portion intended as a storage electrode contact in the source / drain region of the MOS transistor, is formed of a polysilicon layer, and the surface thereof is hydrofluoric acid (HF) or B. O. (buffered). oxide etchant (hereinafter referred to as BOE) to remove the native oxide film.

그 다음, 상기 하부전극(13) 표면을 800 ∼ 950 ℃에서 급속질화처리(rapid thermal nitride, 이하 RTN 이라 함)로 RTN막(15)을 형성하여 후속 산소분위기에서 열처리공정시 산화막의 형성을 억제한다. (도 1참조)Next, the RTN film 15 is formed by rapid thermal nitride (RTN) at 800 to 950 ° C. on the surface of the lower electrode 13 to suppress the formation of an oxide film during a heat treatment process in a subsequent oxygen atmosphere. do. (See Fig. 1)

다음, 상기 RTN막(15) 상부에 저압화학기상증착(low pressure chemical vapor deposition, 이하 LPCVD 라 함)방법으로 Ta2O5막으로 유전막(17)을 형성한다. 상기 유전막(17)은 탄탈륨 에칠레이트(Ta(OC2H5)5)를 170 ∼ 190 ℃로 유지되는 기화기에서 기상상태로 만든 후, 상기 탄탄륨 에칠레이트 0.001 ∼ 2.0 cc와 반응가스인 O2를 10 ∼ 1000 sccm 사용하고, 반응로 내의 압력은 0.1 ∼ 1.2 Torr로 유지하고, 350 ∼ 450 ℃로 가열된 웨이퍼에 탄탈륨 옥사이드(Ta2O5)를 증착한다. 그 후, 상기 Ta2O5막은 300 ∼ 500 ℃에서 RF 파워가 50 ∼ 400 W인 조건에서 N2O 플라즈마를 사용하여 어닐링한다.Next, a dielectric film 17 is formed on the RTN film 15 by using a Ta 2 O 5 film by low pressure chemical vapor deposition (LPCVD). The dielectric layer 17 is made of tantalum acrylate (Ta (OC 2 H 5 ) 5 ) in a gaseous state in a vaporizer maintained at 170 to 190 ° C., followed by 0.001 to 2.0 cc of tantalum acrylate and a reaction gas of O 2. 10 to 1000 sccm is used, the pressure in the reactor is maintained at 0.1 to 1.2 Torr, and tantalum oxide (Ta 2 O 5 ) is deposited on the wafer heated to 350 to 450 ° C. Thereafter, the Ta 2 O 5 film is annealed using an N 2 O plasma at 300 to 500 ° C. under a condition of an RF power of 50 to 400 W.

그 후, 750 ∼ 900 ℃에서 O2또는 N2O 가스 분위기의 로(furnace) 내에서 30 ∼ 60분간 어닐링하여 상기 Ta2O5막을 결정화시킨다. (도 2참조)Thereafter, the Ta 2 O 5 film is crystallized by annealing in a furnace in an O 2 or N 2 O gas atmosphere at 750 to 900 ° C. for 30 to 60 minutes. (See Fig. 2)

다음, 상기 유전막(17) 상부에 TaN 막으로 상부전극(19)을 형성한다. 상기 상부전극(19)은 실온에서 고체상태인 탄탈륨 클로라이드(TaCl5)를 140 ∼ 200 ℃로 유지되는 기화기에서 기상상태로 만든 후, 반응가스인 NH3가스를 10 ∼ 1000 sccm 정도 사용하여 증착한다. 그리고, 반응로 내의 압력을 0.1 ∼ 2.0Torr로 유지하고, 300 ∼ 500 ℃로 가열된 웨이퍼 상에 TaN막을 증착한다.Next, an upper electrode 19 is formed of a TaN film on the dielectric film 17. The upper electrode 19 is formed by vaporizing a tantalum chloride (TaCl 5 ) in a solid state at room temperature in a vaporizer maintained at 140 to 200 ° C., and then depositing the reaction gas using NH 3 gas, which is about 10 to 1000 sccm. . Then, the pressure in the reactor is maintained at 0.1 to 2.0 Torr, and a TaN film is deposited on the wafer heated to 300 to 500 ° C.

상기 TaN막을 플라즈마 화학기상증착(plasma enhanced chemical vapor deposition, 이하 PECVD라 함)방법을 이용하여 증착하는 경우 알.에프.(radio frequency, 이하 RF 라 함)파워(power)를 80 ∼ 400W로 유지하여 증착하되, 상기 RF 파워 인가시 서브 히터(sub heater)를 그라운드(ground)로 하고, 샤워 해드(shower head)를 일렉트로드(electrode)로 한다. (도 3참조)When the TaN film is deposited using plasma enhanced chemical vapor deposition (PECVD), the RF power (radio frequency, hereinafter referred to as RF) is maintained at 80 to 400W. When the RF power is applied, the sub heater is grounded and the shower head is an electrode. (See Fig. 3)

상기한 바와 같이 본 발명에 따른 반도체 소자의 전하저장전극 제조방법은, 하부전극 상부에 유전막인 Ta2O5막을 형성하고, 상기 유전막을 N2O 플라즈마처리 및 고온열처리한 다음, 상기 유전막 상부에 내산화성과 열적으로 안정성이 우수한 TaN막을 상부전극으로 사용함으로써 상기 유전막인 Ta2O5막에 산소가 결핍되는 것을 방지하여 누설전류가 발생하는 것을 감소시켜 소자의 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, in the method of manufacturing a charge storage electrode of a semiconductor device according to the present invention, a Ta 2 O 5 film, which is a dielectric film, is formed on a lower electrode, and the dielectric film is subjected to N 2 O plasma treatment and high temperature heat treatment, and then on the dielectric film. By using a TaN film having excellent oxidation resistance and thermal stability as an upper electrode, the Ta 2 O 5 film, which is the dielectric film, is prevented from oxygen deficiency, thereby reducing the occurrence of leakage current, thereby improving the characteristics and reliability of the device. .

Claims (11)

소정의 하부구조물이 형성된 반도체기판 상부에 하부전극이 구비된 층간절연막을 형성하는 공정과,Forming an interlayer insulating film having a lower electrode on the semiconductor substrate on which the predetermined lower structure is formed; 상기 하부전극 상부를 RTN처리하는 공정과,RTN processing the upper portion of the lower electrode, 전체표면 상부에 Ta2O5막으로 유전막을 형성하는 공정과,Forming a dielectric film on the entire surface with a Ta 2 O 5 film; 상기 유전막을 N2O 플라즈마 처리하는 공정과,N 2 O plasma treatment of the dielectric film, 상기 유전막을 열처리하는 공정과,Heat treating the dielectric film; 상기 유전막 상부에 상부전극용 TaN막을 형성하는 공정을 포함하는 반도체소자의 전하저장전극 제조방법.And forming a TaN film for an upper electrode on the dielectric film. 제 1 항에 있어서,The method of claim 1, 상기 유전막은 LPCVD 방법으로 형성하는 것을 특징으로 하는 반도체소자의 전하저장전극 제조방법.The dielectric film is a method of manufacturing a charge storage electrode of a semiconductor device, characterized in that formed by the LPCVD method. 제 1 항 또는 제 2 항에 있어서.The method according to claim 1 or 2. 상기 유전막은 170 ∼ 190 ℃에서 탄탈륨 에칠레이트(Ta(OC2H5)5)의 기화기 0.001 ∼ 2.0 cc와 반응가스인 O2가스 10 ∼ 1000 sccm을 사용하여 형성하는 것을 특징으로 하는 반도체소자의 전하저장전극 제조방법.The dielectric layer of the semiconductor device characterized in that it formed using tantalum echil rate (Ta (OC 2 H 5) 5) a vaporizer 0.001 ~ 2.0 cc and a reactive gas of O 2 gas 10 ~ 1000 sccm at 170 ~ 190 ℃ Method for manufacturing a charge storage electrode. 제 1 항 또는 제 2 항에 있어서.The method according to claim 1 or 2. 상기 유전막은 반응로의 압력이 0.1 ∼ 1.2 Torr 이고, 웨이퍼의 온도가 350 ∼ 450 ℃ 의 조건에서에 형성하는 것을 특징으로 하는 반도체소자의 전하저장전극 제조방법.The dielectric film is a method of manufacturing a charge storage electrode of a semiconductor device, characterized in that the pressure of the reaction furnace is 0.1 to 1.2 Torr, the wafer temperature is formed under the conditions of 350 ~ 450 ℃. 제 1 항에 있어서.The method of claim 1. 상기 플라즈마처리 공정은 300 ∼ 500 ℃에서 RF 파워가 50 ∼ 400 W인 조건에서 실시하는 것을 특징으로 하는 반도체소자의 전하저장전극 제조방법.The plasma treatment process is a method for manufacturing a charge storage electrode of a semiconductor device, characterized in that the RF power is carried out at 300 to 500 ℃ under the conditions of 50 to 400 W. 제 1 항에 있어서,The method of claim 1, 상기 열처리공정은 750 ∼ 900 ℃에서 O2또는 N2O 가스 분위기의 로 내에서 30 ∼ 60분간 실시하는 것을 특징으로 하는 반도체소자의 전하저장전극 제조방법.The heat treatment process is a charge storage electrode manufacturing method of a semiconductor device, characterized in that performed for 30 to 60 minutes in a furnace of O 2 or N 2 O gas atmosphere at 750 ~ 900 ℃. 제 1 항에 있어서.The method of claim 1. 상기 TaN막은 140 ∼ 200 ℃의 온도에서 기상상태의 탄탈륨 클로라이드(TaCl5)와 반응가스인 NH3가스를 10 ∼ 1000 sccm 사용하여 형성하는 것을 특징으로 하는 반도체소자의 전하저장전극 제조방법.The TaN film is a method of manufacturing a charge storage electrode of a semiconductor device, characterized in that the tantalum chloride (TaCl 5 ) in the gaseous state and NH 3 gas of the reaction gas using a 10 to 1000 sccm at a temperature of 140 ~ 200 ℃. 제 1 항 또는 제 7 항에 있어서,The method according to claim 1 or 7, 상기 TaN막은 반응로 내의 압력을 0.1 ∼ 2.0Torr로 유지하고, 300 ∼ 500 ℃로 가열된 웨이퍼 상에 형성되는 것을 특징으로 하는 반도체소자의 전하저장전극 제조방법.The TaN film is a method of manufacturing a charge storage electrode of a semiconductor device, characterized in that the pressure in the reactor is maintained at 0.1 to 2.0 Torr, and formed on a wafer heated to 300 to 500 ℃. 제 1 항 또는 7 항에 있어서,The method according to claim 1 or 7, 상기 TaN막은 PECVD방법으로 형성되는 것을 특징으로 하는 반도체소자의 전하저장전극 제조방법.The TaN film is a charge storage electrode manufacturing method of a semiconductor device, characterized in that formed by PECVD method. 제 9 항에 있어서,The method of claim 9, 상기 PECVD공정은 80 ∼ 400W 의 RF 파워로 실시하는 것을 특징으로 하는 반도체소자의 전하저장전극 제조방법.The PECVD process is a method of manufacturing a charge storage electrode of a semiconductor device, characterized in that the RF power of 80 to 400W. 제 10 항에 있어서,The method of claim 10, 상기 PECVD공정은 RF 파워 인가시 서브 히터(sub heater)를 그라운드(ground)로 사용하고, 샤워 해드(shower head)를 일렉트로드(electrode)로 사용하여 실시하는 것을 특징으로 하는 반도체소자의 전하저장전극 제조방법.The PECVD process is performed by using a sub heater as a ground and applying a shower head as an electrode when RF power is applied. Manufacturing method.
KR1019980025977A 1998-06-30 1998-06-30 Method for manufacturing a storage electrode of semiconductor devices KR20000004533A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019980025977A KR20000004533A (en) 1998-06-30 1998-06-30 Method for manufacturing a storage electrode of semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019980025977A KR20000004533A (en) 1998-06-30 1998-06-30 Method for manufacturing a storage electrode of semiconductor devices

Publications (1)

Publication Number Publication Date
KR20000004533A true KR20000004533A (en) 2000-01-25

Family

ID=19542358

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980025977A KR20000004533A (en) 1998-06-30 1998-06-30 Method for manufacturing a storage electrode of semiconductor devices

Country Status (1)

Country Link
KR (1) KR20000004533A (en)

Similar Documents

Publication Publication Date Title
US7429538B2 (en) Manufacturing method for two-step post nitridation annealing of plasma nitrided gate dielectric
KR100282413B1 (en) Thin film formation method using nitrous oxide gas
KR100371142B1 (en) Capacitor Formation Method of Semiconductor Device
KR20010064414A (en) Method of forming gate dielectric layer with TaON
KR20000011703A (en) A method for gate-stack formation including a high-k dielectric
KR100192017B1 (en) Fabrication process of semiconductor device
KR100308501B1 (en) Method for forming capacitor of semiconductor device
KR20000004533A (en) Method for manufacturing a storage electrode of semiconductor devices
KR20000042429A (en) Method for manufacturing ferroelectric capacitor of semiconductor device
KR20010063468A (en) Method of manufacturing a capacitor in a semiconductor device
KR100359783B1 (en) Method for Fabricating Capacitor of Semiconductor Device
KR100231604B1 (en) Manufacturing method of capacitor of semiconductor device
KR100574926B1 (en) Method for Thermal treatment of TiAlN layer
KR100530149B1 (en) Method for manufacturing gate electrode of semiconductor device
KR20000024712A (en) Method for fabricating capacitor having tantalum oxide film as dielectric film
KR100600292B1 (en) Method of manufacturing a capacitor in a semiconductor device
JP4106513B2 (en) Capacitor manufacturing method for semiconductor device
KR100304688B1 (en) Method for manufacturing semiconductor device
KR100364804B1 (en) Method for Fabricating of Semiconductor Device
KR100365749B1 (en) A method for fabrication of semiconductor device
KR19990048782A (en) Capacitor Formation Method of Semiconductor Device
KR100949874B1 (en) A method for forming a storage node of a semiconductor device
KR100404481B1 (en) Method for manufacturing capacitor semiconductor device
KR970000704B1 (en) Manufacturing method of capacitor insulating film in semiconductor device
KR20000042480A (en) Method for fabricating capacitor of semiconductor device

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid