KR20000004509A - Precharge circuit of multilevel sensing amplifier and method of precharging multilevel sensing amplifier - Google Patents

Abstract

PURPOSE: The circuit is to prevent read data from being deformed when a multilevel sensing amplifier reads data secondarily. CONSTITUTION: The circuit comprises a first and a second sensing amplifier(10, 70) provided in a bit line of a DRAM and in a bit line of left and right memory cells, a feedback element(60) provided on bit lines, a switching transistor for dividing a reference bit line, and a comparator(50) provided on a bit line. The comparator is connected on its node to a NMOS transistor. In the comparator, a source of the NMOS transistor is connected to a half supply voltage, a drain is connected to the node, and a gate is connected to an equalizing signal.

Description

Precharge Circuit and Method for Multilevel Sense Amplifier

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilevel memory cell sense amplifier of a semiconductor memory device, and in particular, to have a sufficient bitline plate voltage (VBLP) potential when precharged in a multilevel sense amplifier circuit, thereby reading data during secondary sensing. The present invention relates to a precharge circuit of a multilevel sense amplifier, and a method thereof, in which a multi-sense sensing is possible by preventing deformation.

In general, when DRAM reaches a limit that reduces the chip size even though the cell and its process continue to be miniaturized as the DRAM becomes more integrated, the current method, that is, Vcc or Vss is stored in the cell. The chip size can no longer be reduced.

At this time, if Vcc, 2 / 3Vcc, 1 / 3Vcc, Vss can be stored and read in a cell, the number of cells can be reduced by half than the number of cells required by the present method.

Referring to the multilevel sense amplifier in detail, as shown in FIG. 1, in addition to the bit line and cell 2 and 4 structures of a general DRAM, a sense amplifier 1, 7), a feedback element 6 per bit line, a switching transistor 3 dividing the reference bit line into two, a comparator 5 consisting of an exclusive oar gate per bit line, and the like are further required.

Conventional sense amplifiers store and read VCC ("1" data) or VSS ("0" data) in one cell. In a multilevel sense amplifier, VCC ("1.1" data; Strong one), 2 in one cell. / 3VCC ("1.0" data; Weak one), 1 / 3VCC ("0.1" data; Weak Zero), VSS ("0.0" data; Strong Zero) technology to store and read.

First, as shown in (a) of FIG. 2, all of the NMOS transistors N7-N9 are turned on while the equalizing signal EQU is the power supply voltage VCC in the precharge period. The bit lines BLL and BLR and the bit line bars BLB and BLRB are both precharged to the half supply voltage (hereinafter referred to as HVCC below half VCC).

At this time, since both VCT1 and VCT2 are at a high voltage (VCC + = VPP) as shown in FIGS. 2C and 2D, the sensing input nodes S3 and S4 of the second sense amplifier 7 also have a half power supply voltage. (HVCC)

Here, the node X4 of the comparator 5 has the NMOS transistor N22 precharged through the NMOS transistor N23, and the gate voltage of the NMOS transistor N23 is also the half power supply voltage HVCC. Since the source voltage is also the half power supply voltage HVCC, the node X4 reaches only the HVCC-Vt voltage, which causes a problem in the secondary data read operation.

Second, when the first word line wl1 is turned on to the high voltage VCC + = VPP as shown in FIG. 2B in a read or write period, the NMOS transistor N10. ) Is turned on and loaded on the bit lines BLL and BLR as a data charge share of the cell, and the data is transferred to the sensing input node S3 of the second sense amplifier 7. As shown in (d) of FIG. 2, the NMOS transistors N26 and N27 are turned off using the ground power supply VSS to sense the input of the bit line BL and the second sense amplifier 7. The node S3, the bit line bar BLB, and the sensing input node S4 of the second sense amplifier 7 are isolated.

Thereafter, as shown in FIG. 2E, the first sense amplifier 1 suspended from the sensing input node S1 and the sensing input node S2 is activated with VSP1 and VSN1B to read the first data. The feedback voltage VFB is applied to the power supply voltage VCC as shown in FIG. 2 (bar) to pass through the NMOS transistors N24 and N25 to the right bit line BLR and the right bit line bar BLRB. By adjusting the coupling amount of the capacitors C9 and C10 according to the voltage, that is, the gate voltages of the NMOS transistors N24 and N25, the sensing input node S3 and the sensing input node (the input of the second sensing) After modification to S4), VSP2 and VSN2B are operated as shown in Fig. 2G to activate the second sense amplifier 7 to read the second data.

Third, as shown in (a) of FIG. 2 in the restore section, VMT0 remains VCC + and VMT1 becomes the ground power supply VSS to isolate the left bit line bar BLB, and then restore voltage. When the node X4 is " high " according to the potential of the node X4 by applying the VRST to VCC + as shown in FIG. 2, the NMOS transistor N21 is turned on and the node By making (X1) VCC +, the charge of the left bit line BLL, the charge of the right bit line BLR, and the charge of the right bit line bar BLRB are shared through the NMOS transistor N2. The specific voltages (2 / 3VCC, 1 / 3VCC) are generated and restored to the left and right memory cells 2 and 4.

In the above, the outline of read and write operations of conventional multi sensing has been described.

Now, the problem occurs when the node X4 is not precharged by HVCC but is precharged by HVCC-Vtn in the conventional multi-sensing operation.

If the data of the cell is (1, 0), that is, 2/3 VCC is stored and read in the cell (finally S1 = VCC, S2 = VSS, S3 = VSS, and S4 = VCC must be loaded). The equalization signal EQU is disabled as "low" as shown in FIG. 4A, thereby precharging both the bit line BL and the bit line bar BLB. After turn-off.

At this time, it is assumed that the node X4 is also precharged with the HVCC, and the word line WL1 is turned on as shown in (b) of FIG. 4 to have 2/3 VCCs. The data of 4) is loaded on the bit line BL as charge sharing and is also loaded on the sensing input node S3 of the second sense amplifier 7.

At this time, the data loaded on the bit line BL and the sensing input node S3 is “HVCC + ΔV”, and the sensing of the second sense amplifier 7 with VCT2 “low” as shown in (d) of FIG. 4. After the input nodes S3 and S4 are separated from the bit line BL and the bit line bar BLB, the first sense amplifier 1 is connected by VSP1 and VSN1B as shown in FIG. Activate to read "high" data (S1 = VCC, S2 = VSS) with primary sensing.

At this time, it is natural that the delta V10 has a reduced sensing input margin than when the VCC is stored in the left and right memory cells 2 and 4, as shown in FIG.

At this time, the operation of the feedback voltage VFB changes the second sensing input level as shown in FIG. 4B, where the VFB operation timing greatly affects the change of the sensing input nodes S3 and S4. Crazy

Here, normal secondary sensing is possible only when the feedback voltage VFB is modified to S3 = "HVCC- DELTA V" and S4 = "HVCC + DELTA V".

However, a problem actually arises in the process, in which the junction caps of the NMOS transistors N22 and N23 are coupled as the right bit line BLR and the right bit line bar BLRB are opened. In this manner, unwanted deformations start to occur at the sensing input nodes S3 and S4.

At this time, the degree of deformation occurs as the right bit line BLR and the right bit line bar BLRB are widened as shown in the ratio shown in FIG.

Therefore, when the right bit line BLR and the right bit line bar BLRB are minimized, operating the feedback voltage VFB can minimize unwanted deformation.

However, if the feedback voltage VFB is operated while the right bit line BLR and the right bit line bar BLRB are not open yet, selective data transformation cannot be performed.

That is, the right bit line BLR is recognized as "high" and a lot of coupling occurs to the capacitor C9 through the NMOS transistor N24, and the right bit line bar BLRB is "low". The coupling (Coupling) should be less to the capacitor (C10) through the MOS transistor (N25), such a phenomenon does not occur so that the sensing input in the desired state (S3 = HVCC- DV, S4 = HVCC + D) Deformation cannot be applied to the nodes S3 and S4.

For this reason, the optimization of the feedback voltage VFB operation timing is a time point at which the unwanted modifications of the NMOS transistors N22 and N23 are small and the NMOS transistors N24 and N25 can be selectively operated.

That is, when the right bit line BLR is "HVCC + Vt" and the right bit line bar BLRB is "HVCC-Vt".

In the simulation, when VCC = 3.3V, the right bit line BLR is 2.28V and the right bit line bar BLRB is 0.89V.

Here, even if the feedback voltage (VFB) operation is optimized, it is normal for each data "11", "10", "1", and "0" due to an unwanted deformation by the node X4 described below. The operation is difficult.

Here, consider node X4.

The precharge of node X4 to some potential HVCC greatly affects the input level of secondary sensing.

In the first sense, when the right bit line BLR becomes VCC and the right bit line bar BLRB begins to spread to VSS, the right bit line BLR acts as a gate voltage of the NMOS transistor N22, which causes By starting to turn on the MOS transistor N22, the node X4 and the node S4 begin to equalize, thereby causing undesired deformation.

However, here, a problem occurs because the node X4 is actually precharged only "HVCC-Vt".

That is, when the right bit line BLR becomes VCC, the right bit line bar BLRB becomes VSS, and the right bit line BLR becomes “HVCC + Vt” by primary sensing, the NMOS transistor N22 By acting as a gate voltage, the NMOS transistor N22 is turned on to start to equalize the node X4 and the sensing input node S4, so that the sensing input node S4 is shown in FIG. 7. Falls greatly together.

As shown in FIG. 4 (ta), the sensing input node S4 is higher than the node S3 through the NMOS transistor N24 by the operation of the feedback voltage VFB. In other words, S3 = "HVCC- DELTA V", S4 = "HVCC + DELTA V", and so on, such an operation cannot be performed, causing secondary sensing data to fail.

Even if the above-described optimization of the feedback voltage VFB operation is made, the problems caused by the node X4 add up, and as shown in FIGS. 3 to 6, the respective data "11", "10", "1", Normal operation on "0") is difficult.

In general, the conventional multi-sensing circuit has a problem of the above-mentioned operation of the feedback voltage VFB, difficulty in optimizing the timing and problems caused by the node X4, and the right bit line by the NMOS transistors N22 and N23. BLR), unbalanced action due to data in the secondary sense input margin due to continuous coupling between the right bitline bar (BLRB) and the sensing input nodes (S3, S4). 10, 01 ") and a failure (data" 11, 00 ") occur.

Accordingly, the present invention was devised to solve the above-mentioned problems, and has a sufficient bit line plate voltage (VBLP) potential when precharged in a multilevel sense amplifier circuit, thereby reading during secondary sensing. It is an object of the present invention to provide a precharge circuit and a method of a multilevel sense amplifier, which prevents data from being modified to allow full multi sensing.

1 is a configuration circuit diagram of a general multilevel sense amplifier;

2 is a timing diagram of a read and restore operation according to FIG. 1;

3 is an internal timing diagram during read and restore operations when data according to FIG. 1 is Strong One (1, 1);

4 is an internal timing diagram during read and restore operations when data according to FIG. 1 is Weak One (1, 0);

FIG. 5 is an internal timing diagram during read and restore operation when data according to FIG. 1 is Weak Zero (0, 1); FIG.

6 is an internal timing diagram during read and restore operations when data according to FIG. 1 is Strong Zero (0, 0);

7 is a diagram illustrating a second sensing simulation result according to a conventional incomplete precharge level;

8 is a precharge circuit diagram of a multilevel sense amplifier according to the present invention;

9 is an exemplary view illustrating a second sensing simulation result according to a complete precharge level according to the present invention.

<Description of Symbols for Major Parts of Drawings>

10: first sense amplifier 20: left memory cell

30: switching transistor 40: right memory cell

50: comparator 60: feedback element

70 second sense amplifier 80 separation transistor

In order to achieve the object described above, the present invention provides a first and second sense amplifiers per bit line, a feedback element per bit line, and a bit line and a left and right memory cell structure of a general DRAM. A multilevel sense amplifier having a switching transistor for dividing a reference bit line and a comparator formed on the bit line, characterized in that the NMOS transistor is connected to the node X4 of the comparator.

In order to achieve the above object, the present invention provides a method for precharging a multi-level sensing operation, in which the node X4 of the comparator is precharged with a half power supply voltage HVCC using an NMOS transistor. It is characterized by.

The operation principle according to the present invention will be described in detail as follows.

As shown in FIG. 8, the precharge circuit of the multilevel sense amplifier according to the present invention includes first and second per bit lines in a bit line and left and right memory cells 20 and 40 of a general DRAM. A multilevel sense amplifier having a sense amplifier 10, 70, a feedback element 60 per bit line, a switching transistor 30 for dividing a reference bit line, and a comparator 50 formed on the bit line. In this configuration, the NMOS transistor N34 is connected to the node X4 of the comparator 50.

In the comparator 50, the source of the NMOS transistor N34 is connected to the half power supply voltage HVCC, the drain is connected to the node X4, and the equalization signal EQU is connected to the gate.

There is no change in the timing of each control signal, and the operation is performed in the conventional manner.

That is, as shown in (a) of FIG. 2, all of the NMOS transistors N7-N9 are turned on while the equalizing signal EQU is the power supply voltage VCC in the precharge period. Therefore, the bit lines BLL and BLR and the bit line bars BLB and BLRB are both precharged with a half power supply voltage (hereinafter referred to as HVCC below half VCC).

At this time, since both VCT1 and VCT2 are at a high voltage (VCC + = VPP) as shown in FIGS. 2C and 2D, the sensing input nodes S3 and S4 of the second sense amplifier 7 also have a half power supply voltage. (HVCC)

Here, the node X4 of the comparator 50 has the equalized signal EQU “high” when the first and second sense amplifiers 10 and 70 and the bit line BL are precharged. The NMOS transistor N34 is turned on so that the node X4 may be precharged to the half power voltage HVCC as shown in FIG. 9.

As described in detail above, the present invention can prevent deformation of read data during secondary sensing by having a sufficient bit line plate voltage (VBLP) potential when precharged in a multilevel sense amplifier circuit. Due to this, there is an effect of enabling complete multi-sensing by preventing a second sensing failure.

Preferred embodiments of the present invention are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, additions, and the like within the spirit and scope of the present invention, and such modifications and changes should be regarded as belonging to the following claims. something to do.

Claims (5)

The first and second sense amplifiers per bit line, the feedback element per bit line, the switching transistor for dividing the reference bit line, in the bit line and left and right memory cell structures of a general DRAM, A multilevel sense amplifier having a formed comparator, And a NMOS transistor connected to the node (X4) of the comparator. The method of claim 1, The NMOS transistor, A precharge circuit for a multilevel sense amplifier, characterized in that it is configured to control using an equalizing signal (EQU). In the method for precharging during the multi-level sensing operation, A precharge method for a multilevel sense amplifier, characterized in that the node of the comparator is precharged with a half power supply voltage (HVCC) using an NMOS transistor. The method of claim 3, wherein The NMOS transistor, A precharge method for a multilevel sense amplifier, characterized in that the control using an equalization signal (EQU). The method of claim 3, wherein The NMOS transistor, The node is pre-simulated simultaneously with the bit line BL and the first and second sense amplifiers by using an equalization signal EQU which precharges the bit line BL and the first and second sense amplifiers to the half supply voltage HVCC. A precharge method for a multilevel sense amplifier, characterized in that the charge.