KR100337202B1 - Multilevel sensing circuit and method - Google Patents

Abstract

The present invention relates to a multilevel memory cell sense amplifier of a semiconductor memory device. In particular, the secondary sensing input node can be completely separated from the multilevel sense amplifier circuit so that the effective variation of the secondary sensing input and its input gain can be secured. A switching element for selectively dividing a bit line or a bit line bar between a sensing operation and a restore operation, a first sense amplifier reading a first data value stored in a memory cell, and reading a second data value stored in the memory cell. Is a second sense amplifier, a feedback element for inverting the voltage difference between the input terminal of the second sense amplifier when the voltage difference is less than a predetermined voltage as a result of the charge of the capacitor of the memory cell loaded on the bit line and the bit line bar; 2 sense amplifiers are connected to each other by comparing the read first data value and the second data value. In other cases, the present invention relates to a multilevel sensing circuit and a method of operating the bit line and the bit line bar to distribute charge.

Description

Multilevel sensing circuit and method

The present invention relates to a multilevel memory cell sense amplifier of a semiconductor memory device. In particular, the secondary sensing input node can be completely separated from the multilevel sense amplifier circuit so that the effective variation of the secondary sensing input and its input gain can be secured. The present invention relates to a multilevel sensing circuit and a method thereof.

In general, when DRAM reaches a limit that reduces the chip size even though the cell and its process continue to be miniaturized as the DRAM becomes more integrated, the current method, that is, Vcc or Vss is stored in the cell. The chip size can no longer be reduced.

At this time, if Vcc, 2 / 3Vcc, 1 / 3Vcc, Vss can be stored and read in a cell, the number of cells can be reduced by half than the number of cells required by the present method.

Referring to the multilevel sense amplifier in detail, as shown in FIG. 1, in addition to the bit line and cell 2 and 4 structures of a general DRAM, a sense amplifier 1, 7), a feedback element 6 per bit line, a switching transistor 3 dividing the reference bit line into two, a comparator 5 consisting of an exclusive oar gate per bit line, and the like are further required. Such multilevel sense amplifiers have been disclosed in US Pat. No. 5,684,736, "Multilevel Memory Cell Sense Amplifier System," patented by NuRam Technology, Inc.

Conventional sense amplifiers store and read VCC ("1" data) or VSS ("0" data) in one cell. In a multilevel sense amplifier, VCC ("1.1" data; Strong one), 2 in one cell. / 3VCC ("1.0" data; Weak one), 1 / 3VCC ("0.1" data; Weak Zero), VSS ("0.0" data; Strong Zero) technology to store and read.

First, as shown in (a) of FIG. 2, all of the NMOS transistors N7-N9 are turned on while the equalizing signal EQU is the power supply voltage VCC in the precharge period. The bit lines BLL and BLR and the bit line bars BLB and BLRB are both precharged to the half supply voltage (hereinafter referred to as HVCC below half VCC).

At this time, since both VCT1 and VCT2 are at a high voltage (VCC + = VPP) as shown in FIGS. 2C and 2D, the sensing input nodes S3 and S4 of the second sense amplifier 7 also have a half power supply voltage. (HVCC)

Here, the node X4 of the comparator 5 has the NMOS transistor N22 precharged through the NMOS transistor N23, and the gate voltage of the NMOS transistor N23 is also the half power supply voltage HVCC. Since the source voltage is also the half power supply voltage HVCC, the node X4 reaches only the HVCC-Vt voltage, which causes a problem in the secondary data read operation.

Second, when the first word line wl1 is turned on to the high voltage VCC + = VPP as shown in FIG. 2B in a read or write period, the NMOS transistor N10. ) Is turned on and the data charge of the cell is distributed (DataCharge Share) to the bit lines BLL and BLR, and the carried data is transferred to the sensing input node S3 of the second sense amplifier 7, As shown in FIG. 2D, the NMOS transistors N26 and N27 are turned off using the ground power supply VSS to sense the bit line BL and the second sense amplifier 7. The input node S3, the bit line bar BLB, and the sensing input node S4 of the second sense amplifier 7 are isolated.

Thereafter, as shown in FIG. 2E, the first sense amplifier 1 suspended from the sensing input node S1 and the sensing input node S2 is activated with VSP1 and VSN1B to read the first data. The feedback voltage VFB is applied to the power supply voltage VCC as shown in FIG. 2 (bar) to pass through the NMOS transistors N24 and N25 to the right bit line BLR and the right bit line bar BLRB. By adjusting the coupling amount of the capacitors C9 and C10 according to the voltage, that is, the gate voltages of the NMOS transistors N24 and N25, the sensing input node S3 and the sensing input node (the input of the second sensing) After modification to S4), VSP2 and VSN2B are operated as shown in Fig. 2G to activate the second sense amplifier 7 to read the second data.

Third, as shown in (a) of FIG. 2 in the restore section, VMT0 remains VCC + and VMT1 becomes the ground power supply VSS to isolate the left bit line bar BLB, and then restore voltage. When the node X4 is "high", the NMOS transistor N21 is turned on according to the potential of the node X4 by applying the VRST to VCC + as shown in FIG. Since the node X1 is made VCC +, the charge of the left bit line BLL, the charge of the right bit line BLR, and the charge of the right bit line bar BLRB are shared through the NMOS transistor N2. Then, specific voltages (2 / 3VCC, 1 / 3VCC) are generated and restored to the left and right memory cells 2 and 4.

In the above, the read and write operations of the existing multi-sensing have been described.

Now, the problem occurs when the node X4 is not precharged by HVCC but is precharged by HVCC-Vtn in the conventional multi-sensing operation.

If the data of the cell is (1, 0), that is, 2/3 VCC is stored and read in the cell (finally S1 = VCC, S2 = VSS, S3 = VSS, and S4 = VCC must be loaded). The equalization signal EQU is disabled as "low" as shown in FIG. 4A, thereby precharging both the bit line BL and the bit line bar BLB. After turn-off.

At this time, it is assumed that the node X4 is also precharged with the HVCC, and the word line WL1 is turned on as shown in (b) of FIG. 4 to have 2/3 VCCs. The data of 4) is loaded on the bit line BL by charge sharing and is also loaded on the sensing input node S3 of the second sense amplifier 7.

At this time, the data loaded on the bit line BL and the sensing input node S3 is “HVCC + ΔV”, and the sensing of the second sense amplifier 7 with VCT2 “low” as shown in (d) of FIG. 4. After the input nodes S3 and S4 are separated from the bit line BL and the bit line bar BLB, the first sense amplifier 1 is connected by VSP1 and VSN1B as shown in FIG. Activate to read "high" data (S1 = VCC, S2 = VSS) with primary sensing.

At this time, the delta V10 (voltage difference of the bit line when the data of the cell is (1,0)) is set to VCC in the left and right memory cells 2 and 4 as shown in (ta) of FIG. Obviously, the sensing input margin is reduced compared to when is stored.

At this time, the operation of the feedback voltage VFB changes the secondary sensing input level as shown in FIG. 4B, where the VFB operation timing greatly affects the change of the sensing input nodes S3 and S4. Crazy

Here, normal secondary sensing is possible only when the feedback voltage VFB is modified to S3 = "HVCC- DELTA V" and S4 = "HVCC + DELTA V".

However, a problem actually occurs in the process, in which the junction caps of the NMOS transistors N22 and N23 are coupled as the right bit line BLR and the right bit line bar BLRB are opened. In this manner, unwanted deformations start to occur at the sensing input nodes S3 and S4.

At this time, the degree of the deformation occurs as the right bit line BLR and the right bit line bar BLRB are widened as shown in the ratio (c) of FIG. 4.

Therefore, the unwanted deformation can be minimized by operating the feedback voltage VFB when the right bit line BLR and the right bit line bar BLRB are opened to the minimum.

However, if the feedback voltage VFB is operated while the right bit line BLR and the right bit line bar BLRB are not open yet, selective data transformation cannot be performed.

That is, the right bit line BLR is recognized as "high" and a lot of coupling occurs to the capacitor C9 through the NMOS transistor N24, and the right bit line bar BLRB is "low". The coupling (Coupling) should be less to the capacitor (C10) through the MOS transistor (N25), such a phenomenon does not occur so that the sensing input in the desired state (S3 = HVCC- DV, S4 = HVCC + D) Deformation cannot be applied to the nodes S3 and S4.

For this reason, the optimization of the feedback voltage VFB operation timing is a time point at which the unwanted modifications of the NMOS transistors N22 and N23 are small and the NMOS transistors N24 and N25 can be selectively operated.

That is, when the right bit line BLR is "HVCC + Vt" and the right bit line bar BLRB is "HVCC-Vt".

As shown in FIG. 8, the right bit line BLR is 2.28V and the right bit line bar BLRB is 0.89V when VCC = 3.3V in the simulation.

Here, even if the feedback voltage (VFB) operation is optimized, it is normal for each data "11", "10", "1", and "0" due to an unwanted deformation by the node X4 described below. The operation is difficult.

Here, consider node X4.

The precharge of node X4 to some potential HVCC greatly affects the input level of secondary sensing.

In the first sense, when the right bit line BLR becomes VCC and the right bit line bar BLRB begins to spread to VSS, the right bit line BLR acts as a gate voltage of the NMOS transistor N22, which causes By starting to turn on the MOS transistor N22, the node X4 and the node S4 begin to equalize, thereby causing undesired deformation.

However, here, a problem occurs because the node X4 is actually precharged only "HVCC-Vt".

That is, when the right bit line BLR becomes VCC, the right bit line bar BLRB becomes VSS, and the right bit line BLR becomes “HVCC + Vt” by primary sensing, the NMOS transistor N22 The NMOS transistor N22 is turned on to act as a gate voltage to start to equalize the node X4 and the sensing input node S4, so that the sensing input node S4 is shown in FIG. 12. Falls greatly together.

As shown in FIG. 4 (ta), the sensing input node S4 is higher than the node S3 through the NMOS transistor N24 by the operation of the feedback voltage VFB. In other words, S3 = "HVCC- DELTA V", S4 = "HVCC + DELTA V", and so on, such an operation cannot be performed, causing secondary sensing data to fail.

Even if the above-described optimization of the feedback voltage VFB operation is made, the problems caused by the node X4 add up, and as shown in FIGS. 3 to 6, the respective data "11", "10", "01", Normal operation for " 00 "

Here, let's look at the failure phenomenon according to each data.

first ; In the case of " 11 " data, as shown in Fig. 7, the first data is " high (S3 = "HVCC + ΔV", S4 = "HVCC-ΔV") "and the second data is" high (S3 = "HVCC + ΔV"). ", S4 =" HVCC- DELTA V ").

According to the above-described operation method according to the data, the NMOS transistor N22 is turned while the right bit line BLR and the right bit line bar BLRB start to spread from the HVCC to the VCC and VSS by the first sensing. Starts on, equalizes nodes X4 and S4, increases the potential of sensing input node S4, and operates the feedback voltage VFB to operate NMOS transistor N24 and capacitor C9. ), The potential of the node S4 is further increased.

Here, the equalization operation of the nodes X4 and S4 serves as a factor for worsening the second sensing input margin in the case of "11" data.

In addition, in the case of the "11" data, the continuous coupling to the node S4 through the continuous NMOS transistor N22 causes inversion of the data during the second sensing, which causes a failure.

second ; In the case of "10" data, as shown in FIG. 8, the first data is "high (S3 =" HVCC + ΔV ", S4 =" HVCC-ΔV ")" and the second data is "low (S3 =" HVCC-Δ). V ", S4 =" HVCC + ΔV ")".

According to the above-described operation method according to the data, the NMOS transistor N22 is turned while the right bit line BLR and the right bit line bar BLRB start to spread from the HVCC to the VCC and VSS by the first sensing. Starts on, equalizes nodes X4 and S4 to increase the potential of sensing input node S4 and operates feedback voltage VFB to operate NMOS transistor N24 and capacitor C9. Coupling further increases the potential of the sensing input node S4.

Here, the equalizing operation of the nodes X4 and S4 serves as an element for further improving the second sensing input margin in the case of "10" data.

In addition, in the case of "10" data, the continuous coupling to the node S4 through the continuous NMOS transistor N22 makes the secondary sensing input margin even better and does not cause a problem.

third ; In the case of "01" data, as shown in FIG. 9, the first data is "low (S3 =" HVCC-ΔV ", S4 =" HVCC + ΔV ")" and the second data is "high (S3 =" HVCC + ΔV). ", S4 =" HVCC-ΔV ")".

According to the above-described operation method according to the data, the NMOS transistor N23 is turned while the right bit line BLR and the right bit line bar BLRB start to spread from the HVCC to the VCC and VSS in the first sensing. It starts to turn on, and equalizes the nodes X4 and S4 to increase the potential of the sensing input node S4 while operating the feedback voltage VFB to operate the NMOS transistor N25 and the capacitor C10. Coupling further increases the potential of the sensing input node S4.

Here, the equalization operation of the nodes X4 and S4 serves as an element for further improving the second sensing input margin in the case of "01" data.

In addition, in the case of "01" data, the secondary sensing input margin is further improved due to continuous coupling to the sensing input node S3 through the NMOS transistor N23, thereby not causing a problem.

fourth; In the case of "00" data, as shown in Fig. 10, the first data is " low (S3 = " HVCC- DELTA V "), and the second data is " low " S3 = " HVCC- D " V ", S4 =" HVCC + ΔV ")".

According to the above-described operation method according to the data, the NMOS transistor N23 is turned while the right bit line BLR and the right bit line bar BLRB start to spread from the HVCC to the VCC and VSS in the first sensing. Coupling of the NMOS transistor N25 and the capacitor C10 by the operation of the feedback voltage VFB while increasing the potential of the node S4 by equalizing the nodes X4 and S4. Coupling further increases the potential of the sensing input node S4.

Here, the equalizing operation of the nodes X4 and S4 acts as a factor worsening the secondary sensing input margin in the case of "00" data.

In addition, in the case of "00" data, the continuous coupling to the sensing input node S3 through the NMOS transistor N23 makes the secondary sensing input margin worse and causes a problem.

In the operation according to the data described above, the continuous coupling between the right bit line BLR, the right bit line bar BLRB and the sensing input nodes S3 and S4 by the NMOS transistors N22 and N23 is 2; An unbalanced action on the secondary sensing input margin causes a failure.

On the other hand, when data is "10" at the time of restore, BLL = VCC, BLLB = VSS, BLR = VCC, BLRB = VSS, and node X4 is VCC.

At this time, if VMT0 = VCC +, VTM1 = VSS, and VRST goes up to VCC +, the potential of node X4, which was VCC, is boosted to become “VCC +” + ΔV potential, so node X1 becomes VCC + potential and left bit. The line BLL, the right bit line BLR, and the right bit line bar BLRB are charged share so that the (2/3) * VCC potential must be restored.

However, in this operation, the right bitline bar (BLRB), which was actually at VSS, goes up to (2/3) * VCC with charge sharing.

In this process, the NMOS transistor N23 is turned off and is turned on.

In this way, the node X4 at " VCC + " + DELTA V and the sensing input node S3 at VSS are equalized to lower the potential of the node X4, making the restore operation unstable.

In general, the conventional multi-sensing circuit has a problem of the above-mentioned operation of the feedback voltage VFB, difficulty in optimizing the timing and problems caused by the node X4, and the right bit line by the NMOS transistors N22 and N23. BLR), unbalanced action due to data in the secondary sense input margin due to continuous coupling between the right bitline bar (BLRB) and the sensing input nodes (S3, S4). 10, 01 ") and a failure (data" 11, 00 ") occur.

In addition, there is an unstable problem of node X4 at restore time.

That is, when the comparator 5 and the node X4 sense the secondary, an unwanted interference phenomenon occurs at the sensing input nodes S3 and S4, thereby causing a problem.

Accordingly, the present invention has been devised to solve the above-mentioned problems. The second sensing input node is completely separated from the multilevel sense amplifier circuit, so that the effective modification of the second sensing input and its input gain can be secured. It is an object of the present invention to provide a multilevel sensing circuit and a method thereof.

1 is a configuration circuit diagram of a general multilevel sense amplifier;

2 is a timing diagram of a read and restore operation according to FIG. 1;

3 is an internal timing diagram during read and restore operations when data according to FIG. 1 is Strong One (1, 1);

4 is an internal timing diagram during read and restore operations when data according to FIG. 1 is Weak One (1, 0);

FIG. 5 is an internal timing diagram during read and restore operation when data according to FIG. 1 is Weak Zero (0, 1); FIG.

6 is an internal timing diagram during read and restore operations when data according to FIG. 1 is Strong Zero (0, 0);

7 is an exemplary diagram illustrating a second sensing simulation result when data according to FIG. 1 is Strong One (1, 1);

8 is an exemplary diagram illustrating a second sensing simulation result when the data according to FIG. 1 is Weak One (1, 0).

9 is an exemplary diagram illustrating a second sensing simulation result when the data according to FIG. 1 is Weak Zero (0, 1).

10 is an exemplary diagram illustrating a second sensing simulation result when data according to FIG. 1 is Strong Zero (0, 0);

11 is a block diagram of a multilevel sensing circuit according to the present invention;

12 is a timing diagram of a read and restore operation according to FIG. 11;

FIG. 13 is an internal timing diagram during read and restore operations when data according to FIG. 11 is Weak One (1, 0); FIG.

14 is a diagram illustrating a second sensing simulation result when the data according to FIG. 11 is Strong One (1, 1);

15 is an exemplary diagram illustrating a second sensing simulation result when the data according to FIG. 11 is Weak One (1, 0);

16 is an exemplary diagram illustrating a second sensing simulation result when the data according to FIG. 11 is Weak Zero (0, 1).

FIG. 17 is an exemplary view illustrating a second sensing simulation result when data according to FIG. 11 is Strong Zero (0, 0).

<Description of Symbols for Major Parts of Drawings>

10: first sense amplifier 20: left memory cell

30: switching transistor 40: right memory cell

50: comparator 60: feedback element

70 second sense amplifier 80 separation transistor

In order to achieve the above object, the present invention provides a switching element for selectively dividing a bit line or a bit line bar between a sensing operation and a restore operation. A first sense amplifier reading a first data value stored in a memory cell, a second sense amplifier reading a second data value stored in the memory cell, and a charge of a capacitor of the memory cell in the bit line and the bit line When the voltage difference is less than a predetermined voltage, the feedback device for reversing the voltage difference between the input terminal of the second sense amplifier and the second sense amplifier are connected to compare the read first data value and the second data value. A multilevel sense amplifier having a comparator for distributing charges by connecting the bit line and the bit line bar when different from each other, the multi-level sense amplifier further comprising a separating transistor between the comparator and the second sense amplifier. It further comprises a level sensing circuit.

In order to achieve the above object, the present invention provides a comparator 50 and a second sense amplifier 70 in a sensing method of storing and reading data of a memory cell in a DRAM capable of storing data at a multilevel. It is characterized in that it operates so as to arbitrarily isolate or connect the input and the force unit sensing input nodes (S3, S4).

The operation principle according to the present invention will be described in detail as follows.

As shown in FIG. 11, the multilevel sensing circuit according to the present invention includes first and second sense amplifiers 10 per bit line in a bit line and a left and right memory cells 20 and 40 of a general DRAM. 70. A multilevel sense amplifier having a feedback element 60 per bit line, a switching transistor 30 for dividing a reference bit line, and a comparator 50 formed on the bit line. A separation transistor 80 composed of NMOS transistors N34 and N35 is connected between 50 and the sensing input nodes S3 and S4 of the second sense amplifier 70.

In the isolation transistor 80, the source of the NMOS transistor N34 is connected to the sensing input node S4, the drain is connected to the comparator 50, and a signal VaSA is enabled to the gate after the first sensing.

The NMOS transistor N35 has the same structure as that of the NMOS transistor N34. The source of the NMOS transistor N35 is sensed at the sensing input node S3, the drain is provided at the comparator 50, and the gate is first sensed. Connect the enabled signal VaftSA.

First, as shown in (a) of FIG. 12, all of the NMOS transistors N7-N9 are turned on while the equalizing signal EQU is the power supply voltage VCC in the precharge period. The bit lines BLL and BLR and the bit line bars BLB and BLRB are both precharged to the half supply voltage (hereinafter referred to as HVCC below half VCC).

At this time, since both VCT1 and VCT2 are at a high voltage (VCC + = VPP) as shown in FIGS. 12C and 12D, the sensing input nodes S3 and S4 of the second sense amplifier 70 are also half power supply voltages. (HVCC)

Second, when the first word line wl1 is turned on to the high voltage VCC + = VPP as shown in FIG. 12B in the read or write period, the NMOS transistor N10. ) Is turned on and loaded on the bit lines BLL and BLR as a data charge share of the cell, and the data is transferred to the sensing input node S3 of the second sense amplifier 70. As shown in (d) of FIG. 12, the NMOS transistors N26 and N27 are turned off using the ground power supply VSS to sense the sensing inputs of the bit line BL and the second sense amplifier 70. The node S3, the bit line bar BLB, and the sensing input node S4 of the second sense amplifier 70 are isolated.

Thereafter, as shown in FIG. 12E, the first sense amplifier 10 suspended between the sensing input node S1 and the sensing input node S2 is activated with VSP1 and VSN1B to read the first data. The feedback voltage VFB is applied to the power supply voltage VCC as shown in (bar) of FIG. 12, so that the right bit line BLR and the right bit line bar BLRB are connected through the NMOS transistors N24 and N25. By adjusting the coupling amount of the capacitors C9 and C10 according to the voltage, that is, the gate voltages of the NMOS transistors N24 and N25, the sensing input node S3 and the sensing input node (the input of the second sensing) After modification to S4), VSP2 and VSN2B are operated as shown in Fig. 12G to activate the second sense amplifier 70 to read the second data.

Here, the signal VaftSA that is enabled after the primary sensing is normally a ground (GND) ground voltage as shown in FIGS. 12A and 13B, and the NMOS transistors N34 and N35. To be turned off.

In this case, it is also easy to optimize the timing of the feedback voltage VFB operation to the sensing input nodes S3 and S4 which are input signals for secondary sensing.

That is, when the right bit line BLR and the right bit line bar BLRB are maximized, the operation efficiency of the feedback voltage VFB becomes maximum.

Optimization of the feedback voltage VFB operation described above is made, and as shown in Figs. 14 to 17, the data is normally operated with respect to each of the data "11", "10", "01", and "00".

In addition, the problem of equalization between the sensing input nodes S3 and S4 and the node X4 caused by the node X4 is also eliminated.

In addition, the data of the second sensing input margin due to the continuous coupling between the right bit line BLR, the right bit line bar BLRB and the sensing input nodes S3 and S4 by the NMOS transistors N22 and N23. The disproportionate action caused by this is not blocked.

Third, as shown in (a) of FIG. 12 in the restore section, VMT0 remains VCC + and VMT1 becomes the ground power supply VSS to isolate the left bit line bar BLB, and then restore voltage. When the node X4 is "high", the NMOS transistor N21 is turned on according to the potential of the node X4 by applying the VRST to VCC + as shown in FIG. Since the charge of the left bit line BLL, the charge of the right bit line BLR and the charge of the right bit line bar BLRB are shared through the NMOS transistor N21 by making (X1) VCC +. Then, specific voltages (2 / 3VCC, 1 / 3VCC) are generated and restored to the left and right memory cells 20 and 40.

Here, as shown in FIG. 12 (difference) and FIG. 13 (wave), the timing for turning on the NMOS transistors N34 and N35 with VCC is the signal VaftSA that is enabled after the first sensing. After tea sensing is over.

On the other hand, the timing for turning off is as immediately as the restore voltage VRST operates as VCC +, as shown in FIG. 12 and FIG. 13.

Therefore, when the second sensing is started, elements that make a fail in the sensing input nodes S3 and S4 which are the sensing inputs can be completely blocked.

Here, if the data of the cell is (1, 0), that is, 2/3 VCC is stored and read in the cell (finally S1 = VCC, S2 = VSS, S3 = VSS, and S4 = VCC). The equalization signal EQU is disabled as low as shown in FIG. 13A to precharge both the bit line BL and the bit line bar BLB. Then turn off.

At this time, it is assumed that the node X4 is also precharged with the HVCC, and the word line WL1 is turned on as shown in (b) of FIG. 13 to have 2/3 VCCs. The data of 40 is loaded on the bit line BL as charge sharing and is also loaded on the sensing input node S3 of the second sense amplifier 70.

At this time, the data loaded on the bit line BL and the sensing input node S3 is “HVCC + ΔV”, and the sensing of the second sense amplifier 70 with VCT2 “low” as shown in (d) of FIG. 13. After the input nodes S3 and S4 are separated from the bit line BL and the bit line bar BLB, the first sense amplifier 10 is connected by VSP1 and VSN1B as shown in FIG. Activate to read "high" data (S1 = VCC, S2 = VSS) with primary sensing.

At this time, it is natural that the delta V10 has a reduced sensing input margin than when the VCC is stored in the left and right memory cells 20 and 40, as shown in (ta) of FIG. 13.

In addition, since the sensing input nodes S3 and S4 operate after being fully VCC or fully VSS, the node X4 can operate correctly, and the potential of the node X4 exits to the sensing input node S3 when restoring. Sufficient restore operation can be achieved by preventing the phenomenon (eg, when data is "10").

The continuous coupling through the NMOS transistors N22 and N23, which is the cause of the failure according to each data, also indicates that the NMOS transistors N34 and N35 of the isolation transistor 80 are turned off. It is isolated from the sensing input nodes S3 and S4, which are the input stages of the secondary sensing, and thus has no effect at all, thus enabling complete secondary sensing.

As described in detail above, the present invention can effectively deform the secondary sensing input by completely separating the secondary sensing input node in the multilevel sense amplifier circuit, and thus, the effect of securing the input gain can be effectively obtained. have.

Preferred embodiments of the present invention are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, additions, and the like within the spirit and scope of the present invention, and such modifications and changes should be regarded as belonging to the following claims. something to do.

Claims (7)

In each memory cell, two bits of information consisting of a first data value and a second data value have V _cc for (1,1) and 2 / 3V _cc , (0,1) for (1,0). In order to store 1 / 3V _cc , the word line is activated so that the second isolation means for isolating the second sense amplifier after the information of the memory cell is loaded on the bit line, and reading the first data value stored in the memory cell. Is lower than the potential difference between the two input terminals in the case of (1,1) and (0,0) among the two input terminals of the first sense amplifier and the second sense input terminal, and (1,0) and (1, A feedback element that rises to a potential difference higher than the potential difference in the case of 0), the second sense amplifier reading the second data value after the feedback action of the feedback element, and the first sense amplifier after sensing the second sense amplifier. First isolation means for separating the, the first sense amplifier by the first isolation means The first data value and the second data value, which are connected to the switching element and the second sense amplifier, which are selectively bisected into the left and right bit lines or the bit line bars after being compared with each other. In the multi-level sense amplifier having any one of the separated bit line bar or a comparator for distributing charge by connecting any one of the entire bit line bar and the separated bit line, And a separation transistor positioned between the comparator and the second sense amplifier. The method of claim 1, The separation transistor, And controlling the coupling of the comparator and the second sense amplifier after the second sensing by the second sense amplifier is sufficient. The method of claim 1, The separation transistor, And selectively dividing the bit line or the bit line bar for a restore operation, and controlling to isolate the bit line or the bit line bar immediately before operating the restore voltage VRST. The method of claim 1, The separation transistor, A multilevel sensing circuit comprising NMOS transistors. Each memory cell has two bits of information consisting of a first data value and a second data value of V _cc for (1,1) and 2 / 3V _cc , (0,1) for (1,0). In this case, in order to store 1 / 3V _cc , a word line is activated so that information of the memory cell is loaded on a bit line, a second step of isolating a second sense amplifier by a second isolation means, and a first sense. A third step of reading out the first data value stored in the memory cell by an amplifier; and (1,1) and (0,0) the potential of the lower input terminal of the two input terminals of the second sense input terminal by a feedback element. A fourth step of raising the potential difference lower than the potential difference between the two input terminals in the case of (1,0) and higher than the potential difference in the case of (1,0), and reading out the second data value by the second sense amplifier. In a fifth step, a sixth step of separating the first sense amplifier by a first isolation means, switching station A seventh step of selectively dividing the left and right bit lines or the bit line bars into two parts; comparing the first data value and the second data value read by a comparator, and comparing the entire bit lines with the separated bits In the multi-level sensing method comprising the eighth step of distributing charge by connecting any one of the line bar or the entire bit line bar and the separated bit line, And optionally isolating or connecting the comparator and the second sense amplifier after the fifth step. The method of claim 5, The connection operation, And operating after the second sensing by the second sense amplifier is sufficient. The method of claim 5, The isolation operation is And a step of selectively dividing the bit line or the bit line bar for a restore operation and immediately before operating a restore voltage VRST.