KR20000004364A - Forming method of metal wire of a semiconductor device - Google Patents
Forming method of metal wire of a semiconductor device Download PDFInfo
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- KR20000004364A KR20000004364A KR1019980025796A KR19980025796A KR20000004364A KR 20000004364 A KR20000004364 A KR 20000004364A KR 1019980025796 A KR1019980025796 A KR 1019980025796A KR 19980025796 A KR19980025796 A KR 19980025796A KR 20000004364 A KR20000004364 A KR 20000004364A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 26
- 239000002184 metal Substances 0.000 title claims abstract description 26
- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims abstract 2
- 239000010410 layer Substances 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 7
- 239000006117 anti-reflective coating Substances 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 238000005259 measurement Methods 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 다층 금속배선에서의 콘택저항을 감소시킬 수 있는 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a metal wiring of a semiconductor device capable of reducing contact resistance in a multilayer metal wiring.
반도체 디바이스의 고집적화에 따라, 배선 설계가 자유롭고 용이하며, 배선 저항 및 전류용량 등의 설정을 여유있게 할 수 있는 배선 기술에 관한 연구가 활발히 진행되고 있다.BACKGROUND ART With the high integration of semiconductor devices, research on wiring technology that allows free and easy wiring design and allows setting of wiring resistance and current capacity, etc., has been actively conducted.
도 1a 및 도 1b는 종래의 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도이다.1A and 1B are cross-sectional views illustrating a metal wiring forming method of a conventional semiconductor device.
도 1a를 참조하면, 반도체 기판(10) 상에 알루미늄 합금막 또는 텅스텐과 같은 금속막(11)을 형성하고, 그 상부에 금속막(11)의 반사를 방지하기 위하여 TiN막으로 ARC(Anti-Reflective Coating)막(12)을 형성한다. 그런 다음, ARC막(12)과 금속막(11)을 패터닝하여 하부 도전막 패턴(100)을 형성하고, 기판 전면에 층간절연막(13)을 형성한다.Referring to FIG. 1A, to form a metal film 11 such as an aluminum alloy film or tungsten on the semiconductor substrate 10, and to prevent reflection of the metal film 11 thereon, a TiN film is used as an ARC (Anti-). Reflective Coating) film 12 is formed. Then, the ARC film 12 and the metal film 11 are patterned to form the lower conductive film pattern 100, and the interlayer insulating film 13 is formed on the entire substrate.
도 1b를 참조하면, 하부 도전막 패턴(100)의 일부가 노출되도록 층간절연막(13)을 식각하여 콘택홀(14)을 형성한다. 이때, 다른 영역과의 단차를 고려하여 과도식각으로 진행한다. 이에 따라, 식각시 하부 도전막 패턴(100)의 ARC막이 제거된다. 그런 다음, 도시되지는 않았지만, 콘택홀(14)을 통하여 하부 도전막 패턴(100)과 콘택하는 상부 도전막 패턴이 형성된다.Referring to FIG. 1B, a contact hole 14 is formed by etching the interlayer insulating layer 13 to expose a portion of the lower conductive layer pattern 100. At this time, the process proceeds to the excessive etching in consideration of the step with the other area. Accordingly, the ARC film of the lower conductive film pattern 100 is removed during etching. Then, although not shown, an upper conductive layer pattern contacting the lower conductive layer pattern 100 is formed through the contact hole 14.
상기한 종래의 금속배선 형성에 있어서, 콘택홀(14) 형성을 위한 식각은 플로린 계열의 개스를 이용한 물리적 식각으로 진행한다. 그러나, 이러한 물리적 식각은 막을 뜯어내는 방식으로 진행되기 때문에, 도 1b 및 도 3에 도시된 바와 같이, ARC막(12)인 TiN막의 잔류물(12a)이 금속막(11) 상에 존재하여, 콘택홀(14)의 저부의 표면특성이 열악해진다. 이에 따라, 콘택홀(14)의 임계치수(Critical Dimension; CD) 측정이 어려울 뿐만 아니라, 상부 도전막 패턴과의 콘택시 콘택저항이 증가된다. 뿐만 아니라, 식각후 TiN막이 완전히 제거되었는지를 판단하기가 어렵기 때문에, 이러한 문제는 더욱더 심각해진다. 또한, 식각 마스크로서 사용되는 포토레지스트막의 제거 후 발생되는 포토레지스트막 잔류물로 인하여, 후속 공정의 진행시 파티클이 유발될 뿐만 아니라, 콘택저항이 증가된다.In the above-described conventional metallization, the etching for forming the contact hole 14 is performed by physical etching using a florin-based gas. However, since the physical etching proceeds in the manner of tearing off the film, as shown in FIGS. 1B and 3, the residue 12a of the TiN film, which is the ARC film 12, is present on the metal film 11. The surface characteristic of the bottom of the contact hole 14 becomes poor. Accordingly, the critical dimension (CD) measurement of the contact hole 14 is difficult, and the contact resistance when contacting the upper conductive film pattern is increased. In addition, since it is difficult to determine whether the TiN film is completely removed after etching, this problem becomes more serious. In addition, due to the photoresist film residue generated after removal of the photoresist film used as the etching mask, not only particles are generated during the subsequent process but also contact resistance is increased.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 콘택홀 저부의 표면 특성을 향상시켜 콘택홀 크기 측정을 용이하게 함과 더불어 포토레지스트막의 잔류물을 완전히 제거함으로써 콘택저항을 감소시킬 수 있는 반도체 소자의 금속배선 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention is to solve the above-mentioned problems, and to improve the surface characteristics of the bottom of the contact hole to facilitate the measurement of the contact hole size and to completely remove the residue of the photoresist film, thereby reducing the contact resistance. It is an object of the present invention to provide a method for forming metal wiring of a semiconductor device.
도 1a 및 도 1b는 종래의 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도.1A and 1B are cross-sectional views for explaining a metal wiring forming method of a conventional semiconductor device.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도.2A to 2C are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
도 3은 종래의 콘택홀의 CD 모니터링 사진을 나타낸 도면.3 is a view showing a CD monitoring photograph of a conventional contact hole.
도 4는 본 발명의 콘택홀의 CD 모니터링 사진을 나타낸 도면.4 is a view showing a CD monitoring photograph of the contact hole of the present invention.
〔도면의 주요 부분에 대한 부호의 설명〕[Description of Code for Major Parts of Drawing]
20 : 반도체 기판 21, 21a : 금속막20: semiconductor substrate 21, 21a: metal film
22, 22a : ARC막 23, 23a : 폴리실리콘막22, 22a: ARC film 23, 23a: polysilicon film
200 : 하부 도전막 패턴 24 : 산화막200: lower conductive film pattern 24: oxide film
25 : 콘택홀25: contact hole
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속배선은 다음과 같이 형성한다. 먼저, 반도체 기판 상에 금속막, ARC막, 및 폴리실리콘막을 순차적으로 형성하고, 폴리실리콘막, ARC막, 및 금속막을 패터닝하여 하부 도전막 패턴을 형성한다. 그런 다음, 기판 전면에 층간절연막을 형성하고, 폴리실리콘막의 일부가 노출되도록 층간절연막을 식각하여 콘택홀을 형성한 후, 콘택홀을 통하여 하부 도전막 패턴과 콘택하는 상부 도전막 패턴을 형성한다.Metal wiring of the semiconductor device according to the present invention for achieving the above object is formed as follows. First, a metal film, an ARC film, and a polysilicon film are sequentially formed on a semiconductor substrate, and a polysilicon film, an ARC film, and a metal film are patterned to form a lower conductive film pattern. Then, an interlayer insulating film is formed on the entire surface of the substrate, and the interlayer insulating film is etched to expose a portion of the polysilicon film to form a contact hole, and then an upper conductive film pattern contacting the lower conductive film pattern is formed through the contact hole.
본 실시예에서, 폴리실리콘막은 500 내지 2,000Å의 두께로 CVD 또는 노를 이용하여 형성한다. 또한, 층간절연막은 산화막으로 형성하고, 콘택홀을 형성하는 단계에서, 식각은 플로린 계열의 개스를 이용한 건식식각으로 진행한다.In this embodiment, the polysilicon film is formed using CVD or a furnace with a thickness of 500 to 2,000 mm 3. In addition, the interlayer insulating film is formed of an oxide film, and in the forming of the contact hole, etching is performed by dry etching using a florin-based gas.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도이다.2A through 2C are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 반도체 기판(20) 상에 금속막(21) 및 ARC막(22)을 순차적으로 증착한다. 이때, 금속막(21)은 알루미늄 합금막 또는 텅스텐막으로 증착하고, ARC막(22)은 TiN막으로 증착한다. 그런 다음, ARC막(22) 상부에 폴리실리콘막(23)을 화학기상증착(Chemical Vapor Deposition; 이하, CVD) 또는 노(furnace)를 이용하여 약 500 내지 2,000Å의 두께로 증착한다. 폴리실리콘막(23)은 우수한 표면 특성을 갖는 물질로서, 이후 형성되는 산화막 대한 식각 선택비가 1 : 10 이상이다.Referring to FIG. 2A, the metal film 21 and the ARC film 22 are sequentially deposited on the semiconductor substrate 20. At this time, the metal film 21 is deposited by an aluminum alloy film or a tungsten film, and the ARC film 22 is deposited by a TiN film. Then, the polysilicon film 23 is deposited on the ARC film 22 to a thickness of about 500 to 2,000 kPa using chemical vapor deposition (hereinafter, referred to as CVD) or furnace. The polysilicon film 23 is a material having excellent surface properties, and the etching selectivity with respect to the oxide film formed thereafter is 1:10 or more.
도 2b를 참조하면, 폴리실리콘막(23) 상에 포토리소그라피로 포토레지스트막 패턴(미도시)을 형성하고, 폴리실리콘막(23), ARC막(22), 및 금속막(21)을 패터닝하여 하부 도전막 패턴(200)을 형성한다. 그런 다음, 공지된 방법으로 포토레지스트막 패턴을 제거한다. 이때, 폴리실리콘막(23)의 우수한 표면특성에 의해, 포토레지스트막의 잔류물이 발생되지 않고, 완전히 제거된다. 도 2c를 참조하면, 도 2b의 구조 상에 층간절연을 위하여 산화막(24)을 형성하고, 하부 도전막 패턴(200)의 일부가 노출되도록 산화막(24)을 플로린(F) 계열의 개스를 이용한 건식식각으로 식각하여 콘택홀(25)을 형성한다. 이때, 산화막(24)에 대한 폴리실리콘막(23a)의 식각 선택비가 1 : 10 이상이기 때문에, 식각이 과도하게 진행되어도 폴리실리콘막(23a)은 1/2 정도의 두께만 식각된다. 그리고 나서, 콘택홀(25)을 통하여 하부 도전막 패턴(200)과 콘택하는 상부 도전막 패턴(미도시)을 형성한다.Referring to FIG. 2B, a photoresist film pattern (not shown) is formed by photolithography on the polysilicon film 23, and the polysilicon film 23, the ARC film 22, and the metal film 21 are patterned. The lower conductive film pattern 200 is formed. Then, the photoresist film pattern is removed by a known method. At this time, due to the excellent surface characteristics of the polysilicon film 23, no residue of the photoresist film is generated and is completely removed. Referring to FIG. 2C, the oxide film 24 is formed on the structure of FIG. 2B for interlayer insulation, and the oxide film 24 is formed using a florin (F) -based gas so that a part of the lower conductive film pattern 200 is exposed. The contact hole 25 is formed by etching by dry etching. At this time, since the etching selectivity of the polysilicon film 23a with respect to the oxide film 24 is 1:10 or more, the polysilicon film 23a is etched only about 1/2 of the thickness even if the etching proceeds excessively. Then, an upper conductive layer pattern (not shown) that contacts the lower conductive layer pattern 200 is formed through the contact hole 25.
한편, 도면에 도시되지는 않았지만, 폴리실리콘막(23a)을 상부 도전막 패턴의 형성전에 선택적으로 제거할 수 있다. 우선, 하부 도전막 패턴의 형성시 사용되는 Cl2개스와 BCl3개스를 이용하여 인시튜(in-situ) 방식으로 폴리실리콘막(23a)을 제거할 수 있다. 또한, 별도의 제거공정으로 폴리실리콘막(23a)을 제거할 수 있는데, 이러한 경우에는 130 SCCM 이하의 Cl2개스와 100SCCM 이하의 BCl3개스를 이용하여 500W 이하의 최고 파워와 200W 이하의 최저전력하에서, N2개스와 같은 불활성개스(inert gas)를 이용하여 진행한다.Although not shown in the drawings, the polysilicon film 23a can be selectively removed before the upper conductive film pattern is formed. First, the polysilicon film 23a may be removed in-situ using Cl 2 gas and BCl 3 gas used in forming the lower conductive film pattern. In addition, the polysilicon film 23a may be removed by a separate removal process. In this case, a maximum power of 500 W or less and a minimum power of 200 W or less may be achieved using Cl 2 gas of 130 SCCM or less and BCl 3 gas of 100 SCCM or less. Underneath, using an inert gas such as N 2 gas.
상기한 본 발명에 의하면, ARC막 상에 양호한 표면 특성을 가지면서 산화막에 대한 식각 선택비가 높은 폴리실리콘막을 형성하여 ARC막의 노출을 방지한다. 이에 따라, 도 4에 도시된 바와 같이, 콘택홀 저부에 ARC막의 잔류물 발생이 방지되어, 콘택홀 저부의 표면특성 열하가 방지됨으로써, 이후 상부 금속막 패턴과의 콘택시 콘택저항이 감소될 뿐만 아니라, 콘택홀의 CD 측정이 용이해진다.According to the present invention described above, a polysilicon film having good surface properties and high etching selectivity to an oxide film is formed on the ARC film to prevent exposure of the ARC film. Accordingly, as shown in FIG. 4, residues of the ARC film are prevented from occurring at the bottom of the contact hole, thereby preventing deterioration of the surface characteristics of the bottom of the contact hole, thereby reducing contact resistance during contact with the upper metal film pattern. Rather, the CD measurement of the contact hole becomes easy.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
Claims (5)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980025796A KR20000004364A (en) | 1998-06-30 | 1998-06-30 | Forming method of metal wire of a semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980025796A KR20000004364A (en) | 1998-06-30 | 1998-06-30 | Forming method of metal wire of a semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100387761B1 (en) * | 2000-12-12 | 2003-06-18 | 동부전자 주식회사 | Method for providing a metal layer in a semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100387761B1 (en) * | 2000-12-12 | 2003-06-18 | 동부전자 주식회사 | Method for providing a metal layer in a semiconductor device |
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