KR20000004359A - Method for manufacturing a thin film transistor - Google Patents

Method for manufacturing a thin film transistor Download PDF

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KR20000004359A
KR20000004359A KR1019980025791A KR19980025791A KR20000004359A KR 20000004359 A KR20000004359 A KR 20000004359A KR 1019980025791 A KR1019980025791 A KR 1019980025791A KR 19980025791 A KR19980025791 A KR 19980025791A KR 20000004359 A KR20000004359 A KR 20000004359A
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polysilicon
layer
active layer
film
manufacturing
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KR100465637B1 (en
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김연수
전상호
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김영환
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

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  • Thin Film Transistor (AREA)

Abstract

PURPOSE: A fabrication method of polysilicon thin film transistors used in SRAM cell is provided to reduce a trap density of a polysilicon active layer by using PE(plasma enhanced)-TEOS (tetra-ethyl-ortho-silicate) layer as an interlayer dielectric. CONSTITUTION: The method comprises the steps of: forming a gate(11) by depositing a first polysilicon layer on a semiconductor substrate(10) and patterning the polysilicon layer; depositing a gate oxide(12) and a second polysilicon layer and forming an active layer(13) by patterning the second polysilicon layer; and forming a PE-CVD layer(14) as an interlayer dielectric on the active layer(13) by PECVD method, thereby coupling hydrogen ions contained the PE-CVD layer(14) and a silicon dangling bond in the polysilicon active layer(13).

Description

박막 트랜지스터의 제조방법Manufacturing Method of Thin Film Transistor

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 SRAM 셀에서 사용되는 폴리실리콘-TFT의 제조방법에 관하누 것이다.TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a polysilicon-TFT used in an SRAM cell.

반도체 메모리 소자는 기억 방식에 따라 DRAM(Dynamic Random Access Memordy)과 SRAM(Static Random Access Memory)으로 분류된다. SRAM은 DRAM과는 달리 저장된 정보를 주기적으로 리프레시할 필요가 없을 뿐만 아니라 설계가 용이한 장점을 갖는다. 또한, SRAM은 동작속도가 빠르고, 저전력 소모 및 단순동작으로 구동된다.Semiconductor memory devices are classified into a dynamic random access memory (DRAM) and a static random access memory (SRAM) according to a storage method. Unlike DRAM, SRAM does not need to refresh the stored information periodically and has an advantage of easy design. In addition, the SRAM has a high operating speed, low power consumption and simple operation.

일반적으로, SRAM 셀은 2개의 풀다운(pull-down) 소자와, 2개의 억세스(access) 소자 및 2개의 풀업(pull-up)소자로 구성되며, 풀업소자의 형태에 따라 완전 CMOS형, HLR(High load Resistor)형, 및 TFT형의 3가지 구조로 분류된다. 완전 CMOS형 SRAM 셀은 P채널 벌크 모스펫(P-channel bulk MOSFET)이 풀업소자로 사용되고, HLR형 SRAM 셀은 높은 저항을 갖는 폴리실리콘이 풀업소자로 사용되며, TFT형 SRAM 셀은 P 채널 폴리실리콘 TFT가 풀업소자로 사용된다.In general, an SRAM cell is composed of two pull-down devices, two access devices, and two pull-up devices, depending on the shape of the pull-up device. High load resistor) type and TFT type. P-channel bulk MOSFET (P-channel bulk MOSFET) is used as a pull-up device for all CMOS type SRAM cells. TFT is used as a pull-up element.

상기한 바와 같은 SRAM셀에서, 완전 CMOS형 SRAM 셀은 소자의 특성이 가장 우수하고 공정이 단순한 반면, 셀 크기가 커서 대용량의 기억소자에 적용하기가 어려운 단점이 있다. 또한, HLR형 SRAM셀과 TFT형 SRAM셀은 셀 크기를 현저히 줄일수 있기 때문에 기억소자 전용으로 사용되는 반도체 장치에 적용하기가 용이한 반면, 소자의 특성이 우수하지 못하다. 특히, TFT형 SRAM 셀은 액티브층으로 사용되는 폴리실리콘막의 높은 트랩밀도(trap density)로 인하여 채널에서의 캐리어 이동도(carrier mobility) 및 온전류가 낮기 때문에 전기적 특성을 확보하기가 어렵다. 이러한 폴리실리콘막의 높은 트랩밀도를 낮추기 위하여, 고상결정 성장법(Solid Phase Growth; SPG), 실리콘 이온주입, 레이저 어닐링, 및 수소첨가(hydrogenation) 등의 방법이 제시되었으나, 이러한 방법은 별도의 장비 및 추가공정이 요구되기 때문에 제조비용이 높고, 공정이 복잡한 단점이 있다.In the SRAM cell as described above, the fully CMOS type SRAM cell has the most excellent device characteristics and simple process, but has a disadvantage that it is difficult to apply to a large-capacity memory device due to its large cell size. In addition, the HLR type SRAM cell and the TFT type SRAM cell can be easily applied to a semiconductor device used exclusively for a memory device because the cell size can be significantly reduced, but the characteristics of the device are not excellent. In particular, TFT type SRAM cells are difficult to secure electrical characteristics because of low carrier mobility and on-current in the channel due to the high trap density of the polysilicon film used as the active layer. In order to lower the high trap density of the polysilicon film, methods such as solid phase growth (SPG), silicon ion implantation, laser annealing, and hydrogenation (hydrogenation) have been proposed. Since additional processes are required, manufacturing costs are high, and the process is complicated.

따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, SRAM 셀에 적용된 폴리실리콘-TFT를 제조함에 있어서, 별도의 추가공정 및 장비를 사용하는 것 없이, 폴리실리콘막의 트랩밀도를 효과적으로 낮출 수 있는 TFT의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention is to solve the above-described problems, and in manufacturing the polysilicon-TFT applied to the SRAM cell, it is possible to effectively lower the trap density of the polysilicon film without using additional processes and equipment. Its purpose is to provide a method for manufacturing a TFT.

도 1은 본 발명의 실시예에 따른 TFT형 SRAM셀의 TFT 영역을 나타낸 단면도.1 is a cross-sectional view showing a TFT region of a TFT type SRAM cell according to an embodiment of the present invention.

〔도면의 주요 부분에 대한 부호의 설명〕[Description of Code for Major Parts of Drawing]

10 : 반도체 기판 11 : 게이트10 semiconductor substrate 11 gate

12 : 게이트 절연막 13 : 액티브층12 gate insulating film 13 active layer

14 : PE-TEOS 산화막 15 : BPSG막14 PE-TEOS oxide film 15 BPSG film

상기 목적을 달성하기 위한 본 발명에 따른 TFT 소자는 액티브층이 폴리실리콘막으로 이루어진다. 여기서, 폴리실리콘막 상에 층간절연막으로서 PE-TEOS 산화막을 형성하여 PE-TEOS 산화막 내에 함유된 수소이온과 폴리실리콘내의 실리콘 댕글링 본드를 결합시키는 것을 특징으로 한다.In the TFT device according to the present invention for achieving the above object, the active layer is made of a polysilicon film. Here, a PE-TEOS oxide film is formed on the polysilicon film as an interlayer insulating film to bond hydrogen ions contained in the PE-TEOS oxide film with silicon dangling bonds in polysilicon.

바람직하게, PE-TEOS 산화막은 플라즈마 PECVD 방식을 이용하여 250 내지 400℃의 온도와 5 내지 15Torr의 압력하에서 형성한다.Preferably, the PE-TEOS oxide film is formed at a temperature of 250 to 400 ° C. and a pressure of 5 to 15 Torr using a plasma PECVD method.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

도 1은 본 발명의 실시예에 따른 TFT형 SRAM 셀에서 풀업소자로서 사용된 TFT 영역을 나타낸다.1 shows a TFT region used as a pull-up element in a TFT type SRAM cell according to an embodiment of the present invention.

도 1을 참조하면, 워드라인 및 비트라인(미도시)이 형성된 반도체 기판(10) 상에 제 1 폴리실리콘막을 증착하고 패터닝하여 TFT의 게이트(11)를 형성한다. 게이트(11)가 형성된 기판 전면에 게이트 절연막(12)을 형성하고, 그 상부에 제 2 폴리실리콘막(13)을 증착한다. 그런 다음, 제 2 폴리실리콘막(13)을 패터닝하여, 액티브층(13)을 형성하고, 도시되지는 않았지만, 액티브층(13) 내에 소오스 및 드레인을 형성하여, TFT를 형성한다. 그리고 나서, 이후 형성되는 상부 도전층과의 절연을 위하여 기판 전면에 제 1 층간절연막으로서 PE-TEOS 산화막(14)을 형성한다.Referring to FIG. 1, a gate layer 11 of a TFT is formed by depositing and patterning a first polysilicon film on a semiconductor substrate 10 having a word line and a bit line (not shown). A gate insulating film 12 is formed over the entire substrate on which the gate 11 is formed, and a second polysilicon film 13 is deposited on the gate insulating film 12. Then, the second polysilicon film 13 is patterned to form an active layer 13, and although not shown, a source and a drain are formed in the active layer 13 to form a TFT. Then, a PE-TEOS oxide film 14 is formed as the first interlayer insulating film on the entire surface of the substrate to insulate the later formed upper conductive layer.

여기서, PE-TEOS 산화막(14)은 플라즈마 보조 화학기상증착(Plasma Enhanced Chemical Vapor Deposition; PECVD) 방식을 이용하여 250 내지 400℃, 바람직하게 390℃의 저온과 5 내지 15 Torr, 바람직하게 9 Torr의 압력하에서 형성한다. 이때, PE-TEOS 산화막(14) 내에 함유된 수소이온이 액티브층(13)의 폴리실리콘내의 실리콘의 그레인 바운더리로 침투하여 실리콘 댕글링 본드와 결합한다. 이에 따라, 액티브층(13)의 트랩 밀도가 낮아진다. 또한, PE-TEOS 산화막(14)의 형성시 RF 파워를 조절하여 수소이온의 침투정도를 조절할 수 있다. 또한, 수소는 450℃ 이상의 온도에서 결합력이 약화되므로, 상기한 바와 같이 450℃ 이하의 온도에서 형성된 PE-TEOS 산화막(14)은 더 많은 수소이온을 함유한다. 이에 따라, 후속 열처리 공정시 실리콘과 수소와의 추가적인 결합에 의해 트랩 밀도는 더욱더 감소한다.Here, the PE-TEOS oxide layer 14 is a plasma enhanced chemical vapor deposition (PECVD) method using a low temperature of 250 to 400 ℃, preferably 390 ℃ and 5 to 15 Torr, preferably 9 Torr Form under pressure. At this time, the hydrogen ions contained in the PE-TEOS oxide film 14 penetrate into the grain boundaries of silicon in the polysilicon of the active layer 13 to bond with the silicon dangling bond. As a result, the trap density of the active layer 13 is lowered. In addition, the penetration of hydrogen ions may be controlled by adjusting RF power when the PE-TEOS oxide layer 14 is formed. In addition, since hydrogen has a weakening binding force at a temperature of 450 ° C. or higher, the PE-TEOS oxide film 14 formed at a temperature of 450 ° C. or lower as described above contains more hydrogen ions. Accordingly, the trap density is further reduced by additional bonding of silicon and hydrogen in subsequent heat treatment processes.

그 후, PE-TEOS 산화막(14) 상에 제 2 층간절연막으로서 BPSG막(15)을 형성하여 기판의 표면을 평탄화하고, 후속 공정을 진행한다.Thereafter, a BPSG film 15 is formed on the PE-TEOS oxide film 14 as a second interlayer insulating film to planarize the surface of the substrate, and the subsequent process is performed.

상기한 본 발명에 의하면, TFT의 액티브층으로서 작용하는 폴리실리콘막 상에 층간절연막으로서 PE-TEOS 산화막을 형성함에 따라, 별도의 추가공정을 진행하는 것 없이, PE-TEOS 산화막의 형성시 액티층으로 침투되는 수소이온에 의해, 액티브층의 트랩밀도가 낮아진다. 이에 따라, 제조공정이 단순해질 뿐만 아니라 제조비용이 절감되는 효과를 얻을 수 있다. 또한, TFT의 캐리어 이동도 및 온전류가 증가될 뿐만 아니라 누설전류가 방지되어, 결국 TFT의 전기적 특성이 향상된다.According to the present invention described above, by forming a PE-TEOS oxide film as an interlayer insulating film on a polysilicon film serving as an active layer of the TFT, the acti layer during formation of the PE-TEOS oxide film without further processing. By trapping hydrogen ions, the trap density of the active layer is lowered. As a result, not only the manufacturing process may be simplified, but the manufacturing cost may be reduced. In addition, the carrier mobility and the on-current of the TFT are not only increased, but the leakage current is prevented, thereby improving the electrical characteristics of the TFT.

또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (2)

액티브층이 폴리실리콘막으로 이루어진 박막 트랜지스터의 제조방법에 있어서,In the manufacturing method of the thin film transistor which an active layer consists of a polysilicon film, 상기 폴리실리콘막 상에 층간절연막으로서 PE-TEOS 산화막을 형성하여 상기 PE-TEOS 산화막 내에 함유된 수소이온과 상기 폴리실리콘내의 실리콘 댕글링 본드를 결합시키는 것을 특징으로 하는 박막 트랜지스터의 제조방법.And forming a PE-TEOS oxide film as an interlayer insulating film on the polysilicon film to bond hydrogen ions contained in the PE-TEOS oxide film and silicon dangling bonds in the polysilicon. 제 1 항에 있어서, 상기 PE-TEOS 산화막은 플라즈마 PECVD 방식을 이용하여 250 내지 400℃의 온도와 5 내지 15Torr의 압력하에서 형성하는 것을 특징으로 하는 박막 트랜지스터의 제조방법.The method of claim 1, wherein the PE-TEOS oxide film is formed at a temperature of 250 to 400 ° C. and a pressure of 5 to 15 Torr using a plasma PECVD method.
KR10-1998-0025791A 1998-06-30 1998-06-30 Manufacturing Method of Thin Film Transistor KR100465637B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100724573B1 (en) * 2006-01-06 2007-06-04 삼성전자주식회사 Fabrication methods of a semiconductor device having a hydrogen source layer
KR20140011099A (en) * 2012-07-17 2014-01-28 에스케이하이닉스 주식회사 Method for manufacturing semiconductor device

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JP2874175B2 (en) * 1989-03-08 1999-03-24 セイコーエプソン株式会社 Method for manufacturing semiconductor device
US5620906A (en) * 1994-02-28 1997-04-15 Semiconductor Energy Laboratory Co., Ltd. Method for producing semiconductor device by introducing hydrogen ions
KR100280797B1 (en) * 1994-10-07 2001-03-02 김영환 Manufacturing method of semiconductor device
US5686335A (en) * 1996-07-22 1997-11-11 Taiwan Semiconductor Manufacturing Company, Ltd Method of making high-performance and reliable thin film transistor (TFT) using plasma hydrogenation with a metal shield on the TFT channel

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100724573B1 (en) * 2006-01-06 2007-06-04 삼성전자주식회사 Fabrication methods of a semiconductor device having a hydrogen source layer
KR20140011099A (en) * 2012-07-17 2014-01-28 에스케이하이닉스 주식회사 Method for manufacturing semiconductor device

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