KR100280797B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR100280797B1 KR100280797B1 KR1019940025643A KR19940025643A KR100280797B1 KR 100280797 B1 KR100280797 B1 KR 100280797B1 KR 1019940025643 A KR1019940025643 A KR 1019940025643A KR 19940025643 A KR19940025643 A KR 19940025643A KR 100280797 B1 KR100280797 B1 KR 100280797B1
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Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로, 박막 트랜지스터(Thin Film Transistor; TFT) 구조를 갖는 반도체 소자의 제조공정에서 보호막(Passivation Layer)을 3중막(Nitride-Oxide-Nitride)으로 형성함으로써, 박막 트랜지스터의 채널이 형성되는 폴리실리콘막에 존재하는 트랩사이트(Trap Site)를 감소시켜 제품의 성능 및 신뢰성을 향상시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein a passivation layer is formed as a nitride-oxide-nitride in a manufacturing process of a semiconductor device having a thin film transistor (TFT) structure. The present invention relates to a method for manufacturing a semiconductor device capable of improving the performance and reliability of a product by reducing a trap site present in a polysilicon film in which a channel of a transistor is formed.
Description
첨부도면은 본 발명에 의한 반도체 소자 제조방법을 설명하기 위한 소자의 단면도.The accompanying drawings are cross-sectional views of a device for explaining the method of manufacturing a semiconductor device according to the present invention.
〈도면의 주요부분에 대한 부호의 설명〉<Explanation of symbols for main parts of drawing>
1 : 실리콘 기판 2 : 필드 산화막1: silicon substrate 2: field oxide film
3 : 게이트 산화막(NMOS) 4 : 게이트 전극(NMOS)3: gate oxide film (NMOS) 4: gate electrode (NMOS)
5 : N+확산층(NMOS) 6 : 비트라인5: N + diffusion layer (NMOS) 6: bit line
7 : 연결층 8 : 게이트 전극(TFT)7: connection layer 8: gate electrode (TFT)
9 : 게이트 산화막(TFT)9: gate oxide film (TFT)
10 : 폴리실리콘막(TFT의 소오스, 드레인, 채널)10: polysilicon film (source, drain, channel of TFT)
11: 금속배선 12 : 보호막11: metal wiring 12: protective film
12A : 얇은 질화막 12B : 산화막12A: thin nitride film 12B: oxide film
12C : 두꺼운 질화막12C: thick nitride film
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 박막 트랜지스터(Thin Film Transistor ; TFT) 구조를 갖는 반도체 소자의 제조공정에서 보호막(Passivation Layer)을 3중막(Nitride-Oxide-Nitride)으로 형성함으로써, 박막 트랜지스터의 채널이 형성되는 폴리실리콘막에 존재하는 트랩사이트(Trap Site)를 감소시켜 제품의 성능 및 신뢰성을 향상시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, in the manufacturing process of a semiconductor device having a thin film transistor (TFT) structure, a passivation layer is formed as a nitride-oxide-nitride. The present invention relates to a method for manufacturing a semiconductor device capable of improving performance and reliability of a product by reducing trap sites present in a polysilicon film in which a channel of a thin film transistor is formed.
박막 트랜지스터의 채널이 형성되는 폴리실리콘막은 막의 특성상 서로다른 결정 방향을 갖는 무수한 입자와 입자가 만나는 입계(Grain Boundaries)가 존재하게 되며, 이 입계에서는 비정합 원자 배열로 인하여 많은 뎅글링 본드(Dangling Bond)를 갖게된다. 이러한 뎅글링 본드들은 소자의 동작중에 캐리어(Carrier)의 트랩 사이트로 작용하여 트랜지스터의 오프 전류(off current)를 증가시키고, 온/오프 전류비를 감소시키는 원인이 된다.The polysilicon film in which the channel of the thin film transistor is formed has grain boundaries with countless particles having different crystal directions due to the characteristics of the film. Will have These dangling bonds act as a trap site of a carrier during operation of the device to increase the off current of the transistor and reduce the on / off current ratio.
따라서 트랩 사이트가 되는 입계의 길이를 최소화하기 위하여, 폴리실리콘막은 매우 얇은 두께를 가지며, 동시에 조대한 입자구조를 갖는 막으로 증착한다.Therefore, in order to minimize the length of the grain boundary serving as a trap site, the polysilicon film is deposited with a film having a very thin thickness and at the same time having a coarse grain structure.
이러한 구조를 갖는 폴리실리콘막을 증착하는 방법은 550℃ 이하의 저온 상태로 SiH4개스를 열분해하여 비정질 구조의 막을 얇게 증착한 후 저압 상태를 유지한 채 온도를 600℃ 이상으로 상승시켜 열처리를 하므로써, 조대한 입자 구조를 이루며 재결정화하여 폴리실리콘막을 형성하였다. 그러나 조대한 입자 구조를 갖는 폴리실리콘막으로 증착되었다 하더라도 트랩 사이트가 되는 입계는 여전히 존재하며, 입계에서의 비정합 원자 배열로 인하여 뎅글링 본드들이 다수 존재하게 되며, 이는 제품의 성능과 신뢰성을 열화시키는 요인으로 작용된다.In the method of depositing a polysilicon film having such a structure, by thermally decomposing SiH 4 gas at a low temperature of 550 ° C. or lower, a thin film of amorphous structure is deposited and then heated to 600 ° C. or higher while maintaining a low pressure, A polysilicon film was formed by recrystallization with coarse particle structure. However, even when deposited with a polysilicon film having a coarse grain structure, the grain boundary that is a trap site still exists, and due to the misalignment of the atoms at the grain boundary, there are many dangling bonds, which degrades the performance and reliability of the product. It acts as a factor.
따라서, 본 발명은 보호막 형성공정시 수소를 침투시켜 박막 트랜지스터의 폴리실리콘막에 존재하는 뎅글링 본드를 메꾸어 트랩 사이트를 최소화하므로써 제품의 특성을 안정하게 할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention provides a method of manufacturing a semiconductor device that can stabilize the characteristics of the product by minimizing the trap site by filling the dangling bond present in the polysilicon film of the thin film transistor by penetrating hydrogen during the protective film forming process. There is a purpose.
이러한 목적을 달성하기 위한 본 발명의 반도체 소자 제조방법은 매우 얇은 두께와 조대한 입자구조를 갖는 박막 트랜지스터의 폴리실리콘막을 형성하고, 후속 일련의 박막 트랜지스터 소자 제조공정을 완료한 후 제품의 보호막을 형성하는 과정에서 얇은 질화막, 산화막, 두꺼운 질화막(Thin Nitride/Oxide/Thick Nitride) 구조의 3중 보호막(Triple Passivation Layer)을 형성하는 것을 특징으로 한다.The semiconductor device manufacturing method of the present invention for achieving this purpose is to form a polysilicon film of a thin film transistor having a very thin thickness and coarse particle structure, and to form a protective film of the product after completing a series of subsequent thin film transistor device manufacturing process In the process of forming a thin nitride film, an oxide film, a thick nitride film (Thin Nitride / Oxide / Thick Nitride) structure is characterized by forming a triple passivation layer (Triple Passivation Layer).
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
첨부된 도면은 본 발명을 설명하기 위한 실시예로 박막 트랜지스터 구조를 갖는 SRAM 소자를 도시한 단면도이다.The accompanying drawings are cross-sectional views illustrating SRAM devices having a thin film transistor structure as an example for describing the present invention.
실리콘 기판(1)에 필드 산화막(2)을 형성하여 활성영역과 비활성영역을 확정하고, 활성영역에 게이트 산화막(3), 게이트 전극(4), 소오스/드레인용 N+확산층(5)을 형성하여 NMOS 트랜지스터를 구성한다.A field oxide film 2 is formed on the silicon substrate 1 to determine an active region and an inactive region, and a gate oxide film 3, a gate electrode 4, and a source / drain N + diffusion layer 5 are formed in the active region. To configure an NMOS transistor.
NMOS 트랜지스터를 포함한 전체구조 상부에 절연막을 증착한 후 드레인용 N+확산층(5)에 접속되는 비트라인(6)을 형성한다.After the insulating film is deposited over the entire structure including the NMOS transistor, a bit line 6 connected to the drain N + diffusion layer 5 is formed.
비트라인(6)을 포함한 전체구조 상부에 다시 절연막을 증착한 후 소오스용 N+확산층(5)에 콘택홀을 형성하고, 전체구조 상부에 폴리실리콘을 증착한 후 패턴공정을 실시하여 소오스용 N+확산층(5)에 접속되면서 후 공정으로 형성되는 박막 트랜지스터의 소오스에 접속되는 연결층(7)과 박막 트랜지스터의 게이트 전극(8)을 형성한다. 이후 박막 트랜지스터의 게이트 산화막(9)을 형성하고, 그 상부에 조대한 입자 구조를 갖는 폴리실리콘막(10)을 형성한 후 마스크 공정과 BF2불순물 주입공정으로 폴리실리콘막(10)에 소오스, 드레인 및 채널을 형성하고, 이 소오스, 드레인 및 채널영역을 제외한 폴리실리콘막(10)을 식각하여 PMOS 박막 트랜지스터를 구성하되, 폴리실리콘막(10)의 소오스는 상기 연결층(7)에 접속되도록 한다.After depositing an insulating film over the entire structure including the bit line 6, a contact hole is formed in the source N + diffusion layer 5, polysilicon is deposited over the entire structure, and a pattern process is performed to form a source N. The connection layer 7 and the gate electrode 8 of the thin film transistor which are connected to the diffusion layer 5 and connected to the source of the thin film transistor which are formed in a later process are formed. Thereafter, the gate oxide film 9 of the thin film transistor is formed, and a polysilicon film 10 having a coarse particle structure is formed thereon, and then the source and the source of the polysilicon film 10 are subjected to a mask process and a BF 2 impurity injection process. Forming a drain and a channel, and etching the polysilicon film 10 excluding the source, drain and channel region to form a PMOS thin film transistor, wherein the source of the polysilicon film 10 is connected to the connection layer 7. do.
PMOS 박막 트랜지스터를 포함한 전체구조 상부에 절연막을 형성한 후 비트라인(6)에 접속되는 금속배선(11)을 형성하고, 제품을 보호하기 위하여 보호막(12)을 형성한다.After the insulating film is formed over the entire structure including the PMOS thin film transistor, the metal wiring 11 connected to the bit line 6 is formed, and the protective film 12 is formed to protect the product.
보호막(12) 형성공정은 PECVD 방식으로 플라즈마 상태의 SiH4개스와 NH3개스를 이용하여 질화막(12A)을 수백Å 정도로 증착한 후 기존의 방식으로 스트레스가 낮은 산화막(12B)을 증착하고, 계속해서 보호성능이 뛰어난 질화막(12C)을 수천Å으로 두껍게 증착한다.The process of forming the protective film 12 is performed by depositing several hundreds of nitrides of the nitride film 12A using SiH 4 gas and NH 3 gas in the plasma state by PECVD method, and then depositing the oxide film 12B having low stress in the conventional method, and then continuing. Thus, a nitride film 12C having excellent protective performance is deposited to a thickness of thousands of microseconds.
얇은 질화막(12A)을 형성할때, SiH4와 NH3개스가 반응하여 질화막(Si3N4)이 증착되면서 수소가 발생되는데 이 반응식은 하기와 같다.When the thin nitride film 12A is formed, hydrogen is generated as the SiH 4 and the NH 3 gas react to deposit a nitride film (Si 3 N 4 ). The reaction equation is as follows.
3SiH4+ 4NH3 Si3N4+ 12H2 3SiH 4 + 4NH 3 Si 3 N 4 + 12H 2
발생된 수소는 하층 금속배선과 절연막을 통과하여 박막 트랜지스터의 폴리실리콘막(10)으로 침투되어 입계에 자리하게 되는데, 이 수소가 폴리실리콘막(10) 내부의 뎅글링 본드를 메꾸어 트랩 사이트를 감소시킨다. 그리고 증착된 얇은 질화막(12A)은 폴리실리콘막(10)내에 주입된 수소가 외부 확산(out-diffusion)되는 것을 방지한다.The generated hydrogen penetrates into the polysilicon film 10 of the thin film transistor through the lower metal wiring and the insulating film and is located at the grain boundary. The hydrogen fills the dangling bond inside the polysilicon film 10 to reduce the trap site. Let's do it. The deposited thin nitride film 12A prevents out-diffusion of hydrogen injected into the polysilicon film 10.
상술한 바와같이 박막 트랜지스터의 채널이 형성되는 폴리실리콘막에 존재하는 트랩 사이트를 3중 보호막 형성공정으로 최소화시키므로써 제품의 성능 및 신뢰성을 향상시킬 수 있다.As described above, by minimizing the trap site present in the polysilicon film in which the channel of the thin film transistor is formed by the triple passivation layer forming process, the performance and reliability of the product may be improved.
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| KR1019940025643A KR100280797B1 (en) | 1994-10-07 | 1994-10-07 | Manufacturing method of semiconductor device |
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| KR1019940025643A KR100280797B1 (en) | 1994-10-07 | 1994-10-07 | Manufacturing method of semiconductor device |
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| KR960015806A KR960015806A (en) | 1996-05-22 |
| KR100280797B1 true KR100280797B1 (en) | 2001-03-02 |
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| KR100465637B1 (en) * | 1998-06-30 | 2005-04-06 | 주식회사 하이닉스반도체 | Manufacturing Method of Thin Film Transistor |
| KR20020019136A (en) * | 2000-09-05 | 2002-03-12 | 서영거 | Diterpene derivatives and anti-inflammatory analgesic agents comprising the same |
| KR101058113B1 (en) | 2009-11-13 | 2011-08-24 | 삼성모바일디스플레이주식회사 | Thin film transistor and organic light emitting display |
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